CYPRESS PERFORM CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 CYDC064B08 1 8V 4k 8k 16k x 16 and 8k 16k x 8 ConsuMoBL Dual Port Static RAM Features True dual ported memory cells which allow simulta neous access of the same memory location 4 8 16k x 16 and 8 16k x 8 organization High speed access 40 ns Ultra Low operating power Active l cc 15 mA typical at 55 ns Active l cc 25 mA typical at 40 ns Standby l SB3 2
PERFORM CY24272 Rambus XDR Clock Generator with Zero SDA Hold Time Features Meets Rambus Extended Data Rate XDR clocking requirements 25 ps typical cycle to cycle jitter 135 dBc Hz typical phase noise at 20 MHz offset 100 or 133 MHz differential clock input 300 667 MHz high speed clock support Quad open drain differential output drivers Supports frequency multipliers 3 4 5 6 9 2 and 15 4 Spread Aware 2
CY7B991 CY7B992 y CYPRESS PERFORM Programmable Skew Clock Buffer Features All output pair skew lt 100 ps typical 250 maximum 3 75 to 80 MHz output operation User selectable output functions Selectable skew to 18 ns Inverted and non inverted Operation at 1 2 and 1 4 input frequency Operation at 2x and 4x input frequency input as low as 3 75 MHz Zero input to output delay 50 duty cycle outputs Outputs drive 50Q t
CY f7 AU 11CD 4K De embed Audio from HDMI 4K Resolution support HDMI Ops i Cal fie R pitst eam Ss a Loud op 6 wire d E SAFETY PRECAUTIONS Please read all instructions before attempting to unpack install or operate this equipment and before connecting the power supply Please keep the following in mind as you unpack and install this equipment Always follow basic safety precautions to reduce the risk of fire electrical shock and injury to
y CYPRESS PERFORM PRELIMINARY CY14B102L CY14B102N 2 Mbit 256K x 8 128K x 16 nvSRAM Features 20 ns 25 ns and 45 ns Access Times Internally organized as 256K x 8 CY14B102L or 128K x 16 CY14B102N Hands off Automatic STORE on powerdown with only a small Capacitor STORE to QuantumTrap nonvolatile elements initiated by software device pin or AutoStore on power down RECALL to SRAM initiated by software or power up Infinite Read
y CYPRESS PERFORM CY7C1546V18 CY7C1557V18 CY7C1548V18 CY7C1550V18 72 Mbit DDR II SRAM 2 Word Burst Architecture 2 0 Cycle Read Latency Features 72 Mbit density 8M x 8 8M x 9 4M x 18 2M x 36 375 MHz clock for high bandwidth 2 word burst for reducing address bus frequency Double Data Rate DDR interfaces data transferred at 750 MHz at 375 MHz Available in 2 0 clock cycle latency Two input clocks K and K for precise DDR timing
CY8C21634 CY8C21534 CYPRESS _ CY8C21434 CY8C21334 CY8C21234 PSoC Programmable System on Chip Features Powerful Harvard Architecture Processor M8C Processor Speeds to 24 MHz Low power at high speed 2 4V to 5 25V Operating Voltage Operating Voltages Down to 1 0V using On Chip Switch Mode Pump SMP Industrial Temperature Range 40 C to 85 C Advanced Peripherals PSoC Blocks 4 Analog Type E PSoC Blocks provid
CYPRESS PERFORM STK14C88 5 256 Kbit 32K x 8 AutoStore nvSRAM Features 35 ns and 45 ns access times Hands off automatic STORE on power down with externai 68 pF capacitor STORE to QuantumTrap nonvoiatiie eiements is initiated by software hardware or AutoStore on power down RECALL to SRAM initiated by software or power up Unlimited READ WRITE and RECALL cycles 1 000 000 STORE cycles to OuantumTrap 100 year data retention to Oua
CLUX C61C 6 by 1 HDMI V1 3 Switcher with CEC Operation Manual CLUX C61 6x1 HDMI KA Switcher CLUX C61C e Disclaimers The information in this manual has been carefully checked and is believed to be accurate Cypress Technology assumes no responsibility for any infringements of patents or other rights of third parties which may result from its use Cypress Technology assumes no responsibility for any inaccuracies that may be contained in this document Cypres
y CYPRESS PERFORM CY62147DV30 4 Mbit 256K x 16 Static RAM Features Temperature Ranges Industrial 40 C to 85 C Automotive A 40 C to 85 C Automotive E 40 C to 125 C Very high speed 45 ns Wide voltage range 2 20V 3 60V Pin compatible with CY62147CV25 CY62147CV30 and CY62147CV33 Ultra low active power Typical active current 1 5 mA f 1 MHz Typical active current 8 mA f f max Ultra low s
CY7C185 CYPRESS 8K x 8 Static RAM Features High speed 15 ns Fast tQOE Low active power 715 mW Low standby power 220 mW CMOS for optimum speed power _ Easy memory expansion with CE 1 CE 2 and OE features TTL compatible inputs and outputs Automatic power down when deselected Functional Description 111 The CY7C185 is a high performance CMOS static RAM orga nized as 8192 words by 8 bits Easy memory expansio
PERFORM CY7C1317CV18 CY7C1917CV18 CY7C1319CV18 CY7C1321CV18 18 Mbit DDR II SRAM 4 Word Burst Architecture Features 18 Mbit density 2M x 8 2M x 9 1M x 18 512K x 36 300 MHz clock for high bandwidth 4 word burst for reducing address bus frequency Double Data Rate DDR interfaces data transferred at 600 MHz at 300 MHz Two input clocks K and K for precise DDR timing SRAM uses rising edges only Two input clocks for output data C an
CY7C67200 y CYPRESS PERFORM EZ OTG Programmable USB On The Go EZ OTG Features Single chip programmable USB dual role Host Peripheral controller with two configurable Serial Interface Engines SIEs and two USB ports Supports USB OTG protocol On chip 48 MHz 16 bit processor with dynamically switchable clock speed Configurable 10 block supports a variety of 10 options or up to 25 bits of General Purpose 10 GPIO 4K x 16 internal mask ROM c
CY7C1370D CY7C1372D CYPRESS PERFORM 18 Mbit 512K x 36 1M x 18 Pipelined SRAM with NoBL Architecture Features Pin compatible and functionally equivalent to ZBT Supports 250 MHz bus operations with zero wait states Available speed grades are 250 200 and 167 MHz Internally self timed output buffer control to eliminate the need to use asynchronous OE Fully registered inputs and outputs for pipelined operation Byte Write capability
m I KAD FRKF kJ CY7C0837AV CY7C0830AV CY7C0831 AV CY7C0832AV CY7C0832BV CY7C0833AV FLEx18 3 3V 64K 128K x 36 and 128K 256Kx 18 Synchronous Dual Port RAM Features True Dual Ported Memory Cells that Allow Simultaneous Access of the Same Memory Location Synchronous Pipelined Operation Family of 512 Kbit 1 Mbit 2 Mbit 4 Mbit and 9 Mbit Devices Pipelined Output Mode Allows Fast Operation 0 18 micron CMOS for Optimum Speed and Power
y CYPRESS PERFORM CY7C1297H 1 Mbit 64K x 18 Flow Through Sync SRAM Features Functional Description 64K x 18 common I O 3 3V core power supply V DD 2 5V 3 3V I O power supply V DDQ Fast clock to output times 6 5 ns for 133 MHz version Provide high performance 2 1 1 1 access rate User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self time
CY7C68013A CY7C68014A CYPRESS CY7C68015A CY7C68016A EZ USB FX2LP USB Microcontroller High Speed USB Peripheral Controller 1 Features CY7C68013A 14A 15A 16A USB 2 0 USB IF high speed certified TID 40460272 Single chip integrated USB 2 0 transceiver smart SIE and enhanced 8051 microprocessor Fit form and function compatible with the FX2 Pin compatible Object code compatible Functionally compatible FX2LP is a superset U
r if CYPRESS CY7C291A CY7C292A CY7C293A 2K x 8 Reprogrammable PROM Features Windowed for reprogrammability CMOS for optimum speed power High speed 20 ns commercial 25 ns military Low power 660 mW commercial and military Low standby power 220 mW commercial and military EPROM technology 100 programmable Slim 300 mil or standard 600 mil packaging available 5V 10 V cc commercial and military T
y CYPRESS PERFORM CY7C024AV 024BV 025AV 026AV CY7C0241AV 0251AV 036AV 3 3V 4K 8K 16K x 16 18 Dual Port Static RAM Features True dual ported memory cells which enable simultaneous access of the same memory location 4 8 or 16K x 16 organization CY7C024AV 024BV I 1 025AV 026AV 4 or 8K x 18 organization CY7C0241 AV 0251 AV 16K x 18 organization CY7C036AV 0 35 micron CMOS for optimum speed and power High speed access 20 and 25
CY7C1318CV18 CY7C1320CV18 y CYPRESS PERFORM 18 Mbit DDR li SRAM 2 Word Burst Architecture Features 18 Mbit Density 1M x 18 512Kx 36 267 MHz Clock for high Bandwidth 2 word Burst for reducing Address Bus Frequency Double Data Rate DDR Interfaces data transferred at 534 MHz at 267 MHz Two Input Clocks K and K for precise DDR Timing SRAM uses rising edges only Two Input Clocks for Output Data C and C to minimize Clock Skew an