EGG 1232 Microlok Interlocking Simulation System Design Gudielines

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1. EGG 1232 Microlok Interlocking Simulation System Design Gudielines

Engineering Guideline Signals EGG 1232 MICROLOK INTERLOCKING SIMULATION SYSTEM MISS DESIGN GUIDELINES Version 1 2 Issued November 2012 Owner Chief Engineer Signals and Control Systems Approved by Warwick Allison Authorised Paul Szacsvay Chief Engineer by Principal Engineer Signals amp Control Systems Signal Research amp Development Disclaimer E Er 2 O O E St D S O LLI This document was prepared for use on the RailCorp Networ
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