NGMP baseline design - ESA Microelectronics Section

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1. NGMP baseline design - ESA Microelectronics Section

EROFLEX Quad Core LEON4 SPARC V8 Processor v LEON4 NGMP DRAFT GAISLER Data Sheet and User s Manual Features Description e Fault tolerant quad core SPARC V8 integer unit The LEON4 NGMP DRAFT device with 7 stage pipeline 8 register windows 4x4 is a system on chip featuring a quad KiB instruction and 4x4 KiB data caches core fault tolerant LEON4 SPARC V8 Double precision IEEE 754 floating point units processor eight port SpaceWire CPU and I O memory management units 		PDF Manual ENGLISH


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1. NGMP baseline design - ESA Microelectronics Section

EROFLEX Quad Core LEON4 SPARC V8 Processor v LEON4 NGMP DRAFT GAISLER Data Sheet and User s Manual Features Description e Fault tolerant quad core SPARC V8 integer unit The LEON4 NGMP DRAFT device with 7 stage pipeline 8 register windows 4x4 is a system on chip featuring a quad KiB instruction and 4x4 KiB data caches core fault tolerant LEON4 SPARC V8 Double precision IEEE 754 floating point units processor eight port SpaceWire CPU and I O memory management units 		PDF Manual ENGLISH


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