amp XILINX LogiCORE IP Reed Solomon Encoder v7 1 DS251 March 1 2011 Features e Implements many different Reed Solomon coding standards including all ITU T J 83 and CCSDS codes e Automatically configured by user entered parameters e Efficiently handles multiple channels e Fully synchronous design using a single clock e Supports continuous output data with no gap between code blocks e Symbol width from 3 bits to 12 bits e Code block length variable up
amp XILINX LogiCORE IP Interleaver De Interleaver v7 0 DS861 October 19 2011 Introduction The interleaver de interleaver core is appropriate for any application that requires data to be rearranged in an inter leaved fashion including many popular communications standards such as CDMA2000 and DVB Terrestrial T Cable C and Satellite S The multiple configuration mode is particularly useful for standards that require swapping between a number of convolut
Z XILINX LogiCORE IP DSP48 Macro v2 1 DS754 March 1 2011 Introduction The Xilinx LogiCORE DSP48 Macro provides an easy to use interface that abstracts the XtremeDSP slice and simplifies its dynamic operation by enabling the specification of multiple operations via a set of user defined arithmetic expressions The specified operations are enumerated and can be selected by the user via a single port on the generated core Features e Drop in module for Virt
XILINX LogiCORE IP CIC Compiler v3 0 DS845 June 22 2011 Introduction The Xilinx LogiCORE IP CIC Compiler core provides the ability to design and implement AXI4 Stream compliant Cascaded Integrator Comb CIC filters Features e AXI4 Stream compliant interfaces e Decimation or interpolation e Fixed or programmable rate change from 4 to 8192 e Three to six CIC stages e One or two differential delays e Support of signed two s complement input data
amp XILINX LogiCORE IP Binary Counter v11 0 DS215 March 1 2011 Introduction The Xilinx LogiCORE IP Binary Counter core provides LUT and single XtremeDSP slice counter implementations The Binary Counter is used to create up counters down counters and up down counters with outputs of up to 256 bits wide Support is provided for one threshold signal that can be programmed to become active when the counter reaches a user defined count The upper limit of th
XILINX XAPP997 v1 1 June 14 2010 Summary Included Systems Introduction Application Note Embedded Processing Reference Design LogiCORE OPB USB 2 0 Device Author Geraldine Andrews Vidhumouli Hunsigida The application note demonstrates the use of the On Chip Peripheral Bus OPB Universal Serial Bus USB 2 0 Device in a MicroBlaze based reference system This application note describes the e Configuration of the EDK reference system e US
V XI LI NX fegiCUw PLB PCI Full Bridge vl OOa DS508 March 21 2006 Product Specification Introduction The PLB PCI Full Bridge design provides full bridge functionality between the Xilinx 64 bit PLB and a 32 bit Revision 2 2 compliant Peripheral Component Interconnect PCI bus The bridge is referred to as the PLB PCI Bridge in this document The Xilinx PLB is a 64 bit bus subset of the IBM PLB described in the 64 Bit Processor Local Bus Architecture Specification i 3 5
DISCONTINUED PRODUCT LogiCORE IP 1 Gigabit Ethernet MAC v8 5 User Guide UG144 April 24 2009 KXILINX DISCONTINUED PRODUCT HXILINX Xilinx is providing this product documentation hereinafter Information to you AS IS with no warranty of any kind express or impiied Xiiinx makes no representation that the Information or any particuiar impiementation thereof is free from any ciaims of infringement You are responsibie for obtaining any rights