5 SE ae WEIGHT QUALITY MANUAL FOR USE PROGRAMMING AND MAINTENANCE SCALES OF TICKETS AND LABELS 12 AND 20 SELLERS MODEL BC1303 VERSION 14 09 18 5 VERSION 14 09 18 EE WEIGHT QUALITY 1 SCALE COMPONENTES i ves ceesssccccccasccceewssescsccccescoesccuscacveseseveveosecvcveessesexcsecusedesesdssveseecousccesvusscsssecssessseusedsuswereeese 1 1 1 MODEL PL PLANE uu a na bero roe orc oat aseo eode odd radi 1 1 2 MODEL TR
D D s DWE BC with Mezzanines User Manual Board Level Computers for Industrial Applications man mikro elektronik gmbh n rnberg SC13 6U Busless PowerPC SBC with Mezzanines SC13 6U Busless PowerPC SBC with Mezzanines The SC13 is a single board computer for embedded applications based on the Kahlua II PowerPC offering different types of mezzanine slots for industrial and computer I O extensions The SC13 comes with the MPC8245 PowerPC wit
3Com 3Com Router 3000 Ethernet Family Installation Guide 3C13636 www 3Com com Part Number 10014941 Rev AA February 2006 Copyright 2006 3Com Corporation All rights reserved No part of this documentation may be reproduced in any form or by any means or used to make any derivative work such as translation transformation or adaptation without written permission from 3Com Corporation 3Com Corporation reserves the right to revise this documentation and to make c
pi 3Com 3Com Router 5000 Family and Router 6000 Family Module Guide 3C13701 3C13751 3C13755 3C13759 3C13840 3C13880 www 3Com com Part Number 10015049 Rev AA March 2006 Copyright 2006 3Com Corporation All rights reserved No part of this documentation may be reproduced in any form or by any means or used to make any derivative work such as translation transformation or adaptation without written permission from 3Com Corporation 3Com Corporation
Qp 3Com 3Com Router 5000 Family and Router 6000 Family Module Guide 3C13701 3C13751 3C13755 3C13759 3C13840 3C13880 www 3Com com Part Number 10015049 Rev AA March 2006 Copyright 2006 3Com Corporation All rights reserved No part of this documentation may be reproduced in any form or by any means or used to make any derivative work such as translation transformation or adaptation without written permission from 3Com Corporation 3Com Corporation
pi 3Com 3Com Router 5000 Family and Router 6000 Family Module Guide 3C13701 3C13751 3C13755 3C13759 3C13840 3C13880 www 3Com com Part Number 10015049 Rev AA March 2006 Copyright 2006 3Com Corporation All rights reserved No part of this documentation may be reproduced in any form or by any means or used to make any derivative work such as translation transformation or adaptation without written permission from 3Com Corporation 3Com Corporation
Qp 3Com 3Com Router 5000 Family and Router 6000 Family Module Guide 3C13701 3C13751 3C13755 3C13759 3C13840 3C13880 www 3Com com Part Number 10015049 Rev AA March 2006 Copyright 2006 3Com Corporation All rights reserved No part of this documentation may be reproduced in any form or by any means or used to make any derivative work such as translation transformation or adaptation without written permission from 3Com Corporation 3Com Corporation
Qp 3Com 3Com Router 5000 Family and Router 6000 Family Module Guide 3C13701 3C13751 3C13755 3C13759 3C13840 3C13880 www 3Com com Part Number 10015049 Rev AA March 2006 Copyright 2006 3Com Corporation All rights reserved No part of this documentation may be reproduced in any form or by any means or used to make any derivative work such as translation transformation or adaptation without written permission from 3Com Corporation 3Com Corporation
pi 3Com 3Com Router 5000 Family and Router 6000 Family Module Guide 3C13701 3C13751 3C13755 3C13759 3C13840 3C13880 www 3Com com Part Number 10015049 Rev AA March 2006 Copyright 2006 3Com Corporation All rights reserved No part of this documentation may be reproduced in any form or by any means or used to make any derivative work such as translation transformation or adaptation without written permission from 3Com Corporation 3Com Corporation
XZOOl Agilent Acqiris User Manual Family of 8 bit Digitizers For Use with DP and DC Series Digitizers Models covered DP105 DP106 DP110 DP111 DP210 DP211 DP212 DP214 DP235 DP240 DP1400 DC110 DC135 DC140 DC211 DC211A DC240 DC241 DC241A DC265 DC270 DC271 DC271A DC271AR Agilent Technologies User Manual Family of 8 bit Digitizers ZM020010I RevA June 2007 The information in this document is subject to change without notice and may not be c
TV C1300u COLOR TELEVISION TELEVISOR EN COLOR TELEVISEUR COULEUR OPERATING INSTRUCTIONS INSTRUCCIONES DE MANEJ O MODE D EMPLOI f i N For Assistance And Information Call Toll Free 1 800 BUY AIWA _ United States and Puerto Rico ENGLISH ESPANOL FRANCAIS ENGLISH Warning To reduce the risk of fire or electric shock do not expose this appliance to rain or moisture CAUTION RISK OF ELECTRIC SHOCK DO NOT OPEN CAUTION TO REDUCE THE RISK OF
Washer Extractors HC60 HC65 HC75 HC100 HC135 HC165 for corresponding CHC and IHC models see page 6 for complete model list Technical specifications Installation instructions Maintenance A r iiisk lliance Laundry Systems Part No D0285R9 Code 249 00306 20 May 2011 Instruction manual Contents 1 Model Numbers 6 2 Safety and Environmental Informations 8 Safety 8 Environmental 9 Explanation of Safety Messages 10 I
Twelve Hundred LMA lt Gamer Cases The Unbeatable Gaming Case The Antec Twelve Hundred is the evolution of the best selling Nine Hundred expanding on its award winning design with even more cooling capacity and convenience The Twelve Hundred is incredibly robust with 1 2 drive bays 7 expansion slots and space for even the largest graphics cards To keep the most demanding systems nice and cool the Twelve Hundred boasts an unprecedented cooling system with a top mo
Three Hundred P c CASES The Essentially Cool and Quiet Case Impressively spacious and unbeatably reliable the Antec Three Hundred is an unbeatable enclosure The Three Hundred has enough room for an NVIDIA 8800 series graphics card as well as six hard drives and a standardATX motherboard A cable management compartment keeps your system organized and the airflow unobstructed A 1 20mm rear fan and 140mm top fan ensure that the case runs cool even when playing the m
Fusion Remote Max Media Components The Premium Home Theater PC Case Spacious enough for dual graphics cards the Fusion Remote Max enclosure enables you to build the ultimate home theater PC perfect not only for enjoying digital media but for playing the latest games This case features a stylish aluminum front bezel with an LCD a built in IR receiver and a remote control to work the included iMEDIAN HD software If that weren t enough the quiet running 140mm fan and nois
Antec Nine Hundred Gaming Case The most versatile gaming case EVER Introducing the Antec Nine Hundred hardcore gaming case Now you can own any noob ever spawned with this ultra mean case in classic black finish We know your gaming hardware produces a lot of heat that s why the case is built for maximum cool with a perforated front bezel three 120mm fans with mounts for even more fans and a monster top mounted 200mm fan that s right we said 200mm The versatile Nine
ARWir INSTALLATION AND OPERATING INSTRUCTIONS Model DWC13 N HEATED CABINET INTENDED FOR OTHER THAN HOUSEHOLD USE RETAIN THIS MANUAL FOR FUTURE REFERENCE UNIT MUST BE KEPT CLEAR OF COMBUSTIBLES AT ALL TIMES WARNING Improper installation adjustment alteration service or maintenance can cause property damage injury or death Read the Installation Operating and Maintenance Instructions thoroughly before installing or servicing this equipment This equipment has bee
APW INSTALLATION AND OPERATING INSTRUCTIONS Model DWC13 EXPORT WARMER CABINET INTENDED FOR OTHER THAN HOUSEHOLD USE RETAIN THIS MANUAL FOR FUTURE REFERENCE UNIT MUST BE KEPT CLEAR OF COMBUSTIBLES AT ALL TIMES WARNING Improper installation adjustment alteration service or maintenance can cause property damage injury or death Read the Installation Operating and Maintenance Instructions thoroughly before installing or servicing this equipment This equipme
Manual de Instrucciones Garantia limitada Durante un 1 ano a partir de la fecha de compra Aqua Pro Wayne Water Systems reparara o reemplazara segun lo decida para el comprador original cualquier pieza o piezas de sus Bombas para cloacas o Bombas de agua el Producto que despues de un examen sea n haliada s por Aqua Pro como defectuosa s en su material o mano de obra Sirvase llamar a Aqua Pro 877 278 2797 para obtener instrucciones o consulte a su distribuid
C130 User s Guide gt I5K ProXima Ftt CD C Adobe Acrobat pdf y 7 XJl JpjCTiIXttSriTt iS ro fOTT SWiStt i gt a 0 T To 7Ws y b j7x i xx rxiS n xxig Hi c y nXxy yx gt xi HX Xi x J y X X 2 a KjStc InFocus Corporation 27700B SW Parkway Ave Wilsonville Oregon 97070 USA H n y Strawinskylaan 585 1077 XX Amsterdam The Netherlands InFocusTtt EMC Directive 89 336 EEC Amended by 93 68 EEC EMC EN 55022 EN 5502
BUS CUV4X C JumperFree PC133 VC133 AGP 4X Motherboard USER S MANUAL USER S NOTICE No part of this manual including the products and software described in it may be reproduced transmitted transcribed stored in a retrieval system or translated into any language in any form or by any means except documentation kept by the purchaser for backup purposes without the express written permission of ASUSTeK COMPUTER INC ASUS ASUS PROVIDES THIS MANUAL AS IS
SuS CUV4X C JumperFree PC133 VC133 AGP 4X Motherboard USER S MANUAL USER S NOTICE No part of this manual including the products and software described in it may be reproduced transmitted transcribed stored in a retrieval system or translated into any language in any form or by any means except documentation kept by the purchaser for backup purposes without the express written permission of ASUSTeK COMPUTER INC ASUS ASUS PROVIDES THIS MANUAL AS IS
A7V E JumperFree PC133 VC133 200MHz FSB AGP 4X Socket A Motherboard USER S MANUAL USER S NOTICE No part of this manual including the products and software described in it may be reproduced transmitted transcribed stored in a retrieval system or translated into any language in any form or by any means except documentation kept by the purchaser for backup purposes without the express written permission of ASUSTeK COMPUTER INC ASUS ASUS PROVIDES THIS M
CUPLE VM JumperFree PC133 VC133 133 100 66 MHz FSB Socket 370 Motherboard USER S MANUAL USER S NOTICE No part of this manual including the products and software described in it may be reproduced transmitted transcribed stored in a retrieval system or translated into any language in any form or by any means except documentation kept by the purchaser for backup purposes without the express written permission of ASUSTeK COMPUTER INC ASUS ASUS PROVIDES
A7V E JumperFree PC133 VC133 200MHz FSB AGP 4X Socket A Motherboard USER S MANUAL USER S NOTICE No part of this manual including the products and software described in it may be reproduced transmitted transcribed stored in a retrieval system or translated into any language in any form or by any means except documentation kept by the purchaser for backup purposes without the express written permission of ASUSTeK COMPUTER INC ASUS ASUS PROVIDES THIS M
CUPLE VM JumperFree PC133 VC133 133 100 66 MHz FSB Socket 370 Motherboard USER S MANUAL USER S NOTICE No part of this manual including the products and software described in it may be reproduced transmitted transcribed stored in a retrieval system or translated into any language in any form or by any means except documentation kept by the purchaser for backup purposes without the express written permission of ASUSTeK COMPUTER INC ASUS ASUS PROVIDES
A A7V133 M PCI 33 VC 133 200 266 MHz FSB AGP 4X Socket A Motherboard USER S MANUAL USER S NOTICE No part of this manual including the products and software described in it may be reproduced transmitted transcribed stored in a retrieval system or translated into any language in any form or by any means except documentation kept by the purchaser for backup purposes without the express written permission of ASUSTeK COMPUTER INC ASUS ASUS PROVIDES THIS
OPERATOR S MANUAL FOR YOUR BALDOR GENERATORS 3815 OREGON STREET 0 P O BOX 200 0 OSHKOSH Wl 54902 0200 TELEPHONE 920 236 4200 0 FAX 920 236 4219 FORM S PSG 002 25 EFFECTIVE REVISED 6 29 01 D IS09001 FORMS S PSG 002 37 msw FORWARD This manual contains the information you need to safely and efficiently operate your generator set During the preparation of this manual every effort was made to ensure the accuracy of its contents DO NOT OPERATE THIS G
100 USER S MANUAL M B For Socket A Athlon Duron Processor http www bcmcom com 100 Release date January 2001 Year 2000 compliant Trademark Specifications and Information contained in this documentation are furnished for information use only and are subject to change at any time without notice and should not be construed as a commitment by manufacturer TABLE OF CONTENT USER S actas eere
NETWORK SERVICES JULY 2002 IC135A IC1001A IC1000A IC1002A USB Directors RS 232 CUSTOMER SUPPORT INFORMATION Order toll free in the U S Call 877 877 BBOX outside U S call 724 746 5500 FREE technical support 24 hours a day 7 days a week Call 724 746 5500 or fax 724 746 0746 Mailing address Black Box Corporation 1000 Park Drive Lawrence PA 15055 1018 Web site www blackbox com E mail info blackbox com FCC IC RFI STATEMENTS FEDERAL COMMUNICATIONS COMMISSI
Order toll free in the U S 24 hours 7 A M Monday to midnight Friday 877 877 BBOX FREE technical support 24 hours a day 7 days a week Call 724 746 5500 or fax 724 746 0746 Mail order Black Box Corporation 1000 Park Drive Lawrence PA 15055 1018 Web site www blackbox com E mail info blackbox com CUSTOMER SUPPORT INFORMATION FCC AND 1C STATEMENTS FEDERAL COMMUNICATIONS COMMISSION AND INDUSTRY CANADA RADIO FREQUENCY INTERFERENCE STATEMENTS This equipm
SEPTEMBER 2003 IC136C NETWORK SERVICES USB Card CUSTOMER SUPPORT INFORMATION Order toll free in the U S Call 877 877 BBOX outside U S call 724 746 5500 FREE technical support 24 hours a day 7 days a week Call 724 746 5500 or fax 724 746 0746 Mailing address Black Box Corporation 1000 Park Drive Lawrence PA 15055 1018 Web site www blackbox com E mail info blackbox com FCC AND 1C RFI STATEMENTS FEDERAL COMMUNICATIONS COMMISSION AND INDUSTRY CANAD
beaten einen Cinfineon r Motor Control Application Kit For XMC 1000 Family KIT XMC1300 DC 1 XMC1300 Drive Card V1 0 Board User s Manual Revision 1 0 2013 11 05 Microcontroller Edition 2013 11 05 Published by Infineon Technologies AG 81726 Munich Germany 2013 Infineon Technologies AG All Rights Reserved Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics Wi
GREENSTAR CDi WALL HUNG RSF GAS FIRED CONDENSING COMBINATION BOILER FOR SEALED CENTRAL HEATING SYSTEMS AND MAINS FED DOMESTIC HOT WATER THE APPLIANCE IS FOR USE WITH NATURAL GAS OR L P G Cat II 2H3P TYPE C13 amp C33 25CDi GC Number 47 311 92 30CDi GC Number 47 311 93 35CDi GC Number 47 311 94 40CDi GC Number 47 311 95 WORCESTER Bosch Group USER INSTRUCTIONS amp CUSTOMER CARE GUIDE jbenchmar Q CONTACT INFORMATION USER INSTRUCTIONS amp
Bosch Nexxt 100 Series Electric Dryer Model Modele Modelo WTMC1301US WTMC1301CN Operating Care and Installation Instructions Seche linge Notice d utilsation de maintenance et d installation Secadon Operacion cuidado y instrucciones para la instalacion Table of Contents Definitions 3 IMPORTANT SAFETY INSTRUCTIONS 3 GROUNDING INSTRUCTIONS 4 INSTALLATION INSTRUCTIONS 4 Introduction 4 Information concerning waste disposal 4 Before installing
Bosch Nexxt 100 Series Electric Dryer Model Modele Modelo WTMC1301US WTMC1301CN Operating Care and Installation Instructions Seche linge Notice d utilsation de maintenance et d installatidn Secadon Operacion cuidado y instrucciones para la instalacion Table of Contents Definitions 3 IMPORTANT SAFETY INSTRUCTIONS 3 GROUNDING INSTRUCTIONS 4 INSTALLATION INSTRUCTIONS 4 Introduction 4 Information concerning waste disposai 4 Before instailin
CI370 High Capacity Washing Machine 7kg 1400 spin Manual for Installation Use and Maintenance Customer Care Department The ICIDIAI Group Ltd Harby Road Langar Nottinghamshire NG13 9HY T 01949 862 012 F 01949 862 003 E service cda eu W www cda eu lt EN WASHING MACHINE INSTRUCTION MANUAL EN 1 Contents 1 Precautions for safety and use 2 2 Installation instructions 5 3 Description of controls 8 4
CITIZEN USER MANUAL C13D204R 13 TV DVD Combination Colour Television with AC DC Operation www citizen electronics com PRECAUTIONS FCC WARNING This equipment may generate or use radio frequency energy Changes or modifications to this equipment may cause harmful interference unless the modifications are expressly approved in the instruction manual The user could lose the authority to operate this equipment if an unauthorized change or modification
Product Overview 1 1 Specifications User manual English Arabic MHcrpyKuna 3B eKcnjioaTauMfl 6i irapcKM mmn Uzivatelska pnrucka Cestina Handuch Deutsch EvxEipi io EAAnviKQ Manual de Usuario Espanol Manuel de Tutilisateur Frangais Felhasznaloi kezikonyv Magyar Installation Guide Manuals d uso Italiano 0 0 Handleiding Nederlands x hL korean Ko i aHymbi HycKayabiFbi Kazakh Instrukcja Uzytkownika Pol ski Manual do Usuario
Fastwel LE COM gt Express CPC1301 Pentium Core 2 Duo Celeron M Based COM Express Module User Manual Rev 001b E March 2010 The product described in this manual is compliant to all related CE standards Product Title CPC1301 Document Name CPC1301 User Manual Document Version 001b E Source doc ver 1 03 1 06 Copyright 2008 2009 2010 Fastwel Co Ltd All rights reserved Revision Record 001 Initial version CPC1301 October 2008 001a Re
y CYPRESS PERFORM CY7C130 CY7C130A CY7C131 CY7C131A CY7C140 CY7C141 1K x 8 Dual Port Static RAM Features True dual ported memory cells which allow simultaneous reads of the same memory location 1K x 8 organization 0 65 micron CMOS for optimum speed and power High speed access 15 ns Low operating power l cc 110 mA maximum Fully asynchronous operation Automatic power down Master CY7C130 130A CY7C131 131A easily expands d
CY7C1302DV25 CYPRESS PERFORM 9 Mbit Burst of Two Pipelined SRAMs with QDR Architecture Features Separate independent Read and Write data ports Supports concurrent transactions 167 MHz clock for high bandwidth 2 5 ns Clock to Valid access time 2 word burst on all accesses Double Data Rate DDR interfaces on both Read and Write ports data transferred at 333 MHz 167 MHz Two input clocks K and K for precise DDR timing SRA
CY7C1303BV25 CY7C1306BV25 PERFORM 18 Mbit Burst of 2 Pipelined SRAM with QDR Architecture CYPRESS Features Separate independent Read and Write data ports Supports concurrent transactions 167 MHz Clock for high bandwidth 2 5 ns Clock to Valid access time 2 Word Burst on all accesses Double Data Rate DDR interfaces on both Read and Write Ports data transferred at 333 MHz 167 MHz Two input clocks K and K for precise DDR tim
CY7C1305BV25 CY7C1307BV25 PERFORM 18 Mbit Burst of 4 Pipelined SRAM with QDR Architecture CYPRESS Features Separate independent Read and Write data ports Supports concurrent transactions 167 MHz clock for high bandwidth 2 5 ns Clock to Valid access time 4 Word Burst for reducing the address bus frequency Double Data Rate DDR interfaces on both Read and Write Ports data transferred at 333 MHz 167 MHz Two input clocks K and
CY7C1303BV25 CY7C1306BV25 CYPRESS PERFORM 18 Mbit Burst of 2 Pipelined SRAM with QDR Architecture Features Separate independent Read and Write data ports Supports concurrent transactions 167 MHz Clock for high bandwidth 2 5 ns Clock to Valid access time 2 Word Burst on all accesses Double Data Rate DDR interfaces on both Read and Write Ports data transferred at 333 MHz 167 MHz Two input clocks K and K for precise DDR timi
CY7C1305BV25 CY7C1307BV25 PERFORM 18 Mbit Burst of 4 Pipelined SRAM with QDR Architecture CYPRESS Features Separate independent Read and Write data ports Supports concurrent transactions 167 MHz clock for high bandwidth 2 5 ns Clock to Valid access time 4 Word Burst for reducing the address bus frequency Double Data Rate DDR interfaces on both Read and Write Ports data transferred at 333 MHz 167 MHz Two input clocks K and
y CYPRESS PERFORM CY7C130 CY7C130A CY7C131 CY7C131A CY7C140 CY7C141 1K x 8 Dual Port Static RAM Features True dual ported memory cells which allow simultaneous reads of the same memory location 1K x 8 organization 0 65 micron CMOS for optimum speed and power High speed access 15 ns Low operating power l cc 110 mA maximum Fully asynchronous operation Automatic power down Master CY7C130 130A CY7C131 131A easily expands d
y CYPRESS PERFORM CY7C130 CY7C130A CY7C131 CY7C131A CY7C140 CY7C141 1K x 8 Dual Port Static RAM Features True dual ported memory cells which allow simultaneous reads of the same memory location 1K x 8 organization 0 65 micron CMOS for optimum speed and power High speed access 15 ns Low operating power l cc 110 mA maximum Fully asynchronous operation Automatic power down Master CY7C130 130A CY7C131 131A easily expands d
CYPRESS PRELIMINARY CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 18 Mb QDR II SRAM 2 Word Burst Architecture Features Functional Description Separate independent Read and Write data ports Supports concurrent transactions 167 MHz clock for high bandwidth 2 Word Burst on all accesses Double Data Rate DDR interfaces on both Read and Write ports data transferred at 333 MHz 167MHz Two input clocks K and K for precise DDR timing
PERFORM CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18 Mbit QDR II SRAM 2 Word Burst Architecture Features Separate independent read and write data ports Supports concurrent transactions 250 MHz clock for high bandwidth 2 word burst on all accesses Double Data Rate DDR interfaces on both read and write ports data transferred at 500 MHz at 250 MHz Two input clocks K and K for precise DDR timing SRAM uses rising edges o
y CYPRESS PRELIMINARY CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 18 Mb QDR II SRAM 2 Word Burst Architecture Features Separate independent Read and Write data ports Supports concurrent transactions 167 MHz clock for high bandwidth 2 Word Burst on all accesses Double Data Rate DDR interfaces on both Read and Write ports data transferred at 333 MHz 167MHz Two input clocks K and K for precise DDR timing SRAM uses rising edge onl
PERFORM CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18 Mbit QDR II SRAM 2 Word Burst Architecture Features Separate independent read and write data ports Supports concurrent transactions 250 MHz clock for high bandwidth 2 word burst on all accesses Double Data Rate DDR interfaces on both read and write ports data transferred at 500 MHz at 250 MHz Two input clocks K and K for precise DDR timing SRAM uses rising edges o
y CYPRESS PRELIMINARY CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 18 Mb QDR II SRAM 2 Word Burst Architecture Features Separate independent Read and Write data ports Supports concurrent transactions 167 MHz clock for high bandwidth 2 Word Burst on all accesses Double Data Rate DDR interfaces on both Read and Write ports data transferred at 333 MHz 167MHz Two input clocks K and K for precise DDR timing SRAM uses rising edge onl
PERFORM CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18 Mbit QDR II SRAM 2 Word Burst Architecture Features Separate independent read and write data ports Supports concurrent transactions 250 MHz clock for high bandwidth 2 word burst on all accesses Double Data Rate DDR interfaces on both read and write ports data transferred at 500 MHz at 250 MHz Two input clocks K and K for precise DDR timing SRAM uses rising edges o
PERFORM CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 18 Mbit DDR II SRAM 2 Word Burst Architecture Features 18 Mbit density 2M x 8 2M x 9 1M x 18 512K x 36 300 MHz clock for high bandwidth 2 word burst for reducing address bus frequency Double Data Rate DDR interfaces data transferred at 600 MHz at 300 MHz Two input clocks K and K for precise DDR timing SRAM uses rising edges only Two input clocks for output data C an
PERFORM CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 CY7C1320CV18 18 Mbit DDR II SRAM 2 Word Burst Architecture Features 18 Mbit density 2M x 8 2M x 9 1M x 18 512K x 36 267 MHz clock for high bandwidth 2 word burst for reducing address bus frequency Double Data Rate DDR Interfaces data transferred at 534 MHz at 267 MHz Two Input clocks K and K for precise DDR timing o SRAM uses rising edges only Two Input clocks for output data C and
PERFORM CY7C1316JV18 CY7C1916JV18 CY7C1318JV18 CY7C1320JV18 18 Mbit DDR II SRAM 2 Word Burst Architecture Features 18 Mbit density 2M x 8 2M x 9 1M x 18 512K x 36 300 MHz clock for high bandwidth 2 word burst for reducing address bus frequency Double Data Rate DDR interfaces data transferred at 600 MHz at 300 MHz Two input clocks K and K for precise DDR timing SRAM uses rising edges only Two input clocks for output data C an
PERFORM CY7C1317CV18 CY7C1917CV18 CY7C1319CV18 CY7C1321CV18 18 Mbit DDR II SRAM 4 Word Burst Architecture Features 18 Mbit density 2M x 8 2M x 9 1M x 18 512K x 36 300 MHz clock for high bandwidth 4 word burst for reducing address bus frequency Double Data Rate DDR interfaces data transferred at 600 MHz at 300 MHz Two input clocks K and K for precise DDR timing SRAM uses rising edges only Two input clocks for output data C an
PERFORM CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 18 Mbit DDR II SRAM 2 Word Burst Architecture Features 18 Mbit density 2M x 8 2M x 9 1M x 18 512K x 36 300 MHz clock for high bandwidth 2 word burst for reducing address bus frequency Double Data Rate DDR interfaces data transferred at 600 MHz at 300 MHz Two input clocks K and K for precise DDR timing SRAM uses rising edges only Two input clocks for output data C an
PERFORM CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 CY7C1320CV18 18 Mbit DDR II SRAM 2 Word Burst Architecture Features 18 Mbit density 2M x 8 2M x 9 1M x 18 512K x 36 267 MHz clock for high bandwidth 2 word burst for reducing address bus frequency Double Data Rate DDR interfaces data transferred at 534 MHz at 267 MHz Two input clocks K and K for precise DDR timing SRAM uses rising edges only Two input clocks for output data C an
CY7C1318CV18 CY7C1320CV18 y CYPRESS PERFORM 18 Mbit DDR li SRAM 2 Word Burst Architecture Features 18 Mbit Density 1M x 18 512Kx 36 267 MHz Clock for high Bandwidth 2 word Burst for reducing Address Bus Frequency Double Data Rate DDR Interfaces data transferred at 534 MHz at 267 MHz Two Input Clocks K and K for precise DDR Timing SRAM uses rising edges only Two Input Clocks for Output Data C and C to minimize Clock Skew an
CY7C1318CV18 CY7C1320CV18 y CYPRESS PERFORM 18 Mbit DDR li SRAM 2 Word Burst Architecture Features 18 Mbit Density 1M x 18 512Kx 36 267 MHz Clock for high Bandwidth 2 word Burst for reducing Address Bus Frequency Double Data Rate DDR Interfaces data transferred at 534 MHz at 267 MHz Two Input Clocks K and K for precise DDR Timing SRAM uses rising edges only Two Input Clocks for Output Data C and C to minimize Clock Skew an
CY7C1318CV18 CY7C1320CV18 y CYPRESS PERFORM 18 Mbit DDR li SRAM 2 Word Burst Architecture Features 18 Mbit Density 1M x 18 512Kx 36 267 MHz Clock for high Bandwidth 2 word Burst for reducing Address Bus Frequency Double Data Rate DDR Interfaces data transferred at 534 MHz at 267 MHz Two Input Clocks K and K for precise DDR Timing SRAM uses rising edges only Two Input Clocks for Output Data C and C to minimize Clock Skew an
CY7C1318CV18 CY7C1320CV18 y CYPRESS PERFORM 18 Mbit DDR li SRAM 2 Word Burst Architecture Features 18 Mbit Density 1M x 18 512Kx 36 267 MHz Clock for high Bandwidth 2 word Burst for reducing Address Bus Frequency Double Data Rate DDR Interfaces data transferred at 534 MHz at 267 MHz Two Input Clocks K and K for precise DDR Timing SRAM uses rising edges only Two Input Clocks for Output Data C and C to minimize Clock Skew an
CY7C1318CV18 CY7C1320CV18 y CYPRESS PERFORM 18 Mbit DDR li SRAM 2 Word Burst Architecture Features 18 Mbit Density 1M x 18 512Kx 36 267 MHz Clock for high Bandwidth 2 word Burst for reducing Address Bus Frequency Double Data Rate DDR Interfaces data transferred at 534 MHz at 267 MHz Two Input Clocks K and K for precise DDR Timing SRAM uses rising edges only Two Input Clocks for Output Data C and C to minimize Clock Skew an
CY7C1318CV18 CY7C1320CV18 y CYPRESS PERFORM 18 Mbit DDR li SRAM 2 Word Burst Architecture Features 18 Mbit Density 1M x 18 512Kx 36 267 MHz Clock for high Bandwidth 2 word Burst for reducing Address Bus Frequency Double Data Rate DDR Interfaces data transferred at 534 MHz at 267 MHz Two Input Clocks K and K for precise DDR Timing SRAM uses rising edges only Two Input Clocks for Output Data C and C to minimize Clock Skew an
PERFORM CY7C1316JV18 CY7C1916JV18 CY7C1318JV18 CY7C1320JV18 18 Mbit DDR II SRAM 2 Word Burst Architecture Features 18 Mbit density 2M x 8 2M x 9 1M x 18 512K x 36 300 MHz clock for high bandwidth 2 word burst for reducing address bus frequency Double Data Rate DDR interfaces data transferred at 600 MHz at 300 MHz Two input clocks K and K for precise DDR timing SRAM uses rising edges only Two input clocks for output data C an
PERFORM CY7C1317CV18 CY7C1917CV18 CY7C1319CV18 CY7C1321CV18 18 Mbit DDR II SRAM 4 Word Burst Architecture Features 18 Mbit density 2M x 8 2M x 9 1M x 18 512K x 36 300 MHz clock for high bandwidth 4 word burst for reducing address bus frequency Double Data Rate DDR interfaces data transferred at 600 MHz at 300 MHz Two input clocks K and K for precise DDR timing SRAM uses rising edges only Two input clocks for output data C an
y CYPRESS PERFORM CY7C130 CY7C130A CY7C131 CY7C131A CY7C140 CY7C141 1K x 8 Dual Port Static RAM Features True dual ported memory cells which allow simultaneous reads of the same memory location 1K x 8 organization 0 65 micron CMOS for optimum speed and power High speed access 15 ns Low operating power l cc 110 mA maximum Fully asynchronous operation Automatic power down Master CY7C130 130A CY7C131 131A easily expands d
PERFORM CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 18 Mbit DDR II SRAM 2 Word Burst Architecture Features 18 Mbit density 2M x 8 2M x 9 1M x 18 512K x 36 300 MHz clock for high bandwidth 2 word burst for reducing address bus frequency Double Data Rate DDR interfaces data transferred at 600 MHz at 300 MHz Two input clocks K and K for precise DDR timing SRAM uses rising edges only Two input clocks for output data C an
PERFORM CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 CY7C1320CV18 18 Mbit DDR II SRAM 2 Word Burst Architecture Features 18 Mbit density 2M x 8 2M x 9 1M x 18 512K x 36 267 MHz clock for high bandwidth 2 word burst for reducing address bus frequency Double Data Rate DDR interfaces data transferred at 534 MHz at 267 MHz Two input clocks K and K for precise DDR timing SRAM uses rising edges only Two input clocks for output data C an
CY7C1318CV18 CY7C1320CV18 y CYPRESS PERFORM 18 Mbit DDR li SRAM 2 Word Burst Architecture Features 18 Mbit Density 1M x 18 512Kx 36 267 MHz Clock for high Bandwidth 2 word Burst for reducing Address Bus Frequency Double Data Rate DDR Interfaces data transferred at 534 MHz at 267 MHz Two Input Clocks K and K for precise DDR Timing SRAM uses rising edges only Two Input Clocks for Output Data C and C to minimize Clock Skew an
CY7C1318CV18 CY7C1320CV18 CYPRESS PERFORM 18 Mbit DDR II SRAM 2 Word Burst Architecture Features 18 Mbit Density 1M x 18 512Kx 36 267 MHz Clock for high Bandwidth 2 word Burst for reducing Address Bus Frequency Double Data Rate DDR Interfaces data transferred at 534 MHz at 267 MHz Two Input Clocks K and K for precise DDR Timing SRAM uses rising edges only Two Input Clocks for Output Data C and C to minimize Clock Skew an
CY7C1318CV18 CY7C1320CV18 y CYPRESS PERFORM 18 Mbit DDR li SRAM 2 Word Burst Architecture Features 18 Mbit Density 1M x 18 512Kx 36 267 MHz Clock for high Bandwidth 2 word Burst for reducing Address Bus Frequency Double Data Rate DDR Interfaces data transferred at 534 MHz at 267 MHz Two Input Clocks K and K for precise DDR Timing SRAM uses rising edges only Two Input Clocks for Output Data C and C to minimize Clock Skew an
CY7C1318CV18 CY7C1320CV18 y CYPRESS PERFORM 18 Mbit DDR li SRAM 2 Word Burst Architecture Features 18 Mbit Density 1M x 18 512Kx 36 267 MHz Clock for high Bandwidth 2 word Burst for reducing Address Bus Frequency Double Data Rate DDR Interfaces data transferred at 534 MHz at 267 MHz Two Input Clocks K and K for precise DDR Timing SRAM uses rising edges only Two Input Clocks for Output Data C and C to minimize Clock Skew an
CY7C1318CV18 CY7C1320CV18 CYPRESS PERFORM 18 Mbit DDR II SRAM 2 Word Burst Architecture Features 18 Mbit Density 1M x 18 512Kx 36 267 MHz Clock for high Bandwidth 2 word Burst for reducing Address Bus Frequency Double Data Rate DDR Interfaces data transferred at 534 MHz at 267 MHz Two Input Clocks K and K for precise DDR Timing o SRAM uses rising edges only Two Input Clocks for Output Data C and C to minimize Clock Skew and Fl
PERFORM CY7C1316JV18 CY7C1916JV18 CY7C1318JV18 CY7C1320JV18 18 Mbit DDR II SRAM 2 Word Burst Architecture Features 18 Mbit density 2M x 8 2M x 9 1M x 18 512K x 36 300 MHz clock for high bandwidth 2 word burst for reducing address bus frequency Double Data Rate DDR interfaces data transferred at 600 MHz at 300 MHz Two input clocks K and K for precise DDR timing SRAM uses rising edges only Two input clocks for output data C an
PERFORM CY7C1317CV18 CY7C1917CV18 CY7C1319CV18 CY7C1321CV18 18 Mbit DDR II SRAM 4 Word Burst Architecture Features 18 Mbit density 2M x 8 2M x 9 1M x 18 512K x 36 300 MHz clock for high bandwidth 4 word burst for reducing address bus frequency Double Data Rate DDR interfaces data transferred at 600 MHz at 300 MHz Two input clocks K and K for precise DDR timing SRAM uses rising edges only Two input clocks for output data C an
CY7C1324H Wlmw CYPRESS PERFORM 2 Mbit 128K x 18 Flow Through Sync SRAM Features 128K x 18 common I O 3 3V core power supply 3 3V 2 5V I O supply Fast clock to output times 6 5 ns 133 MHz version Provide high performance 2 1 1 1 access rate User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self timed write Async
CY7C1329H CYPRESS PERFORM 2 Mbit 64K x 32 Pipelined Sync SRAM Features Registered inputs and outputs for pipelined operation 64K x 32 common I O architecture 3 3V core power supply 2 5V 3 3V I O operation Fast clock to output times 3 5 ns for 166 MHz device 4 0 ns for 133 MHz device Provide high performance 3 1 1 1 access rate User selectable burst counter supporting Intel Pentium interleaved or linear burst seque
0 CYPRESS PERFORM CY7C1330AV25 PRELIMINARY CY7C1332AV25 18 Mbit 512Kx 36 1 Mbit X 18 Pipelined Register Register Late Write Features Fast clock speed 250 200 MHz Fast access time 2 0 2 25 ns Synchronous Pipelined Operation with Self timed Late Write Internally synchronized registered outputs eliminate the need to control OE 2 5V core supply voltage 1 4 1 9V Vddq supply with Vref of 0 68 0 95V Wide range HSTL I O Levels Si
y CYPRESS PERFORM CY7C1330AV25 PRELIMINARY CY7C1332AV25 18 Mbit 512Kx 36 1 Mbit x 18 Pipelined Register Register Late Write Features Fast clock speed 250 200 MHz Fast access time 2 0 2 25 ns Synchronous Pipelined Operation with Self timed Late Write Internally synchronized registered outputs eliminate the need to control OE 2 5V core supply voltage 1 4 1 9V V DDQ supply with V REF of 0 68 0 95V Wide range HSTL I O Levels S
CYPRESS PRELIMINARY CY7C1333H 2 Mbit Features Can support up to 133 MHz bus operations with zero wait states Data is transferred on every clock Pin compatible and functionally equivalent to ZBT devices Internally self timed output buffer control to eliminate the need to use OE Registered inputs for flow through operation Byte Write capability 64K x 32 common I O architecture Single 3 3V power supply Fast clock to ou
CY7C1334H aHr CYPRESS PERFORM 2 Mbit 64K x 32 Pipelined SRAM with NoBL Architecture Features Functional Description Pin compatible and functionally equivalent to ZBT devices Internally self timed output buffer control to eliminate the need to use OE Byte Write capability 64K x 32 common I O architecture 3 3V core power supply 3 3V 2 5V I O operation Fast clock to output times 3 5 ns for 166 MHz device 4 0 ns
PRELIMINARY CY7C1336H IJHr CYPRESS PERFORM 2 Mbit 64K x 32 Flow Through Sync SRAM Features Functional Description 64K x 32 common I O 3 3V core power supply 3 3V I O supply Fast clock to output times 6 5 ns 133 MHz version 8 0 ns 100 MHz version Provide high performance 2 1 1 1 access rate User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences Separate processor and cont
CY7C1338G CYPRESS PERFORM 4 Mbit 128K x 32 Flow Through Sync SRAM Functional Description The CY7C1338G is a 128K x 32 synchronous cache RAM designed to interface with high speed microprocessors with minimum glue logic Maximum access delay from clock rise is 6 5 ns 133 MHz version A 2 bit on chip counter captures the first address in a burst and increments the address automati cally for the rest of the burst access All synchronous inputs are gated by registers
CY7C1339G CYPRESS PERFORM 4 Mbit 128K x 32 Pipelined Sync SRAM Features Functional Description Registered inputs and outputs for pipelined operation 128K x 32 common I O architecture 3 3V core power supply V DD 2 5V 3 3V I O power supply V DDQ Fast clock to output times 2 6 ns for 250 MHz device Provide high performance 3 1 1 1 access rate User selectable burst counter supporting Intel Pentium interleaved or l
CY7C1344H aHr CYPRESS PERFORM 2 Mbit 64K x 36 Flow Through Sync SRAM Features Functional Description 64K x 36 common I O 3 3V core power supply 3 3V 2 5V I O supply Fast clock to output times 6 5 ns 133 MHz version 8 0 ns 100 MHz version Provide high performance 2 1 1 1 access rate User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences Separate processor and controller addr
CY7C1345G y CYPRESS PERFORM 4 Mbit 128K x 36 Flow Through Sync SRAM Features 128K x 36 common 10 3 3V core power supply V DD 2 5V or 3 3V 10 supply V DDQ Fast clock to output times 6 5 ns 133 MHz version Provide high performance 2 1 1 1 access rate User selectable burst counter supporting Intel Pentium inter leaved or linear burst sequences Separate processor and controller address strobes Synchronous self timed w
CY7C1346H aHr CYPRESS PERFORM 2 Mbit 64K x 36 Pipelined Sync SRAM Features Functional Description Registered inputs and outputs for pipelined operation 64K x 36 common I O architecture 3 3V core power supply 3 3V 2 5V I O operation Fast clock to output times 3 5 ns 166 MHz device Provide high performance 3 1 1 1 access rate User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences
CYPRESS PERFORM CY7C1347G 4 Mbit 128K x 36 Pipelined Sync SRAM Features Fully registered inputs and outputs for pipelined operation 128K X 36 common 10 architecture 3 3V core power supply Vqq 2 5V 3 3V 10 power supply Vqdq Fast clock to output times 2 6 ns for 250 MFIz device User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences Separate processor and controller address strobes S
y CYPRESS PERFORM CY7C1350G 4 Mbit 128K x 36 Pipelined SRAM with NoBL Architecture Features Functional Description Pin compatible and functionally equivalent to ZBT devices Internally self ti med output buffer control to eliminate the need to use OE Byte Write capability 128K x 36 common I O architecture 3 3V power supply V DD 2 5V 3 3V I O power supply V DDQ Fast clock to output times 2 6 ns for 250 MHz devi
CYPRESS _ CY7C1353G PERFORM 4 Mbit 256K x 18 Flow through SRAM with NoBL Architecture Features Supports up to 133 MHz bus operations with zero wait states Data is transferred on every clock Pin compatible and functionally equivalent to ZBT devices Internally self timed output buffer control to eliminate the need to use OE Registered inputs for flow through operation Byte Write capability 256Kx 18 common 10 architecture 2
0 CYPRESS PERFORM CY7C1354CV25 CY7C1356CV25 9 Mbit 256Kx 36 512Kx 18 Pioelined SRAM with NoBL Architecture Features Pin compatible with and functionally equivalent to ZBTTM Supports 250 MHz bus operations with zero wait states Available speed grades are 250 200 and 166 MHz Internally self timed output buffer control to eliminate the need to use asynchronous OE Fully registered inputs and outputs for pipelined operation Byte Wr
y CYPRESS PERFORM CY7C1354CV25 CY7C1356CV25 9 Mbit 256Kx 36 512Kx 18 Pipelined SRAM with NoBL Architecture Features Pin compatible with and functionally equivalent to ZBT Supports 250 MHz bus operations with zero wait states Available speed grades are 250 200 and 166 MHz Internally self timed output buffer control to eliminate the need to use asynchronous OE Fully registered inputs and outputs for pipelined operation Byte Wri
CYPRESS PERFORM CY7C1360C CY7C1362C 9 Mbit 256K x 36 512K x 18 Pipelined SRAM Features Functional Description Supports bus operation up to 250 MHz Available speed grades are 250 200 and 166 MHz Registered inputs and outputs for pipelined operation 3 3V core power supply V DD 2 5V 3 3V I O operation V DDQ Fast clock to output times 2 8 ns for 250 MHz device Provide high performance 3 1 1 1 access rate User
CY7C1361C CY7C1363C y CYPRESS PERFORM 9 Mbit 256K x 36 512K x 18 Flow Through SRAM Features Supports 100 133 MHz bus operations Supports 100 MHz bus operations Automotive 256K x 36 512K x 18 common I O 3 3V 5 and 10 core power supply V DD 2 5V or 3 3V I O power supply V DDQ Fast clock to output times 6 5 ns 133 MHz version Provide high performance 2 1 1 1 access rate User selectable burst counter supporting I
CYPRESS PERFORM CY7C1360C CY7C1362C 9 Mbit 256K x 36 512K x 18 Pipelined SRAM Features Functional Description Supports bus operation up to 250 MHz Available speed grades are 250 200 and 166 MHz Registered inputs and outputs for pipelined operation 3 3V core power supply V DD 2 5V 3 3V I O operation V DDQ Fast clock to output times 2 8 ns for 250 MHz device Provide high performance 3 1 1 1 access rate User
CY7C1361C CY7C1363C 0 CYPRESS PERFORM 9 Mbit 256K x 36 512K x 18 Flow Through SRAM Features Supports 100 133 MHz bus operations Supports 100 MHz bus operations Automotive 256K X 36 512K x 18 common I O 3 3V 5 and 10 core power suppiy Vdd 2 5V or 3 3V I O power supply Vddq Fast clock to output times 6 5 ns 133 MHz version Provide high performance 2 1 1 1 access rate User selectable burst counter supporting Inte
CY7C1364C CYPRESS PERFORM 9 Mbit 256K x 32 Pipelined Sync SRAM Features Registered inputs and outputs for pipelined operation 256K x 32 common I O architecture 3 3V core power supply V DD 2 5V 3 3V I O power supply V DDQ Fast clock to output times 2 8 ns for 250 MHz device Provide high performance 3 1 1 1 access rate User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences Sepa