1983_Mostek_Computer_Products_Data_Book 1983 Mostek Computer Products Data Book

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1983
COMPUTER PRODUCTS
DATA BOOK

Copyright © 1983 Mostek Corporation (All rights reserved)
Trade Ma rks Registered ®
Mostek reserves the right to make changes in specifications at any time and without notice. The information furnished by
Mostek in this publication is believed to be acurate and reliable. However, no responsibility is assumed by Mostek for its use;
nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any
patents or patent rights of Mostek.

PRINTED IN USA March 1983

1983 COMPUTER PRODUCTS DATA BOOK
Table of Contents

TABLE OF CONTENTS

I.
II.

III.

Table of Contents . ................................................................

1-1

General Information
Mostek - Technology for Today and Tomorrow .................... '" .. '" ................ 11-1
U.S. and Canadian Sales Offices ........................................................ 11-5
U.S. and Canadian Representatives ...................................................... 11-6
U.S. and Canadian Distributors .................... '" .. " .............................. 11-7
International Sales Representatives/Distributors .......................................... 11-8
International Marketing Offices ......................................................... 11-9'
European Sales Representatives/Distributors ............................................. 11-9

VMEbus
VME-SBC .......................................................................... 111-1
VME-SASI ......................................................................... 111-13
VME-SIO .......................................................................... 111-23
VME-FDC .......................................................................... 111-33
VME-DRAM ....................................................................... 111-37
MMCPU .................................................•......................... 111-41
VME Baseline System ............................................................... 111-45

IV.

STD-Z80 Bus
STD-Z80 Bus Systems ................................................................ IV-1

IVA.

STD Bus Microcomputer Systems
Matrix 80/0EM .............................................................•...... IVA-1
Matrix 01 0, 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. IVA-11
Matrix 200. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. IVA-19

IVB.

MDX Series Data Processing
MDX-CPU1 and MDX-CPU1A ...................................................•.... IVB-1
MDX-CPU2A ....................................................................... IVB-7
MDX-CPU3 ...................................................................... IVB-15
MDX-CPU4 ...................................................................... IVB-21
MDX-Math ...................................................................... IVB-29
MD-SBC1 ....................................................................... IVB-35

IVC.

MDX Series Input/Output
MDX Series System Interrupt Units (SIU) Table .......................................... IVC-l
MDX-FLP2 ......................................................................... IVC-3
MDX-SASI-1 ....................................................................... IVC-9
MDX-~ASI-2 ................. " ................................................. " IVC-15
MDX-488 ........................................................................ IVC-23
MDX-ISIO ....................................................................... IVC-25
MDX-SI02 ....................................................................... IV'C-27
MDX-4221 ....................................................................... IVC-47
MDX-422N ...................................................................... IVC-51
RSCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. IVC-55
RIOC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. IVC-63
DIOB1 .......................................................................... IVC-71
DIOP ...................................•.......•....•......•.................... IVC-77
MDX-PIO ....................................................•...•............... IVC-89

1-1

IVD.

MD Series Memory
MOX-ORAM .••......................................................•............. IVO-1
MOX-EPROM/UART ................................. : ................•............. IVO-7
MOX-UMC .•..•.................................................................. IVO-17
MOX-UMC2 ..................................................................... IVO-23
MOX-BRAM ..................................................................... IVO-29
MOX-RAM 64/128 .......................................•......................• IVO-33

IVE.

MD Series Special Functions
MOX-OEBUG ...................................................................... IVE-1
MOX-INT ..........................................•............................... IVE-7
MOX-SC/O ...•................................................................... IVE-13
MOX-PFO ....•................................................................... IVE-17
MOX-BCLK ...•.................................................................... IVE-21

IVF.

M 0 Series Accessories
MO-ACC .......................................................................... IVF-1
Matrix 80/0EM Printer Cable ........................................................ IVF-9
MOX-CPU3/4 Printer Cable ......................................................... IVF-11
MO-PWR1 ........................................................................ IVF-13
MO-RMC12 ....................................................................... IVF-15
HMOFSS ......................................................................... IVF-19
Enclosure ......................................................................... IVF-25

V.

SO Series Data Processing
SOE-Combo ......................................................................... V-1
OEM-80E .......................................................................... V-15
OCC-80E .................................................................•........ V-19
FLP-80E ........................................................................... V-25
RAM-80E .......................................................................... V-29
VOI-80E ........................................................................... V-33

V!.

SDE Series Accessories
sOE-Acc ........................................................................... VI-1
SOE-RMC6 ..................................................................•...... VI-5

VII.

Development Systems
Radius ............................................................................ VII-1
AIM 68000 ........................................................................ VII-5
. AIM Z80BE ....................................................................... VII-11
AIM 7XE .......................................................................... VII-15
EPP-1 .......................................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •. VII-19
Matrix 80/S0S ..........................•......................................... VII-25
EVAL 70 ......................................................................... VII-29
PPG 8/16C .............................................. ; ........................ VII-33
Oewelopment System Ordering Guide ................................................. VII-35

1-2

VIII.

Application Notes
Interfacing Mostek's MDX-PIO to Opto-22 BP24 App. Note #1 ............................. VIII-1
MD-RMC12/MD-RMC12-50 App. Note #2 ...•......................................... VIII-5
MDX-CPU2A App. Note #3 .......................................................... VIII-11
Reset Circuit for MDX-CPU1 A App. Note #4 ........................................... VIII-13
Customizing MDX-CPU3 PROMs App. Note #5 ......................................... VIII-17
Upgrading from MDX-FLP1 to MDX-FLP2 App. Note #6 ....•............................ VIII-23
MDX-SASI1: The Hard Disk Interface App. Note #7 ..................................... VIII-27
MDX-FLP2 vs. MDX-FLP1: Hardware and Software Issues App. Note #B .................. VIII-35
MDX-CPU3/41/0 Drivers App. Note #10 ............................................. VIII-39
Pro-Log MOOD Universal PROM Programmer with the STD-ZBO Bus App. Note #11 ......... VIII-55

IX.

Software Products
M/OS-SO ......•....•.•....................................................•....... IX-1
MOSGEN ..................•...............................•........................ IX-5
ASM-6S000 ........................................................................ IX-7
Microsoft ......................... , ................................................. IX-9
CRASM ...•....................................................................... IX-11
MOD-LIB .......................................................................... IX-13

X.

Integrated Digital Systems
8200 ...............................................................•............... X-1

1-3

1-4

1983 COMPUTER PRODUCTS DATA BOOK
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Mostek - Technology For Today And Tomorrow

Mostek goal is meeting specificatiolls the
first time on every product. This goal requires
a collective discipline from the company as
well as individual efforts. Discipline, coupled
with very personal pride, has enabled
Mostek to build in quality at every level of
production.

TECHNOLOGY
From its beginning, Mostek has been an
innovator. From the developments ofthe 1 K
dynamic RAM and the single-chip calculator
in 1970 to the current 64K dynamic RAM,
Mostek technological breakthroughs have
proved the benefits and cost-effectiveness of
metal oxide semiconductors. Today, Mostek
represents one of the industry's most .
productive bases of MOS/LSI technology,
including Direct-Step-on-Wafer processing.
The addition of the Microelectronics
Research Center in Colorado Springs adds a
new dimension to Mostek circuit design
capabilities. Using the latest computer-aided
design techniques, center engineers are
keeping ahead of the future with new
technologies and processes.

PRODUCTION CAPABILITY
The commitment to increasing production
capability has made Mostek one of the
world's largest manufacturers of dynamic
RAMs. Mostek capital expenditures as a
percentage of sales are one of the highest in
the industry, enabling us to provide high
volumes of quality state-of-the-art products.

THE PRODUCTS
QUALITY
Memory Products
The worth of a product is measured by
how well it is designed, manufactured and
tested, and by how well it works in your
system.
In design, production and testing, the

Through innovations in circuit design,
wafer processing and production, Mostek
has become one of the 'industry's leading
suppliers of dynamic RAMs.

11-1

Military Products
An extension of the high quality in
fabrication and design inherent in Mostek's
product line allows many of our ICs to be
made available screened to MIL-STD-883. In
addition, select parts are qualified to the
rigors of MIL-M-38510 and are processed on
our QPL certified lines.
The MKB product line begins with the
complete memory products offering, and
extends into microprocessors and gate
arrays. Leadless Chip Carrier (LCC)
packaging and prepared customer SCDs
address the particular needs of the military
community.

Examples of Mostek leadership are
families of x1 and x8 high-performance
static RAMs and our extremely successful
64K ROMs with more codes processed than
any other mask-ROM in the industry.
Another performance and density milestone
is our 256K ROM, the MK38000.
Advanced circuit techniques and design
used in our fast MK4564 64K dynamic RAM
enhance manufacturability to satisfy the
demands of a huge marketplace. This year
Mostek introduced a new generation of 64K
dynamic RAMs, operating at previously
unheard-of speeds and breaking yet another
barrier in VLSI technology.

Telecommunications Products
Mostek is a leading supplier of tone
dialers, pulse dialers and CODEC devices.
As each new generation of telecommunications systems emerges, Mostek is
ready with new generation components,
including PCM filters, tone decoders,
repertory dialers, new integrated tone
dialers, and pulse dialers.
These products, many of them using
CMOS technology, represent the most
modern advancements in telecommunications component design.

Memory Systems
Taking full advantage of our leadership in
memory components technology, Mostek
offers a broad line of memory systems
products, all with the performance and
reliability to match our industry-standard
circuits. Mostek offers add-in memory boards
for popular DEC, Data General, and PerkinElmer minicomputers.
Mostek also offers general-purpose and
custom memory boards for special
applications.

Industrial Products
Mostek's line of Industrial Products offers
a high degree of versatility per device. This
family of components includes various
microprocessor-compatible AID converters,

11-2

a counter/time-base circuit for the division
of clock signals, and combined
counter/display decoders. A low parts count
provides an economical alternative to
discrete logic systems.

Mostek MATRIXTM Development System is a
stand-alone hardware and software debug
and integration system.

Microcomputer Components

Mostek is the world's leading manufacturer of Z80-based STD BUS system
components. This year Mostek introduced a
new line of microsystems using the VMEbus
and based on the MK68000.
Computer systems include our MATRIX
line, which uses STD BUS cards to let you
custom-design your own system.

Microcomputer Systems

Mostek's microcomputer components
cover the entire spectrum of microcomputer
applications.
Our MK68000 16-bit microprocessor
family is designed for high-performance,
memory-intensive systems.
Our Z80 is today's industry-standard 8-bit
microprocessor. The Mostek 3870 family of
single-chip microcomputers offers upgrade
options in ROM, RAM and I/O-all in the
same socket. The MK38P70 EPROM
piggyback microcomputer emulates the
entire family and is ideal for low-volume
applications.
Development systems include the
RADIUSTM remote development station that
lets you use your host minicomputer to
develop the applications software. The
program is then downloaded into the
RADIUS which then lets you perform realtime in-circuit emulation and debug. The

Semicustom Circuits
Using the technology developed by Mostek
and United Technologies' Microelectronics
Research Center, Mostek is the leader in
semicustom circuit design. The Mostek
HIGHLANDsM Design System is one of the
most user-friendly, highly-automated, stateof-the-art semicustom circuit development
tools in the industry. Mostek combines this
highly-developed CAD system with highvolume CMOS production capability,
enabling us to offer you quality gate arrays at
a low cost.
11-3

11-4

U.S. AND CANADIAN SALES OFFICES

CORPORATE HEADQUARTERS
Mostek Corporation
1215 W Crosby Rd.
P.O Box 169
Carrollton, Texas 75006

o REGIONAL OFFICES
Northeastern Area
Mostek

777 West Putnam
Greenwich, Conn. 06830
203/531-1146
TWX 710-579-2928

Northeast U.S.
Mostek
29 Cummings Park, SUite #426
Woburn, Mass. 01801

617/935-0635
TWX 710-348-0459

Southeast U.S.

813/962-8338
TWX 81 0-876-4611

313/348-8360

408/287-5080

TWX 810-242-1471

TWX 910-338-2219

Central U.S.
Mostek
4100 McEwen Road
SUite 151
Dallas, Texas 75234

Seattle Region
Mostek
1107 North East 45th St
SUite 411
Seattle, WA 98105

Upstate NY Region
Mostek
4651 Crossroads Park Dr., SUite 201
Liverpool, NY 13088

315/457-2160
TWX 710-945-0255

Northern California
Mostek
1762 Technology Drive
SUite 126
San Jose, Calif. 95110

214/386-9340

206/632-0245

TWX 910-860-5437

TWX 910-444-4030

Chicago Region

Southwest Region

Southern California

Mostek
Two Crossroads of Commerce
SUite 360
Roiling Meadows, III. 60008

Mostek
4100 McEwen Road
SUite 237
Dallas, Texas 75234

Mostek
18004 Skypark Circle
Suite 140
Irvine. Calif 92714

714/549-0397

312/577-9870

214/386-9141

TWX 910-291-1207

TWX 910-860-5437

TWX 910-595-2513

Chevy Chase #4
7715 Chevy Chase Dr, SUite 116
Austin, TX 78752

Mostek
2150 East Highland Ave.
SUite 101
PhoeniX, A2. 85016

Arizona Region

Southeastern Area
Mostek
4001 B Greentree Executive Campus
Route #73
Marlton, New Jersey 08053

Western Region

Michigan
Mostek
Orchard Hill Place
21333 Haggerty Road
SUite 321
NOVI, MI 48050

Mostek
13907 N. Dale Mabry Highway
SUlte2Ql
Tampa, Flonda 33618

North Central U.S.
Mostek
6101 Green Valley Dr
Bloomington, Mn. 55438

609/596-9200

612/831-2322

TWX 710-940-0103

TWX 910-576-2802

512/458-5226
TWX 910-874-2007

11-5

602/954-6260
TWX 910-957-4581

u.s.

AND CANADIAN REPRESENTATIVES

ALABAMA
Conley & Associates, Inc
3322 Memorial Pkwy., S W.

GEORGIA
Conley & Associates, Inc
3951 Pleasantdale Road

Suite 17

Suite 201

Huntsville, AL 35801

205/882-0316
lWX 810-726-2159

Doraville, GA 30340
414/447-6992
TWX 810-766-0488

ARIZONA

ILLINOIS

Summit Sales
7825 E Redfield Rd
Scottsdale, AZ 85260
6021998-4850
TWX 910-950-1283

Carlson Electronic" Sales
Associates, Inc
600 East Higgins Road
Elk Grove Village, !L6Q007
312/956-8240
TWX 910-222-1819

CALIFORNIA
Harvey King, Inc.
8124 Miramar Road
San Diego, CA 92126
714/566-5252
TWX 910-335-1231

COLORADO

INDIANA
Rich Electronic Marketing'"
599 I nd ustrial Drive
Carmel, IN 46032
317/844-8462
TWX 810-260-2631

Waugaman Associates"
4800 Van Gordon
Wheat Ridge, CO 80033
303/423-1020
TWX 910-938-0750

Rich Electronic Marketing
3448 West Taylor St
Fort Wayne, IN 46804
219/432-5553
TWX 810-332-1404

CONNECTICUT

IOWA

New England Technical Sales
240 Pomeroy Ave
Meriden, CT 06450
203/237-8827
TWX 710-461-1126

REP Associates
980 Arica Ave
Marion, IA 52302
319/393-0231

FLORIDA

Rush & West Associates*
107 N. Chester Street
Olathe, KN 66061
9131764-2700
Wichita 316/683-0206
TWX 910-749-6404

Conley & ASSOCiates, Inc .,
P.O. Box 309
235 S. Central
Oviedo, FL 32765
305/365-3283
TWX 810-856-3520

KANSAS

KENTUCKY

MASSACHUSElTS
New England Technical Sales"
135 Cambridge Street
Burlington, MA 01 803
617/272-0434
TWX 710-332-0435
Computer Marke,ting
241 Crescent 5t 12nd Floor
Waltham, MA 02154
617/894-7000
710-324-1503

MICHIGAN

MINNESOTA

Tn-Tech Electronics, Inc
3215 East Main St
Endwell, NY 13760
607/754-1094
TWX 510-252-0891

Cahill, Schmitz & Cahill, Inc *
315 N. Pierce
St Paul, MN 55104
612/646-7217
TWX 910-563-3737
Micro Resources, Inc
2700 Chowen Avenue South
Minneapolis: MN 55416

Tn-Tech ElectroniCS, Inc.
14 Westview Dr.
Fishkill, NY 12524
914/897-5611

OHIO

MISSOURI
Rush & West ASSOCiates
481 Melanie Meadows lane
BallWin, MO 63011
314/394-7271

NORTH CAROLINA
Conley & Associates, Inc.
4050 Wake Forest Road
Suite 102
Raleigh, NC 27609
919/876-9862
TWX 510-928-1829

Conley & ASSOCiates, Inc.

MARYLAND

Trltek Sales, Inc
21 E Euclid Ave
Haddonfield, NJ 08033
609/429-1551
215/627-0149 (Philadelphia Line)
TWX 710-896-0881

Arbotek Associates
3600 St Johns Lane
Ellicott City, MD 21043
301/461-1323
TWX 710-862-1874

Waugaman ASSOCiates
P.O Box 14894
Albuquerque, NM 87111

NEW JERSEY

NEW MEXICO

0'

9004 Menaul NE
SUite 7
Albuquerque, NM 87112
505/294-1437
505/294-1436 (Ans. Service)

~Home

Tn-Tech Electronics, Inc.'"
6836 East Jenesse St
Fayetteville, NY 13066
315/446-2881
TWX 710-541-0604Trl-Tech Electronics, Inc
590 Perinton Hills Office Park
Fairport NY 14450
716/223-5720
TWX 510-523-6356

Conley & ASSOCiates, Inc
4021 W. Waters
Suite 2
Tampa, FL 33614
813/885-7658
TWX 810-876-9136

1612 N w. 2nd Avenue
Boca Raton, FL 33432
305/395-6108
TWX 510-953-7548

516/543-0510
TWX 510-226-1485
(New Jersey Phone Ii
800/645·5500, 5501)

Action Components
21333 Haggerty Road
SUite 201
Novi, MI 48050
313/349-3940

Rich ElectrOnic Marketing
8819 Roman Court
P.O. Box91147
LOUisville. KY 40291
502/499-7808
TWX 81 0-535-3757

PO. Sox 700

NEW YORK
ERA Inc
354 Veterans Memorial Highway
Commack, NY 11725

Office

11-6

The Lyons Corp
4812 Fredenck Rd.
Dayton, OhiO 45414
513/278-0714
TWX 810-459-1754
The Lyons Corp
4615 N. Streetsboro Rd.
Richfield, Ohio 44286
216/659-9224
TWX 810-427-9103

OREGON
Northwest Marketing Assoc
9999 SW. Wilshire St
Suite 124
Portland OR 97225
503/297-2581
TELEX 910-464-5157

TENNESSEE
Co!"'ley & ASSOclates, Inc
1128 Tusculum Blvd
SUite D
Greenville, TN 37743
615/639-3139
TWX 810-576-4597

UTAH
Waugaman Associates
10332 South 1540 W
South Jordan, UT 84065
801/254-0570
0'

801-254-0572
TWX 910-925-4073

WASHINGTON
Northwest Marketing Assoc.*
128:35 Bellevue-Redmond Rd.
Suite 203E
Bellevue, WA 98005
206/455-5846
TWX 910-443-2445

WiSCONSIN
Carlson Erectronk" Sales
Associates, Inc
Northbrook Exe~utive Ctr
10701 West Nor.th Ave.
,Suite 209
Milwaukee, WI 53226
414/476-2790
TWX 910-222-1819

CANADA
Cantec Representatives Inc .,
1573 Laperriere Ave
Ottawa, Ontario
Canada K1Z 7T3
613/725-3704
TWX 610-562-8967
Cantec Representatives Inc
15 Charles Street East
Kitchener, Ontario
Canada N2G2P3
5191744-6341
TWX 610-492-2683 (Toronto)
Cantec Representatives Inc.
8 Strathearn Ave, Unit 18
Brampton, Ontario
Canada L6T4L8
4161791-5922
TWX 610-492-2683
Cantec Representatives Inc
3639 Sources Blvd
SUite 116
Dollard Des Ormeaux, Quebec
Canada H9B2K4
514/683-6131
TWX 610-422-3985

U.S. AND CANADIAN DISTRIBUTORS
ALABAMA

COLORADO

Schweber ElectrOnics
2227 Drake Avenue S.W.
SUite 14
Huntsville, ALA 35805

Arrow Electronics

205/882-2200

2121 South Hudson St.
Denver, CO 80222
3031758-2100
TWX 910/931"()552

ARIZONA

7060 S. Tucson Way

Klerulff Electronics
4134 E. Wood St.
PhoeniX, AZ 85040

602/243·4101
TWX 910/951-1550
Kierulff Electronics
1806 W. Grant Rd.
SUite 102
Tucson, A.Z 85705

602/624-9986
TWX 910/952-1119
CALIFORNIA
Arrow Electronics
4029 Westerly Place
Bldg. 15, Unit 113
Newport Beach, CA 92660

714/851·8961
TWX 910/595-2861
Arrow Electronics
19748 Dearborn St.
Chatsworth, CA 9131 1

2131701-7500
,1WX 910-493-2086
Arrow Electronics
9511 Ridgehaven Court
San Diego, CA 92123

714/565-4800
TWX 910/335-1195
Arrow Electronics
521 Weddell Or.
Sunnyvale, CA 94086

4081745-6600
TWX 910/339·9371
Klerulff Electronics
2585 Commerce Way
Los Angeles, CA 90040

213/725-0325
TWX 910/580-3106
Kierulff ElectrOnics
3969 E. Bayshore Rd.
Palo Alto, CA 94303

415/968-6292
Kierulff Electronics
8797 Balboa Avenue
Sa n Diego, CA 92123

Kierulff Electronics

408/748-4700
ZeuslWest, Inc.
1130 Hawk Circle
Anaheim, CA 92807

714/632-6880
TWX 910/591-1961

TWX 9101764-0882
Kierulff Electronics
2608 Metro Park Blv'd.
Maryland Heights, MO 63043

1536 landmeler Rd.

617/935-5134
TWX 710/390-1449

312/364·3750

TWX 710/332-1387
Schweber Electronics
25 Wiggins Avenue
8edford, MA 01730

203/265· 7741
TWX 710/476-0162
Kierulff Electronics
169 N. Plains Industrial Rd.
Wallingford, CT 06492
203/265-1115
TWX 7101476-0450
Schweber Electronics
Finance Drive
Commerce Industrial Park
Danbury, CT 06810

203/792-3742
TWX 710/456-9405
FLORIDA
Arrow Electronics
1001 N.W. 62nd St.
Suite 108
Ft. Lauderdale, FL 33309

305/776-7790
TWX 510/955-9456

INDIANA
Advent Electronics
8446 Moller
Indianapolis, IN 46268

317/872·4910
TWX 810/341 -3228
Arrow Electronics
2718 Rand Road
Indianapolis, IN 46241

317/243·9353
TWX81O/341-3119
Pioneer Electronics
6408 Castleplace Drive
Indianapolis, IN 46250

317/849-7300
TWX 8101260- 1794

Arrow Electronics
50 Woodlake Dr.
Palm Bay, FL 32905

IOWA
Advent Electronics
682 58th Avenue
Court South West
Cedar Rapids, IA 52404

305/725-1480

319/363·0221

TWX 510-959-6337
Klerulff Electronics
4850 N. State Road F
Suite E
Ft. Lauderdale, FL 33319

TWX 910/525-1337
Arrow Electronics
1930 St. Andrews Or., NE
Cedar Rapids, IA 52402

305/486-4004

Schweber Electronics
5270 North Park Place, N.E.
Cedar Rapids, IA 52402

Kierulff Electronics
3247 Tech Drive
St. Petersburg, FL 33702

813/576-1966
TWX 810/863·5625
Schweber ElectrOnics
2830 North 28th Terrace
Hollywood, FL 33020
Schweber Electron1cs
181 Whooping Loop
Altamonte Spnngs, FL 32701
(Orlando)

714/556-3880

Klerulff Electronics
13 Fortune Drive
Billerica, MA 01 865

617/933-8130
TWX 710/393-6770

Elk Grove Village, IL 60007
312/640·0200
TWX 910/222-0351
Schweber Electronics
904 Cambridge Dr.
Elk Grove Village, IL 60007

TWX 910/335-1182
Kierulff Electronrcs
14101 Franklin Avenue
Tustin, CA 92680

TWX 910/595-1720
Schweber Electronics
3110 Patrick Henry Dr.
Santa Clara, CA 95050

MISSOURI
Arrow Electronics
2380 Schuetz Road
St. Louis, MO 63141

3031790-4444
CONNECTICUT
Arrow Electronics
12 Beaumont Rd.
Wallingford, CT 06492

714/278-2112

Schwaber ElectrOniCs
17811 Gillette Avenue
Irvine, CA 92714

312/893-9420
TWX 910/291-3544
Kierulff Electronics

MASSACHUSETTES
Arrow ElectroOics
Arrow Drive
Woburn, MA alSo.

Englewood, CO 80112

305/927-0511

714/731-5711
TWX 910/595-2599

ILLINOIS
Arrow Electronics
492 Lunt Avenue
P. O. Box 94248
Schaumburg, IL 60193

305/331·7555
GEORGIA
Arrow Electronics
2979 Pacific Drive
Norcross, GA 30071

4041449·8252
TWX 810/766-0439
Kierulff Electronics'
5824 E. Peachtree Corner East
Norcross, GA 30093

404/447·5252
Schweber Electronics
303 Research Drive, SUIte 210
Norcross, GA 30092

404/449-9170

319/395-7230

319/373-1417
KANSAS
Schweber Electronics
Wycliff Commercial Center
10300 West 103rd Street
Suite 103 Building F
Overland Park, KS 66214

913/492-2921
MARYLAND
Arrow Electronics
4801 Benson Avenue
Baltimore, MD 21227
3011247-5200
TWX 7101236·9005
Kierulff Electronics
202 Azar Court
Benson Business Center
Baltimore, MD 21227
3011247-5020
Pioneer Electronics
9100 Gaither Road
GaIthersburg, MO 20877

301/948-0710
TWX 710/828-0545
Schweber Electronics
'·9218 .Gaither Rd.
Gaithersburg, MD 20877

301/840·5900
TWX 710/828-9749

11-7

Lionex Corporation
1 North Avenue
Burlington, MA 01 803

617/272-1660

617/275·5100
TWX 710/326-0268
Zeus/New England, Inc.
25 Adams Street
Burlington, MA01803

6171273·0753

314/567-6888

314/739-0855
TWX 9101762-0721
Olive Electronics
9910 Page 8lvd.
St. Louis, MO 63132

314/426·4500
TWX 9101763·0720
Schweber Electronics
502 Earth City Expressway
SUite 203
Earth City, MO 63045

314/739-0526
Semiconductor Spec
3805 N. Oak Trafficway
Kansas City, MO 64116

816/452-3900

TWX 710/322-0716

TWX 910/771-2114

MICHIGAN
Arrow Electronics
3810 Varsity Drive
Ann Arbor, MI 48104

NEW HAMPSHIRE
Arrow Electronics
1 Perimeter Rd.
Manchester, NH 03103

313/971-8220
1WX 810/223-6020
Pioneer Electronics
13485 Stamford
Livonia, MI 48150

313/525·1800
TWX 810/242-3271
Schweber Electronics
10260 Hubbard Ave.
liVOnia, MI48150

313/525·8100
TWX 810/242·2983
MINNESOTA
Arrow Electronics
5230 W. 73rd Street
Edina, MN 55435

612/830·1800
TWX 910/576-3125
Kierulff Electronics
7667 Cahill Rd.
Edina, MN 55435

612/941-7500
TWX 910/576-2721
Schweber Electronics
7422 Washington Ave., South
Eden Prairie, MN 55343

6121941-5280
TWX 910/576-3167

6031668-6968
TWX 710/220·1684
Schwaber Electronics
Farms Bld'g #2 1st Floor
Kilton & South River Road
Manchester, NH 03102

603/625-2250
NEW JERSEY
Arrow Electron1cs
Pleasant Valley Avenue
Morrestown, NJ 08057

6091235·1900
TWX 7101897-0829
Arrow Electronrcs
2 Industrial Ad.
Fairfield, NJ 07006

201/575-5300
Kierulff Electronics
3 Edison Place
Fairfield, NJ 07006

201/575-6750
TWX 7101734-4372
Schweber Electronics
18 Madison Road
Fairfield, NJ 07006

2011227-7880
TWX 7101734-4305
NEW MEXICO
Arrow ElectroniCS
2460 Alamo Ave. S.E.
Albuquerque, NM 87106

505/243-4566
TWX 910/989-1679

U.S. AND CANADIAN DISTRIBUTORS

NEW YORK

Add Electronic
7 Adler Drive
E. Syracuse, NY 13067

315/437·0300
Arrow Electronics
900 Broad Hollow Rd.
Farmingdale, U., NY 11735
516/694-6800
TWX 5101224-6494
Arrow Electronics
7705 Malttage Drive
P. O. Box 370
Liverpool. NY 13088
315/652-1000
TWX 710/545-0230
Arrow Electronics

3000 S. Winton Road
Rochester, NY 14623

716/275-0300
TWX 510/253-4766
Arrow Electronics
20 Oser Ave.
Hauppauge. NY 11787

516/231-1000
TWX 5101227 -6623
Lionex Corporation
400 Oser Ave.
Hauppauge, NY 11787
5161273-1660
TWX 5101227 -, 042
Schweber Electronics
3 Town Line Circle
Rochester, NY 14623

716/424-2222
Schweber Electronics
Jericho Turnpike
Westbury, NY 11590

516/334-7474

TWX 510/222-3660
Zeus/Long Island
401 Broad Hollow Rd.
Melville. NY 11746

516/752-9551
TWX 710/567-1248
Zeus Components Components, Inc.
100 Midland Avenue
Port Chester, NY 10573

914/937 -7400
TWX 710/567-1248
NORTH CAROLINA
Arrow Electronics
938 Burke St.
Winston Salem, NC 27102
919/725-8711
TWX 510/931-3169
Arrow Electronics
3117 Poplarwood Court
Suite 123, P.O. Box 95163
Raleigh, NC 27625
TWX 919/876-3132
Hammond Electronics
2923 Pacific Avenue
Greensboro, NC 27406
919/275-6391
TWX 510/925-1094

NORTH CAROLlNA(CONT)
Kierulff Electronics
1800 #E Fairfax Road
Greensboro, NC 27407
919/852-9440
TWX 510/922-7384
Schweber ElectrOniCS
1 Commerce Center
5285 North Blv:d.
Raleigh, NC 27604
919/876-0000
OHIO
Arrow Electromcs
7620 McEwen Road
Centervilie, OH 45459
513/435-5563
TWX 810/459-1011
Arrow Electronics
6238 Cochran Road
Solon, OH 44139
216/248-3990
lWX 810/427-9409
Kierulff Electronics
23060 Miles Road
Cleveland, OH 44128
216/587-6558
TWX 810/427-2282
Pioneer Electronics
4800 East 131 st Street
Cleveland, o.H 441 O~
216/587-3600
TWX 810/422-2211
Pioneer Electronics
4433 Interpoint Blvd.
Dayton, OH 45424
513/236-9900
TWX 810/459-1622
Schweber Electronics
23880 Commerce Park Road
Beachwood, OH 44122
216/464-2970
TWX 810/427-9441
Schweber Electronics
7865 Paragon Road
Suite 210
Dayton, OH 45459
513/439-1800
OKLAHOMA
Kierulff Electronics
12318 E. 60th St.
Tulsa. OK 74145
918/252-7537
Quality Components
9934 East 21 st South
Tulsa, OK 74129

918/664-8812
OREGON
Klerulff Electronics
14273 NW Science Park
Portland. OR 97229
503/641-9150
TWX 910/467-8753

PENNSYLVANIA
Arrow Electronics
650 Seco Rd.
Monroeville, PA 15146
4121856-7000
Pioneer ElectrOnics
560 Alpha Drive
Pittsburgh. PA 15238
4121782-2300
TWX 710/795-3122
Pioneer Electronics
261 Gibraltar
Horsham, PA 19044
215/674-4000
TWX 510/665-6778
Schweber Electronics
231 Gibraltar Rd.
Horsham, PA 19044
215/441-0600
Schweber Electronics
1000 R.I.D.C. Plaza
Suite 203
Pittsburgh, PA 15238
412/782-1600
SOUTH CAROLINA
Hammond Electronics
1035 lowndes Hill Rd.
Greenville, SC 29602
803/233-4121
TWX 810/281 -2233
TEXAS
Arrow Electronics
10125 Metropolitan Dr.
Aust;n, TX 78758
512/835-4180
Arrow Electronics
13715 Gamma Road
Dallas, TX 75240
214/386-7500
1WX 910/860-5377
Arrow Electronics
10700 Corporate Drive
Suite 100
Stafford, TX 77477
713/491-4100
TWX 910/880-4439
Kierulff Electronics
3007 longhorn elv'd.
Suite 105
Austin, TX 78758
5121835-2090
TWX 910/874-1359
Kierulff Electronics
9610 Skillman Ave.
Dallas, TX 75243
214/343-2400
TWX 910/861-9149
Kierulff Electronics
10415 Landsbury Dr.
Suite 210
Houston, TX 77099
713/530-7030
TWX 910/880-4057
Quality Components
4257 Kellway Circle
Addison, TX 75001
214/387-4949
TWX 910/860-5459

TEXAS(CONT)
Quality Components
2427 Rutland Drive
Austin, TX 78758

512/835-0220
TWX 910/874-1377
Quality Components
6126 Westline
Houston, TX 77036
713/772-7100
Schweber Electronics
4202 Beltway Drive
Dallas, TX 75234
214/661-5010
TWX 910/860-5493
Schweber Electronics
10625 Richmond
Suite 100
Houston, TX 77042

7131784-3600
TWX 910/881-4836
Zeus/Dallas, Inc
14001 Goldmark Dr
Suite 250
Dallas, TX 75240
214/783-7010
TWX 910/867-9422

UTAH
Arrow Electromcs
4980 Amelia Earhart Dr.
Salt Lake City, UT 84116
801/539-1135
Kierulff Electronics
2121 South 3600 West
Salt Lake City, UT84119
801/973-6913
WASHINGTON
Arrow Electronics
14320 NE 21st
Bellevue, WA 98005
206/643-4800
TWX 910/444-2017
Klerulff Electronics
1053 Andover Park East
Tukwila, WA 98188
206/575-4420
TWX 910/444-2034
Zeus/West
23701 150th S.E.
Monroe, WA 98279
WISCONSIN
Arrow Electronics
434 Rawson Avenue
Oak Creek, WI 53154
414/764-6600
TWX 9101262-1193
Kierulff Electronics
2212 E. Moreland 8lvd.
Waukesha, WI 53186
4141784-8160
TWX 910/265-3653
Schweber Electronics
150 Sunnyslope Road
Suite 120
Brookfield, WI 53005
414/784-9020

*Franchised for USA and Canada excluding California for military products

CANADA
Prelco Electronics
2767 Thames Gate Drive
Mississauga, Ontario
Toronto l4T 1 G5
416/678-0401
TWX 610/492-8974
Prelco Electronics
480 Port Royal St. W.
Montreal 357 P.Q. H3l 2B9

514/389-8051
TWX 610/421-3616
Prelco ElectrOnics
1770 Woodward Drive
Ottawa, Ontario K2C OP8
613/226-3491
Telex 05-34301
RAE. Industrial
3455 Gardner Court
Burnaby, B.C. V5G 4J7
604/291-8866
TWX 610/929-3065
Zentronlcs
141 Catherine Street
Ottawa, Ontario
K2P le3

6131238-6411
Zentronics
8 Tilbury Court
8rampton, Ontarto
l6T3T4 (Toronto)
416/451-9600
Telex 06-97678
Zentronics
505 Locke St.
St. laurent, Quebec
H4T IX7

5141735-5361
Telex 058-27535
Zentronics
590 8erry Stre~
St. James, Manitoba
R2H OR4
204/775-8661
Zentronics
480 "AU Dutton Drive
Waterloo, Ontario
N2L4C6
519/884-5700
RAE. Industrial
11680 170th St.
Edmonton, Alberta T5S 1J7
403/451-4001
Telex 03-72653
Zentronics
550 Cambie St.
Vancouver, B.C. V6B 2N7

604/688-2533
Telex 04507789
Zentronics
3651 21st Street, N.E.
Calgary, Alberta T2E 6T5
403/230-1422
Zentronics
9224 27th Avenue
Edmonton, Alberta T6N 182
403/463-3014
Zentronics
30 Sommonds Drive, Unit B
Dartmouth, N.S. B3B 1R3
902/463-8411

INTERNATIONAL SALES REPRESENTATIVES AND DISTRIBUTORS
ARGENTINA
Rayo Electronics S.RL
Belgrano 990, Pisos 6y2
1092 Buenos Aires
(381-1779.37-9476
Telex: 122153

BRASIL
Casels, ltd.
Rua da Consolacao. 867
Conj.31
01301 Sao Pa ulo

(55111-257.35.35/258.43.25
Telex - 1130869

AUSTRAUA
Amtron Tyree PIy.Ltd.
176 Botany Street
Waterloo, N.S.W. 2017
(61169-89.666
Telex - 25643

ISRAEL
Telsys ltd.
12, Kahilat Venetsia St.
69010 Tel-Aviv
(31494891-2.494881-2
Telex: 032392

JAPAN
Systems Marketing, Inc.
4th Floor, Shindo Bldg.
3-12-5 Uchikanda,
Chiyoda-Ku,
Tokyo, 100
(8113-254.27.51
Telex - 25276
KOREA
Vine Overseas Trading Corp.
Room 308 Korea Electric
Association Bldg.
11 -4 Supyo-Dong Jung-Ku
Seoul
(8212-66-1663
Telex: 24154

11-8

NEW ZEALAND
E.C.S. Div. of Airsperes
P.O. Box 1048
Airport Palmerston North
(771-047
Telex - 3766

SINGAPORE
Dynamar International, lTD.
Suite 526, Cuppage Road
Singapore. 0922
Telex: 26283
SOUTH AFRICA
Radiokom
P.O. Box 56310
Pinegowrie, 2123,
Transvaal
789-1400
Telex: 424822

TAIWAN
Dynamar Taiwan Limited
P.O. Box 67-445
2nd Floor, No. 14, Lane 164
Sung-ChIang Road
Taipei
5418251
Telex: 511064
FOR ALL OTHER COUNTRIES
Mostek Corporation
International Dept.
1215 West Crosby Road
(07158166.121545
Carrollton, Texas 75006, USA

214/466-6000
Telex: 4630093

INTERNATIONAL MARKETNG OFFICES
EUROPEAN HEAD OFFICE
Mostek International
Av de Tervuren 270-272 Bte 21
8-1150 Brussels/Belgium

02/762.1880
Telex. 62011
FAR EAST
Mostek Asia Ltd.
Kam Chung Commercial Bldg.
19 Hennessy Rd. 11/FL
p.a Box 20786 Hong Kong
Phone: 5.296.886
Telex: 72585 MKHK

FRANCE
Mostek France s.a.r.l.
35 Rue de Mantjean

ZAC. Sud. Senders 504
F-94266 Fresnes Cedex

(1)666.21.25
Telex: 204049

PLZ 8 Mostek GmbH
Frelschutzstrasse 92

0-8000 Muiichen 81
(089195. '0.71
Telex. 5216516

ITALY
Mostek ttalla SAL
Via F.D. Guerraul 27
1-20145 Milano

(02)318.5337/349.2696
and 34.23.89
Telex: 333601

GERMANY
PLZ , -5 Mostek GmbH
Friedlandstrasse 1
0-2085 Quickborn

HONG KONG
Mostek Asia LTD.
19 Hennessy Rd.
Karn Chung, Camm. Bldg. l1/Fl
P.O. Box 20786
Wanchal, Hong Kong

(04106)2077178

8525296886

Mostek Japan KK
Sanyo Bldg. 3F
1-2-7 Kita-Aoyama
MlOato-Ku, Tokyo 107

TeleX' 213685

Telex' 72585

(03)404-7261

PLZ 6-7 Mostek GmbH
Schurwaldstrasse 15
0-7303 Neuhausen/Filder
(07158) 66.45
Telex: 72.38.86

IRELAND
Mostek Ireland B.V.
Irish Sales Office
Snugboro Industrial Park
Blanchardstown, Co Dublin

JAPAN

Telex: J23686

SWEDEN
Mostek Scandinavia AS
Spjulvagen 7
S-' 7561 JlIrfalia
Sweden
08-362820
Telex: 12997
UNITED KINGDOM
Mostek U,K. Ltd.
Masons House,

'-3 Valley Drive
Kingsbury Road
London, N,W.9

01-2049322
Telex: 25940

(1)2'7333
Telex: 30958

EUROPEAN SALES REPRESENTATIVES AND DISTRIBUTORS

AUSTRIA
Transistor Vertriebsges, mbH
Auhofstrasse 41 A
A-1130 Vienna

(02221829451. 829404

Mecodis
33-35, Rue Pierre Brossolette
F-94000 Creteil
(1)898.-1",
Telex: 250303

Raffel-Electronic GmbH
Lochnerstrasse 1
0-4030 Ratingen 1
(02102) 280.24
Telex: 8585180

P.E.P.
4 Rue Barthelemy
F-92120 Montrouge

Siegfried Ecker
Koenigsberger Strasse 2
0-6120 Michelstadt
(06061) 2233
Telex: 4191630

Telex: 0133738
BELGIUM
Sotronic
14 Rue Pere De Deken
B-1040 Brussels

DENMARK
Semicap APS
AlhambraveJ 3
OK-1826 Kobenhavn V
01-22.15.10
Telex: 15987
FINLAND
Insele Oy
Kumpulantie 1
SF-00520 Helsinki 52
0735774
Telex: 122217
FRANCE
Copel
Rue Fourny, Z.I.
B.P. 22, F-78530 BUe

(')96610.'8
Telex: 698965
Facen
110AvdeFIandre
F59290 Wasquehal. Nord

(' )-735.33.20
Telex: 204534
Sca.lb
80 Rue d'Arcueil
SILlC 137
F-94523 Rungls Cedex

(11-687.23.'3
Telex: 204674

Positron GmbH
Benzstrasse 1
Postfach 100364
0-7016 Gertingen
Tel: (07156) 3560
Telex: 7245266

NORWAY
Satt ElectroniCS AlS
Sandviksveien, 12
N-1322 Hovik
02-12.36.00
Telex: 72558
PORTUGAL
olgicontrole LOA
Av. de Roma 105
Sexto Esquerdo
1700 Lisboa

Sorhodis
150-152, Rue A. France
F-691 00 Vdleurbanne

Branch offices in:
Hamburg, Dusseldorf, Munchen

('9)682428

(7)8850044

Matronic GmbH
Lichtenberger Wag 3
0-7400 Tubingen

SPAIN
Come Ita S.A.
Emilio Munoz 41, ESC 1
Planta 1 Nave 2
Madrid·17
01-7543001
Telex: 42007

Telex: 380181
GERMANY
Dr Dohrenberg
Bayreuther Strasse 3
0-1000 Berlin 30

(030)213.80.43
Telex: 0184860

(07071)4503'
Telex: 7262879
oema-Electronic GmbH
Turkenstrasse 11
0-8000 Munchen 2

(089) 2724053
CES-Vertriebs-GmbH
Schillerstrasse 14
0-2085 QUickborn
(04106)612-1
Telex: 0213.590

(20)98.92.' 5
Branch Offices in
Lille, Lyon,
Nancy, Rouen, Strasbourg

(020)462221
Telex: ,,625

02-736.1007
Telex: 2514'

THE NETHERLANDS
NiJkerk Elektronika BV
Drentestraat 7
NL ~ 1083 HK Amsterdam

Branch offices m: Berlin, Hannover,
Dusseldorf, Darmstadt. Stuttgart,
Munchen

Telex: 0529345

Telex: '5084

Branch Office:
C. Pedro IV, 84
Barcelona

(03)3095116
ITALY
Comprel s.d.
V Ie Romagna. 1
1·20092 Cinisello B. (Mil
(02)61.20.641/2/3/4/5
Telex: 332484
Branch offices in
Bologna, Firenze,
Chlavari, loreto,
Padova, Roma, Torino,
Bari, Vicenza

.11-9.

Telex: 51934

SWEDEN
Traco AB
Box 32
S-12322 Farsta
08-13.21.60
Telex: 10689

SWITZERLAND
MemotecAG
Gaswerkstrasse, 32
CH-4901 Langenthal
063-28.11.22
Telex: 68636
UNITED KINGDOM
Celdis Limited
37 -39 Loverock Road
Reading
Berks RG 31 ED
0734-58.51.71
Telex: 8483770
lock Distribution ltd.
Neville Street
Chadderton
Oldham
lancashire
Ol96lF
061-652.04.31
Telex: 669971
Pronto Electronic Systems ltd.
466-478 Cranbrook Road,
Gants HilIlIford
Essex 1 G2 6lE
01-56462.22
Telex: 8954213
VSI Electronics (UK) ltd.
Roydonbury Industrial Part<
Horsecroft Rd.
Harlow
Essex CM195 BY

(0279)35477
Telex: a1 387
Thame Components ltd.
Thame Park Road
Thame, Oxon axs 3XD
084 421.31.46
Telex: 837917

11-10

1983 COMPUTER PRODUCTS DATA BOOK

VMEbus

. ,'/

,

..... ' ..

::: 'l;

~

,;

;

J ....
~

!

!t

COMPUTER
PRODUCTS
DIVISION

UNITED
TECHNOLOGIES
MOSTEK

VME-SBC

FEATURES

VME-SBC
Figure 1

The SBC board serves as a stand alone module or as the
System Controller/Master (slot 1 type CPU) on the VMEbus.
It contains the following features:

o

VMEbus Master/Slave

o CPU MK68000 (8 MHz to 12 MHz)
o Eight BYTEWYDE Sockets
• 2 EPROM/ROM dedicated
• 2 RAM dedicated
• 4 option EPROM/ROM or RAM
o Provides VMEbus utilities
• Power and Pushbutton Reset
• System 16 MHz clock
• Programmable 8us-Time-Out
• 1 Level Arbiter utilizing the CPU's BR*, BG*, and
BGACK* lines
o CSR Register
o Selection Switches (With Remote Capability)
independent serial communications bus, and open-ended
transaction coding, it provides for tomorrow's applications
as well, assuring the user of a compatible upward growth
path for years to come. The international-standard compact
board size promotes functional modularity and low board
cost, and allows the user to select only those functions
needed for his application.

o Interrupt Handler
o Two Timer/Counters
o Serial I/O (D.C. E.)
• One channel modified RS-232
• Asynchronous only (to 19.2K Baud)
• Receive Data, Transmit Data, RTS, CTS, DTR. DSR.
and DCD

Mostek's VME board product line provides an everexpanding family of powerful general-purpose modules,
applicable to a wide variety of systems and applications
including data, word, and image processing, communications, industrial automation and robotics, data acquisition, and software development. For specialized functions
provided by other vendors or by the user, Mostek VME
boards are totally compatible with the VMEbus specification, ensuring fully functional operation with all other
VMEbus compatible modules.

o On Board Vectored Interrupts
o Self-Test LED
VME SYSTEM DESCRIPTION
The VMEbus was designed jointly by Mostek, Motorola, and
Signetics, and was introduced in October, 1981 . It offers an
attractive combination of high performance timing
parameters, compact form factor, and the advanced
functional capability appropriate for today's applications of
16-bit microprocessors such as the MK68000. With
features such as expansion to 32-bit auJress and data, an

VME-SBC DESCRIPTION
The Mostek VME-SBC, based on the powerful 68000
microprocessor, features eight 28-pin memory sockets
which enable the user to populate the. module with any

111-1

~

2

~

RESET'
HALT'

SYSRESET*

RESET

&-

8MHz

SYSCLK

CLOCK CIRCUIT

t

..

~

1---+

Ci\ IJI
Nr-

1---+

c
':;
Ii)

o
o

CLK
ADORES!; BUS (A01-A23)

23

A01A23

cS'g:
c: 0

'"

:D

l>

It
FCO
FC1
FC2

FUNCTION CODES

,,3

ADDRESS
MODIFIER
ENCODE
LOGIC

lACK &
ADDRESS MODIFIERS (AMO-AM5)

,,7

I
LOCAL
MEMORY
DECODE &
CONTROL
LOGIC

BR'
BG'
BGACK'

~

,,7

---

I---

I

1---+
0
R
I
V
E
R
S
&
R
E
C
E
I
V
E
R
S

I

: LOCAL MEMORy l
I
I

I

I

I

I
I
I

I
I

---I-~-I---I---

I
I
I

BUS GRANT LOGIC SIGNALS

I

f-----;

LOCAL
1/0 DECODE
& CONTROL
LOGIC

MK68000
(8 MHz).

s::

f--

L.,

--

-

BUS
GRANT
LOGIC

BBSY'

I:r-----

BR3'
BGOUT3'
DTACK'

DTACK'
000015
AS'
UDS'
LOS'

illw

IPLO
IPL1
IPL2
VPA'

,
~

~

3

•
INTERRUPT
CONTROL
LOGIC

-,

BUS CONTROL SIGNALS

,,4

-

I :

IACKOUT'

I

IR01*-IR07'

8

J.- ' - - .....----.

f

I

INT

, ,,8

2

00-07 SERIAL
MK3801
(STI)

BFRR'

~

DATA BUS (000-015)

16

BTO
LOGIC

,

TIMERS

8

CLK

It

r

SWITCH
REGISTER

1I

V
M
E
B
U
S
(P1)

CSR
REGISTER

~

RS-232
(DCE)
INTERFACE

~
V
M
E
B
U
S
(P2)

t
TIMER
CLOCK

L.......-....I

combination of designated ROM, RAM, and EPROM
devices.

MK75601-X-01 SOCKET POPULATION
(2-2764s 6-6116s)
Figure 3

Flexible address decoding allows the user to configure each
memory device within any 4K byte boundary of the 16M
byte addressing space. The user can choose one of the two
preselected memory configurations or, by programming a
decoder PAL, may assign any of the eight sockets to any
address range. In addition, a memory controller PAL is
utilized to accommodate different speed memory devices,
taking advantage of fast RAM access times.

MEMORY
DEVICE
2764 (EPROM)
6116(RAM)
6116 (RAM)
6116 (RAM)

EVEN
BYTE #

ODD
BYTE #

ASSOC
JUMPER

U09
U10
U11
U12

U24
U25
U26
U27

J3
J2
J1
J4

MK75601-X-02 SOCKET POPULATION
(6-2764s 2-61165)

The on-board I/O includes a Mostek Serial/Timer/Interrupt chip (ST!. MK3801) which provides an RS-232C serial
channel, two counter/timer channels, programmable Baud
rate, and programmable bus time out. In addition, the VMESBC contains an 8-bit switch input register and a Command
Status Register (CSR). The CSR register allows software
control of the following: STI interrupt level (1-7), Bus-TimeOut status, Self Test LED control (RED/GREEN), and
Individual interrupt enable bits (1-7).

MEMORY
DEVICE
2764 (EPROM)
6116(RAM)
2764 (EPROM)
2764 (EPROM)

EVEN
BYTE #

ODD
BYTE #

ASSOC
JUMPER

U09
U10
U11
U12

U24
U25
U26
U27

J3
J2
J1
J4

MEMORY SPEED REQUIREMENTS
Figure 4

MEMORY SOCKET POPULATION
The VME-SBC is offered in two memory configurations.
MK75601-X-01 is populated with two 2764's (16Kb
EPROM) containing a software debugger monitor
(MON68K), andsix6116's(12KbRAM). MK75601-X-02 is
populated with two 6116's (4Kb RAM) and the remaining
sockets are configured for but not populated to
accommodate six 2764's, allowing the user 48Kb of
EPROM. The memory socket population is shown in Figure
3.
The memory access time of the on-board RAM and EPROM
required by the VME-SBC is determined by the processor
speed. Refer to Figure 4 to determine the memory speed
requirements:

VME-SBC
MK#

EPROM
ACCESS TIME
Min (nsec)

RAM
ACCESS TIME
Min (nsec)

MK75601-8-01
MK75601-8-02
MK75601-10-01
MK75601-10-02
MK75601-12-01
MK75601-12-02

300
300
250
250
200
200

150
150
150
150
120
120

MEMORY CONFIGURATION STRAPS
The memory configurating straps are installed at shipment.
Each configuration is shown in Figure 5.

MK75601-X-01 MEMORY STRAPPING
(2-2764s 6-6116s)
Figure 5
J1
1- 2
3
4
5
6
7
8
9-10
11
12
14
13
15 - 1 6

J2
1- 2
3
4
5
6
7
8
9-10
11
12
13
14
15 - 1 6

J3
1
2
3- 4
5
6
7- 8
10
9
11
12
13-14
15
16

J4
1- 2
3
4
5
6
7
8
9-10
11
12
13
14
15-16

J5
1-2

J4
1
2
3- 4

J5
1-2
3
4

3

4

J6
1
2
3-4

MK75601-X-02 MEMORY STRAPPING
(6-2764s 2-6116s)
J1
2
3- 4
6
5
7- 8
10
9
11
12
13-14
16
15

J2
1- 2
3
4
5
6
7
8
9-10
11
12
13
14
15-16

J3
2
3- 4
5
6
7- 8
10
9
11
12
13-14
15
16

5

2
3-4

6

7- 8
10
9
11
12
13-14
15
16

111-3

J6

NOTE:
(-) Indicates strap installed.

I/O Adapter

Timer Input/Output Bits

The VME-SBC provides the RS-232C, Timer/Control,
Remote Reset, and Remote Selection inputs on the P2
connector. In order to interface to the I/O connector, one
must construct either a custom cable or purchase an I/O
adapter MK75901, which allows use of a standard RS232C cable. The I/O adapter contains four DB-25
connectors where one is dedicated for the serial interface
and the second for remoting the selection switch, timer
inputs/outputs, and Reset. The other two DB-25's are
unused. The I/O adapter also contains jumper blocks to
allow timer "chaining" and Baud rate measurement.
Appendix A contains the connections needed to interface
P2 to EIA RS-232C and Appendix B contains the P2 pinout.

The SBC provides four counter/timers via the STI. Two of
the timers (TAO and TBO), provide full service features
including delay timer operation, event counter operation,
pulse width measurement and pulse generation. The other
two timers (TCO and TOO) provide delay timer operation
only, and are used for programmable bus time out and Baud
rate generation, respectively. Timers TAO and TBO,
however, are for user use and have their outputs and inputs
routed to P2. These locations can be found in the P2 pinout
table in Appendix B. The bus time out clock is routed to
P2-A6 to allow chaining this timer to either Timer A or B to
increase the maximum time out of Timer A or B. When
using this feature, one must realize that the bus time out
clock still retains its function of bus time out.

Baud Rate Measurement Strap
When using the Mostek debugger monitor (MON68K), it is
necessary to strap P2-A3 to P2-A4. This strapping
arrangement routes the serial in data to a timer input of the
STI (Serial Timer Interface) to allow Baud rate measurement.

ARBITRATION
The VME-SBC provides a one level arbiter on Bus Request
Level 3 utilizing the CPU's BR*, BG*, and BGACK* pins. The
SBC will not acknowledge requests on any other levels.

External Push Button Reset Option

MEMORY MAP

The VME-SBC provides an input on P2-A 18 for a remote
reset switch, so that the system can be reset from either the
on-board push button or an external one.

The VME-SBC MK75601-X-01 has 16Kb of EPROM
(2764's) containing the software debugger monitor
(MON68K) and 12Kb of RAM. In addition it contains a 16-bit
CSR (Command Status Register), an 8-bit selection switch
register, and a Mostek STI. The local memory map is shown
in Figure 6.

Remote Selection Switches
The two selection switches located on the SBC provide
eight bits of information that can be read by the CPU. The
switch inputs (S7 -SO) are routed to P2 to allow inputs other
than from the on-board switches. To use external inputs,
one must set the on-board switches to a value of FF. Refer to
Appendix B to determine the P2 locations of the inputs.

The VME-SBC MK75601-X-02 can be populated to have
48Kb of EPROM (2764's) containing user firmware and 4Kb
of RAM. Similar to the VME-SBC MK75601-X-01, it
contains a 16-bit CSR and an STI. It has a local memory map
as shown in Figure 7.

Parallel Output Bit
The STI (Serial Timer Interface), bit 17 is buffered as an
output and routed to P2-A17.

Application Note #4420XXX provides necessary informa~
tion if the pre-configured memory map needs to be changed
to meet a particular application.

VME-SBC MK75601-X-01 MEMORY MAP
Figure 6

DEVICE
RAM (U10,25)
RAM (U11,26)
RAM (U12,27)
EPROM (U9,24)
SWITCHES
CSR
STI (U34)

ADDRESS

SUP/USER

WORD/BYTE

00000o - oooFFF

SUP
SUP/USER
SUP/USER
SUP
SUP
SUP
SUP

WORD OR BYTE
WORD OR BYTE
WORD OR BYTE
WORD OR BYTE
BYTE ONLY
WORD OR BYTE
BYTE ONLY

001000 - 001 FFF
002000 - 002FFF
FECOOO - FEFFFF
FFF801
FFF802 - FF803
FFF821 - FFF83F

111-4

VME-SBC MK75601-X-02 MEMORY MAP
Figure 7

DEVICE

ADDRESS

SUP/USER

WORD/BYTE

RAM (UlO,25)
EPROM (Ull ,26)
EPROM (U12,27)
EPROM (U9,24)
SWITCHES
CSR
STI (U34)

00000o - OOOFFF

SUP
SUP
SUP
SUP
SUP
SUP
SUP

WORD OR BYTE
WORD OR BYTE
WORD OR BYTE
WORD OR BYTE
BYTE ONLY
WORD OR BYTE
BYTE ONLY

FE4000 - FE7FFF
FESOOO - FEBFFF
FECOOO - FEFFFF
FFFSOl
FFFS02 - FFFS03
FFFS2l - FFFS3F

RESET VECTOR LOCATION

operation to the EPROM.

The MK6S000 reserves the first 1Kb of memory starting at
address ooOOOOH for the exception vectors, including the
power-on reset vector and initial supervisor stack pointer.
The VME-SBC contains logic that enables the EPROM to
provide the processor with the reset vector and supervisor
stack pointer upon either push button reset or system power
up. The power up vectors are located at address FECoooFEC007 on the MK75601 -X-Ol version and at FE40ooFE4007 on the MK75601 -X-02 version. The user SHOULD
BE AWARE that when a write access to RAM addresses
000000-000007 is made, a bus .error will result because
the on-board logic will interpret this cycle as a write

.A PROM is used to implement the logic that determines if
the exception vector is fetched from RAM or EPROM. The
Application Note referenced describes how to program this
PROM to allow exception vectors in addition to Reset to
reside in EPROM.
COMMAND STATUS REGISTER
The CSR has a fixed address of FFF802 and can only be
addressed locally in the Supervisor State. The register is
initialled to ooH on reset and is a Read-Write Register. The
bit definitions are defined in Figure S.

BIT DEFINITIONS
Figure 8
015

014

013

012

011

010

11
11
009

008

FUNCTION

L

IE1
IE2
IE3
IE4
IE5
IE6

1E7
INTENABLE

007

006

005

004

1
003

002

001

FUNCTION

000

T
T~1T_:::~
I -

UNUSED

' - - - - - - - - - - - - - - - ' - - - - - - BTO CLEAR
' - - - - - - - - - - - - - - - - - - - - - - - BTOSTAT
' - - - - - - - - - - - - - - - - - - - - - - - - - GSYSFAIL
' - - - - - - - - - - - - - - - - - - - - - - - - - - - LSYSFAIL

111-5

015 Interrupt Enable

allows programming the interrupt level from 0 to 7. The
power-up reset level is 000 which disables STI interrupts.
111 equals a level of 7.

The interrupt enable bit controls all interrupt requests for
the VMEbus and on-board devices, including SYSFAIL * and
ACFAIL*. The power up condition is all interrupts disabled.
Setting this bit to a "1" allows all enabled interrupts.

SELECTION SWITCH REGISTER

008-014 Interrupt Enable Bits
If Interrupt Enable (D15 =1) is on, setting these bits to a "1 "
enables the specified interrupt level. The ACFAIL* (Level 7
Autovector) and SYSFAIL* (Level 6 Autovector) interrupts
are enabled whenever the INT ENABLE bit is set (D15).

The VME-SBC contains an 8-bit switch input register to
accommodate two 4-bit switches. This register has a local
address of FFF801 (Byte Register) and is read only in the
Supervisor State: The register inputs are also routed to P2 to
allow remote selection switches. The location of the P2
register inputs can be found in Appendix B.
Baud Rates

007 Local SVSFAIL
This bit controls the board's contribution to the VME
SYSFAIL* signal and the state of the red/green LED. When
set to 1, the SYSFAIL* signal is not driven and the LED is
green. When cleared, the SYSFAIL" signal is asserted and
the LED is red.

006 Global SYSFAIL
This is a read only bit and reflects the status of the VMEbus
SYSFAIL* signal. A low-going edge on SYSFAIL*,
subsequent to RESET, also causes a level 6 autovector. A
"0" indicates a system fail condition.

Baud rates on the SBC are fully programmable and are
generated by the Timer D outputofthe STI. Table 1 contains
the Timer D data register values for the various Baud rates.
Refer to Appendix C for a software example that sets the
Baud rate. Timer D should be programmed to a prescaler of
divide by 4.
'
BAUD RATE SELECTION
(TIMER 0 PRESCALER = DIVIDE BY 4)
Table 1
TIMER 0 DATA REGISTER
HEX VALUE (TDDR)
$AE

005 BTO Status

$40
$20
$10
$08

The BTO (Bus Time Out) status bit is set when the on-board
BTO logic detects a BTO and asserts BERR*. It is cleared by
writing a 1 to the BTO CLEAR bit (004).

004 BTO Clear
Writing a "1 "to the bit clears the BTO status bit. This bit will
always be "0" when it is read.

000-002 STI Interrupt Priority
The interrupt priority bits sets the priority of the STI. This

106

106

104

103

102

101

2400
4800

$02
$01

9600
19200

The STI parallel input/outputs are used to implement the
RS-232C control signals. Appendix C contains a software
example which will aid in programming the control bits.

FUNCTION

I1T~-

ICTS
IOSR
IOTR
TBIN
TAIN

IRTS
lOCO
P20UTPUT

111-6

110
300
600
1200

RS-232C Control Signals

100

TT

(x16)

$04

STI PARALLEL INPUT/OUTPUT DEFINITIONS
Figure 9

107

BAUD RATE

STI (MK3801) Operation

SPECIFICATIONS

The Mostek MK3801 (STI) internal registers are available to
the programmer starting at hex address FFF820 as shown
in Appendix C, which contains a simple software driver. For
specific programming of these registers, refer to the
MK3801 Technical Manual.

Electrical Specifications
VMEbus DRIVERS
Totem-Pole

VOL = 0.6 V [email protected] ma
V OH = 2.4 V Min @ 3 ma

Three-State

VOL = 0.6 V [email protected] ma
V OH = 2.4 V Min @ 3 ma
loz = +50 !J.a Max @ 2.4 V or 0.5 V

Open-Collector

VOL =0.6 V Max @ 48 ma
10H = 50 !J.a Max @ 5 V

PROGRAMMABLE BUS-TIME-OUT
The STI Timer C output is used to provide the bus time out
clock. The first positive clock is used to sample the state of
the data strobes. If either data strobe is sampldd low for two
clock periods, the bus time out logic drives BERR* active and
sets the status bit in the CSR. Since the bus time out clock is
asynchronous to the assertion of the data strobes the bus
time out is only accurate to + one clock period due to the
synchronization of the data strobes with the bus time out
clock. Below is the BTO range, depending on the prescaler
value selected. Once a prescaler value is chosen, one can
specify a bus time out period and compute the correct
counter data value with the formula given in Figure 10. One
must convert the base ten value given by the formula to
base 2 for the actual counter value. Appendix C contains a
software example for programming the bus time out in the
Initialization routine.

VMEbus RECEIVERS
V IL = 0.8 V Max
V IH = 2.0 V Min
IlL = -400 !J.a Max @ 0 < V < 0.5
IIH = 50!J.a Max @ 5.0> V> 2.7
VOLTAGE REQUIREMENTS
[email protected]
+12 V @ 150 mA MAX (RS232 only)
-12 V @ 150 mA MAX (RS232 only)

COUNTER DATA VALUE
Figure 10

Mechanical Specifications

PRESCALER

MIN BTO

MAXBTO

4
10
16
50
64
100
200

3.26 !J.sec
8.13 !J.sec
13.02 !J.sec
40.69 !J.sec
52.08 !J.sec
81.38 !J.sec
162.76 !J.sec

0.84
2.08
3.33
10.42
13.33
20.83
41.76

(BTO) (2457600)
COUNTER VALUE 10= (PRESCALER) (2)

msec
msec
msec
msec
msec
msec
msec

Length
Width
Board Thickness
Component Lead Protrusion
Connector

6.30 in. (160 mm)
9.20 in. (233.7 mm) .68
.38mm)
.062 in. (1.57 mm)
.100 (2.54 mm) Max
96 Pin, IEC Standard
(603-2 IEC-c096-M)

±

Environmental Specifications
Temperature Range
Relative Humidity

111-7

0-60° C
10-90% (non-condensing)

APPENDICES
APPENDIX A
RS·232C PIN OUT AND CABLE WIRING LIST
RS232C
SIGNAL

DB25
PIN#

BA (TXDATA)
BB (RXDATA)
CA (DSR)
CB (CTS)
CC (DCD)
AB (GND)
CF (DCD)
CD (DTR)

2
3
4
5
6
7
8
20

P2·PIN NUMBER
7a
8a
8e·
ge
10a
10e
11 e
11a

APPENDIXB
P2 PINOUT
PIN NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
i5
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

ROWA

ROWB

ROWC

TAOUT
TAIN
SI
TBIN
TBOUT
BTOCLK
BA(TXDATA)
BB(RXDATA)
NC
CC(DSR)
CD(DTR)
NC
SO
S1
S2
S3
170UT
EXTRESET*
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

5VOLT
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND
5VOLT
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND
NC
NC
GND
5VOLT

NC
NC
NC
NC
NC
NC
NC
CA(RTS)
CB(CTS)
AB(GND)
CF(DCD)
NC
S4
S5
S6
GND
S7
NC
NC
NC
NC
GND
NC
NC
NC
NC
NC
GND
NC
NC
NC
NC

APPENDIXC
SOFTWARE DRIVER EXAMPLE
MOTOROLA MK68000 ASM VERSION 1.20 SYS :
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39

40
41
42
43

.SA 08126/82

.SBCOPS

14:16:28

PAGE 1

*
SBC SERIAL SOFTWARE DRIVER EXAMPLE

*
00001000

00000002
OOOOOOFF
00000000
00000002

ORG

$1000

*
*

PROGRAM DEFINITIONS

BAUD
BTO
RXFULL
TXEMPTY

EQU
EQU
EQU
EQU

$02
$FF
SO
$2

;
;
;
;

BAUD RATE = 9600
BUS TIME OUT CONSTANT
RECEIVER FULL BIT
TRANSMITTER EMPTY BIT

STI DIRECT REGISTER DEFINITIONS
ooFFF821

00000000
00000002
00000004
00000006
00000008
ooOOOOOA
OOOOOOOC
OOOOOOOE
00000010
00000012
00000014
00000016
00000018
0000001 A
0000001C
0000001E

00000000
00000001
00000002
00000003

44

00000OO4

45
46
47

00000005
00000006
00000007

49
50
51
52
53
54
55

12

$FFF821
$0
$2
$4
$6
$8
SA
$C
$E
$10
S12
$14
$16
$18
$1A
$1C
$1E

;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;

STI BASE ADDRESS
INDIRECT DATA REGISTER
GENERAL PURPOSE I/O INTERRUPT
INTERRUPT PENDING REGISTER B
INTERRUPT PENDING REGISTER A
INTERRUPT IN-SERVICE REGISTER B
INTERRUPT IN-SERVICE REGISTER A
INTERRUPT MASK REGISTER B
INTERRUPT MASK REGISTER A
POINTER VECTOR REGISTER
TIMER A AND B CONTROL REGISTER
TIMER B DATA REGISTER
TIMER A DATA REGISTER
USART CONTROL REGISTER
RECEIVER STATUS REGISTER
TRANSMITTER STATUS REGISTER
USART DATA REGISTER

STI
IDR
GPIP
IPRB
IPRA
ISRB
ISRA
IMRB
IMRA
PVR
TABCR
TBDR
TADR
UCR
RSR
TSR
UDR

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

*
*
*

STI INDIRECT REGISTER DEFINITIONS

SCR
TDDR
TDCR
AER
IERB
IERA
DDR
TCDCR

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

*
*
*
*
*

LOOP TO ECHO CHARACTERS AND SET UP BUS TIME OUT VALUE
TO SERVE AS AN EXAMPLE OF USE OF THE THREE SUBROUTINES
TO FOLLOW

$0
$1
$2
$3
$4
$5
$6
$7

111-9

;
;
;
;
;
;
;
;

SYNC CHARACTER
TIMER D DATA REGISTER
TIMER C DATA REGISTER
ACTIVE EDGE READY
INTERRUPT ENABLE REGISTER B
INTERRUPT ENABLE REGISTER A
DATA DIRECTION REGISTER
TIMER C AND D CONTROL REGISTER

MOTOROLA MK68000 ASM VERSION 1.20 SYS :
56
57
58
59
60
61
62
63
64

"
"
00001000
00001002
00001004
00001006

6106
614C
615E
60FA

12

.SA 08/26/82

.SBCOPS

14:16:28

PAGE ,2

,

START
LOOP

INIT
RDCHR
WRTCHR
LOOP

BSR.S
BSR.S
BSR.S
BRA.S

; SET BAUD RATE,BTO, AND USART
; GET TERMINAL INPUT
; OUTPUT TO TERMINAL

"
"

:'.~' ,

66
67
68
69
70
71

*
*
*

"

*
*:

72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107

INITIALIZATION: SETS BAUD RATE, BUS TIME OUT CONSTANT,
AND USART THROUGH THE STI

00001008 43F900FFF821
oooo100E 137C00060010
00001014 12BC0043
00001018 137COOOOOOO2
0000101 E 137C00010010
00001024 12BCOOO2
00001028 137800070010
oooo102E 12BC0021
00001032 137C00980018
00001038 137C0001001A
00001 03E137COOO5001 C
00001044 137COOO20010
oooo104A 12BCOOFF
00001 b4E ' 4E75

"

INIT

LEA
MOVE.B
MOVE.B
MOVE.B
MOVE.B
MOVE.B
MOVE.B
MOVE.B
MOVE.B
MOVE.B
MOVE.B
MOVE.B
MOVE.B
RTS

STI,A1
#DDR,PVR(A 1 )
#$43,IDR(A1)
#$OO,GPIp(A1)
#TDDR;P'ilR(A 1)
#BAUD,IDR(A 1)
TCDCR,PVR(A1 )
#$21,IDR{A1)
#$98,UCR(A 1)
#$1,RSR(A1)
#$5,TSR(A1)
#$TDCR,PVR(A 1)
#BTO,IDR(A1)

;
;
;
;
;
;
;
;
;
;
;
;
;

STI BASE ADDRESS
POINT TO DATA DIRECTION REGISTER
SET OUTPUTS
RS-232 CONTROL OUTPUTS ACTIVE
POINT TO BAUD RATE COUNTER
SET BAUD RATE
POINT TO TIMER C AND D CONTROL REG.
DIV BY 4 (TIM D), DIV BY 10 (TIM C)
DIV BY 16, 2 STOP BITS
ENABLE RECEIVER
ENABLE TRANSMITTER
POINT TO BUS TIME OUT COUNTER
SET BUS TIME OUT CONSTANT

*
*
*

"*

"
"
"

RDCHR: READS CHARACTER FROM STI AND RETURNS ASCII
VALUE IN DO.

*

*

00001050 43F900FFF821
00001056 08290000001A
0000105C 67F8
0000105E 1029001E
000010624E75

."
"

RDCHR
RXPOOL

LEA
BTST.B
BEQ.S
MOVE.B
RTS

STI,A1
; STI BASE ADDRESS
~(A1) ; RECEIVER FULL?
#RXFULI
; CONTINUE POLL
RXPOOl
UDR(A1) , J
; GET ASCII INPUT

"
"
"

109
110
111
112
113

*

"
"

WRTCHR: OUTPUTS CHARACTER IN DO TO TERMINAL

111-10

MOTOROLA MK68000 ASM VERSION 1.20 SYS:
114
115
116
117
118
119
120
121
122
123
124

00001064
oooo106A
00001070
00001072
00001076

43F900FFF821
WRTCHR
08290002001 C TXPOOL
67F8
1340001E
4E75

.sBCOPS

12

LEA
BTST.B
BEQ.S
MOVE.B
RTS

.SA

08/26/82

14:16:28

STI,A1
; STI BASE ADDRESS
#TXEMPTY,TSR(A 1) ; TRANSMITTER EMPTY?
TXPOOL
DO,UDR(A 1)
; OUTPUT CHARACTER

END

****** TOTAL ERRORS
****** TOTAL WARNINGS

0-0--

0
0

MOTOROLA MK68000 ASM VERSION 1.20 SYS:

12

.SBCOPS

.SA 08126/82

14:16:28

SYMBOL TABLE LISTING

SYMBOL NAME

SECT VALUE

SYMBOL NAME

SECT VALUE

AER
BAUD
BTO
DDR
GPIP
lOR
IERA
IERB
IMRA
IMRB
INIT
IPRA
IPRB
ISRA
ISRB
LOOP
PVR
RDCHR

00000003
00000002
OOOOOOFF
00000006
00000002
00000000
00000005
00000004
OOOOOOOE
OOooooOC
00001008
00000006

RSR
RXFULL
RXPOOL
SCR
START
STI
TABCR
TADR
TBDR
TCDCR
TDCR
TDDR
TSR
TXEMPTY
TXPOOL
UCR
UDR
WRTCHR

0000001 A
00000000
00001056
00000000
00001000
OOFFF821
00000012
00000016
00000014
00000007
00000002
00000001
0000001C
00000002
oooo106A
00000018
oooo001E
00001064

00000OO4

OOOOOOOA
00000008
00001002
00000010
00001050

ORDERING INFORMATION

DESIGNATOR

DESCRIPTION

PART NO.

VME-SBC

VME 8 MHz Single Board Computer with Technical Manual
(MON68K Debugger Monitor, 12K bytes RAM)

MK75601-8-01

VME-SBC

VME 8 MHz Single Board Computer with Technical Manual
(4K bytes RAM, configured for 48K bytes EPROM)

MK75601-8-01

VME-SBC
Technical Manual

Technical Manual only

4420342

111-11

PAGE 3

111-12

IJ

UNITED
TECHNOLOGIES
MOSTEK

COMPUTER
PRODUCTS
DIVISION
VME-SASI

FEATURES

VME·SASI BOARD
Figure 1

o VMEbus Master/Slave
o DMA cantransfer up to 64K byte data blocks
o Programmable Bus Request and Interrupt Priority
Request level
o Interface to SASI compatible controllers
o Up to eight Controllers can interface to the VMEbus
through the VME-SASI
o Byte or Word DMA data transfer capability or
Programmed byte data transfers
o Automatic SASI handshake control for communication
with controller
o End of command interrupt
o Selectable I/O address on P2 connector
VME SYSTEM DESCRIPTION
The VMEbus was designed jointly by Mostek, Motorola, and
Signetics and was introduced in October, 1981. It offers a
combination of high performance timing parameters, a
compact form factor, and the advanced functional capability
appropriate for today's applications' of 16-bit microprocessors' such as the MK68000. The internationalstandard compact board size promotes functional modularity and low board cost, and it allows the user to select only
those functions needed for his application.
VME-SASI DESCRIPTION
The VME-SASI interfaces the VMEbus with a nonarbitrating Shugart Associates System Interface(SASI) bus,
which is compatible with many hard disk and floppy disk
controllers. SASI handshake control signals are monitored
and acknowledged automatically by the VME-SASI. thus
minimizing software overhead. The condition of the
interface is available through a status register.

Interrupts report the conditions of controller status ava ilable
and the end of DMA transfer.
The daisy chain bus request and interrupt request
configuration of the VMEbus allows multiple VME-SASI
boards to be used in a system. Each VME·SASI board
address, within short I/O address space, is selected (8 word
increments) by strapping on the P2 connector.
A control register provides the capability to select the
Interrupt priority level, bus request level. User/Supervisor
access, DMA mode, and diagnostic status.
A red/green bi-color LED provides a visual indication of the
diagnostic status of the board.
The VME·SASI Block Diagram is shown in Figure 2.
INSTALLATION

Data transfers with a controller can be performed on a
programmed byt.e basis or by using the DMA modes. A byte
DMA mode is provided for DMA transfers to or from other
byte oriented I/O devices. The word DMA mode allows data
transfers in standard addressed memory.

The VME·SASI mates with the VMEbus standard
ccmnections as defined by the VMEbus Technical
Specification. The SASI bus connections are made through
the P2 connector. The P2 signals are defined in Table 1.

111·13

:n<
cg s:

m
,

~
CD

NC/)

J>

~

"..-.,....16

CONTROLLER
DATA INTERFACE

t
8

lit

1\:--

8

N

\

I

0

P2

511'

CONTROLLER
II INTERFACE
CONTROL

4

T
1

4

DMA COMMAND;
STATUS REGISTER

Dl

r-

(')

TO HARD DISK
CONTROLLERS

"l>
Cl

3

G)

'--

JJ

J>

s:

4
4

16
BYTE
COUNTER

I
2

8

...

2
3

COMMAND/STATUS
REGISTER

.j:>

8

16

DATA
BUFFER

)
000-015

I

2

t

BUS
REQUEST
RELEASE
CONTROL

f2
15

~

,. ADDRESS

SYSRESET

MASTER SLAVE
CONTROL

P2 JUMPERS

23

RESET

1

1

INTERRUPT
VECTOR
NUMBER

ADDRESS
COUNTER

2
INTERRUPT
CONTROL

I

ADD""
DECODE
ADDRESS
MODIFIER DECODER
BUFFER

'0" 'B'

A01·A23

lACK

AMO-5

'

6

,

1

.1

1 ,

4

~
I----

i-4 ,-

4

1

"

1

1

,

1

"

1

1
•••

SYSFAIL

VMEbus

IRQ IACKIN IACKOUT BBSY BR
1-6
0-3

BG
IN

BG
OUT

AS

DSO

DS1

WRITE DTACK BERR

P2 CONNECTOR
Table 1

PIN NO.

ROWA

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

CA 15
CA 13
CAll
CA 9
CA 7
CA 5
GND
DATA 0*
DATA 1*
DATA 2*
DATA 3*
DATA 4*
DATA 5*
DATA 6*
DATA 7*
NU
NU
NU
NU
NU
NU
NU
NU
NU
BSY*
ACK*
RST*
MSG*
SEL*
C*/D
REQ*
1/0*

VME-SASI P2 CONNECTOR SIGNALS
ROWB
+5V
GND
R'SVED
A24
A25
A26
A27
A28
A29
A30
A31
GND
+5V
016
017
018
019
020
021
022
023
GND
024
025
026
027
028
029
030
D31
GND
+5V

ROWC
CA 14
CA 12
CA 10
CA 8
CA 6
CA 4
GND
SIGGND
SIGGND
SIGGND
SIGGND
SIGGND
SIGGND
SIGGND
SIGGND
NU
NU
NU
NU
NU
NU
NU
NU
NU
SIGGND
SIGGND
SIGGND
SIGGND
SIGGND
SIGGND
SIGGND
SIGGND

NU - NOT USED
CA - COMPARED ADDRESS Strap address lines to ground to select the desired SASI short 1/0 address.
SIGGND - SIGNAL GROUND To be used when a ground is desired for each signal such as a twisted pair, or alternating
grounds ina flat cable.
Address Strapping
The VME-SASI slave address resides in short 110
addressing space and is strappable to any sixteen byte 110
address boundary. Base address selection is made by
strapping the desired address via the P2 connector.
The P2 address pins are a logic high (true) when left open.
Therefore, to select the desired base address, strap the
address bits required to be logic low (false) to ground. If all
pins are left open, the base address will be FFFFFO.lf all pins

are grounded, the base address will be FFOOOO. The P2
address pins are listed in Table 2.
SASI P2 Interlace
The SASI signal pinout on the P2 connector is shown in
Table 3. The P2 - GND column indicates the ground
associated with each signal for cabling purposes. Note that
the pinouts are compatible with a 50 pin flat cable to
interface directly to a SASI bus.

111-15

TECHNICAL INFORMATION
P2 ADDRESS STRAPPING PINS

Table 2

Register Map

P2~6c",

A 4
A 5

P2-6a
P2-5c
P2-5a
P2-4c
P2-4a
P2-3c
P2-3a
P2-2c
P2-2a
P2-1c
P2-1a

A6

A 7
A 8
A 9
A10
A11
A12
A13
A14
A15

All registers on the VME-SASI are accessed through short
I/O addressing. The exact address block (8 words) is
selected by address strapping (A4-A 15) on the P2
connector. All registers may be accessed as word registers
on even addresses. All registers, except the upper byte
registers that are "don't cares", may be accessed as byte
registers. If an attempt is made to access a "don't care"
upper byte register as a byte, the SASI will not respond arid
a bus timeout will occur. The upper byte "don't care"
registers are shown in Figure 3 as X's.
The registers are listed below in the order of their offset
from the base address selected by the address straps on P2.
The register map is shown in Figure 3.
OFFSET

P2 SASI SIGNALS

Table 3

o -

SASI SIGNAL

P2 - PIN

DATA 0*
DATA 1*
DATA 2*
DATA 3*
DATA 4*
DATA 5*
DATA 6*
DATA 7*
BSY*
ACK*
RST*
MSG*
SEL*
C/D*
REQ*
1/0*

a 8
a 9
a10
a11
a12
a13
a14
a15
a25
a26
a27
a28
,'..a29
a30
a31
a32

P2 - GND

I

c 8
c 9
c10
c11 .
c12
c13
c14
c15
c25
c26
c27
c28
c29
c30
c31
c32

2
4
6
8

-

A

-

C E OFFSET

1
3 5
7

9 B
D

F -

* indicates true low signals

111-1«»

REGISTER
DMASTATUS
DMACOMMAND
UPPER BYTE COUNT
DON'T CARE
MIDDLE BYTE DMA ADDRESS
DON'T CARE
DON'T CARE
DON'T CARE'
REGISTER
INTERRUPT VECTOR
CSR
LOWER BYTE COUNT
UPPER BYTE DMA ADDRESS
LOWER BYTE DMA ADDRESS
CONTROLLER COMMAND/STATUS
CONTROLLER SELECT
CONTROLLER DATA

REGISTER MAP
Figure 3
015

014

DMA
COMP BERR

013

012

011

010

D09

D08

RE
SET'

REO"

I/O

C/O

BSY"

MSG"

R/W
TC/D MODE MODE ---TI/O
U
L

DMA
EN

RE
SET

007

006

005

004

003

D02

001

000

IRO
LEV
M

IRO
LEV
L

INTERRUPT VECTOR NUMBER

"
TMSG TBSY

SYS
FAIL

BRO
PRI
U

U/S

BYTE
X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

UPPER BYTE OF DMA ADDRESS
LOWER BYTE OF DMA ADDRESS

X

X

X

X

CONTROLLER COMMAND/STATUS

X

X

X

X

X

CONTROLLER SELECT

X

X

X

X

X

CONTROLLER DATA

Referring to the register map, the top word register resides
at the base address (XXXO). The low byte is the VECTOR
NUMBER register. Each register and its bit functions are
defined below.

this bit must be low for the SASI data to be valid.
This is true when the controller is inserting data
on the SASI bus, and when he is requesting data
on the SASI bus.

D11 -

1/0 indicates the direction the SASI bus is
presently being set by the controller. A '0' means
is inputting data from the controller. A '1'
indicates the SASI is outputting data to the SASI
bus.

D10 -

C/D indicates the type of data being transferred
over the SASI bus. A '0' means a command or
command status is being transferred.

D09 -

BSY* bit indicates the active status of the
controller. BSY* set to '0' indicates the controller
is selected and ready to conduct transactions
over the SASI bus. BSY* set to '1 ' indicates the
controller is waiting for a new command.

D08 -

MSG* indicates that a command has been
completed by the controller.
POWER UP/RESETVALUE - indeterminate

Interrupt Vector Register
Doo the interrupt vector register is programmed
by the user to contain the vector number for the
SASI interrupt service routine.
POWER UP/RESET VALUE - Indeterminatel
Unchanged

DMA Status Register (Read Only)

D14 -

IRO
LEV
U

X

Register Descriptions

D15 -

TEST
ENA
BLE

COUNTER

MIDDLE BYTE OF DMA ADDRESS

Doo-

BRO
PRI
L

DMA COMPLETE* indicates when a DMA
operation has been completed by a '0' being
placed in this bit. When a new DMA operation is
started, the DMA COMPLETE bit is set
automatically to '1'.
BERR indicates that a bus error occurred during
a DMA operation while the SASI was the
master. When a bus error occurs, the DMA
operation is terminated, and an interrupt
request is issued. The address at which the bus
error occurred remains the DMA address
registers. BERR is reset when the DMAEN bit is
set in the CSR register.

D13 -

RESET* is a read only bit which is the state ofthe
SASI bus RESET* signal. Normally, this bit is
used for diagnostic purposes.

D12 -

REQ* is the SASI request line. When this bit is
low, the controller is requesting or presenting
data on the SASI bus. During polled operation,

eSR Register

D07 -

SYSTEM FAIL* is a status bit that can be set (1)
or reset (0) to turn on a red (0) or green (1 ) LED.
The system fail LED is set to red by a hardware
system reset or by programmed access. The LED
is set to green by programmed access only. This
LED is intended to be used as a diagnostic
indicator.

D06 -

U/S allows user or supervisor mode access
when set to '1 '. When set to '0', the SASI
registers can only be accessed in supervisor
mode.

111-17

005 -

BUS REQUEST PRIORITY high bit

004-

BUS REQUEST PRIORITY low bit
The two bus request priority bits select the level
that will be used to request the bus during OMA
operations.
00 - level 0, 01 - level 1, 10 - level 2, 11 - level 3

003 -

TEST ENABLE bit provides selection of the test
mode. By setting this bit to '1 " the SASI control
signals are controlled by bits in the OMA
COMMAND register. and provide wrap-around
of the data transfer handshake bits. Do not set
the test enable bit high when a controller is
connected. See the test mode section for more
details.

0- OMA write is selected. Data is OMNed from
the controller to the memory.
When TEST ENABLE =1, this bit is also the TIIO
test control bit for the SASII/O signal. The I/O
signal will assume the opposite state of this bit.
009 -

OMAEN enables the SASI to start a OMA
transfer. OMAEN is automatically reset to '0'
when the OMA transfer is completed or a bus
error occurs.

008 -

RESET is used to reset the controller. This bit
must be set to '1' then to '0' to reset the
controller.
POWER UP/RESET VALUE - 00

Byte Count Register
002 -

INTERRUPT REQUEST PRIORITY level select
high bit

001 -

INTERRUPT REQUEST PRIORITY level select
middle bit

000 -

INTERRUPT REQUEST PRIORITY level select
low bit. The interrupt request priority level bits
select the level (1-6) to be used for interrupts.
The interrupt request priority bits are binary
coded. If level 0 or 7 is selected, the interrupt
requests are disabled.
POWER UP/RESET VALUE - 00

DMA Control Register
015 -

014 -

013 -

TMSc;l is a test control bit for the SASI bus
MSG* signal. The MSG* signal will assume the
opposite state of this bit when the TEST ENABLE
bit is high.
TBSY is a test control bit for the SASI BSY*
signal. .The BSY* signal will assume the
opposite state of this bit when the TEST ENABLE
bit is high.

015 -

000 The byte count register is used to set the
number of bytes to be transferred during a OMA
operation.
POWER UP/RESET VALUE - 0000

DMA Address Upper Byte Register

007 -

DOO OMA access will begin in the upper
address.This register represents A23 - A 16.
POWER UP/RESET VALUE -Indeterminate/
Unchanged

DMA Address Lower Word Register
015 -

000 OMA access will begin in the lower
address. These bitsrepresentA15 -A01. BitOof
this register is always set to (even address) by
the hardware.
POWER UP/RESET VALUE -Indeterminate
Unchanged

a

Controller Command/Status Register

007 -

000 All command and command status
transfers with the controller are transferred
through this register.
POWER UP/RESET VALUE -Indeterminate

TC/O is a test control bit for the SASI C/O
signal. The C/O signal will assume the opposite
state of this bit when the TEST ENABLE bit is
high.

Controller Select Register

012 -

MODE selection high bit

007-

011 -

MODE selection low bit
Mode bits select the operating mode ofthe SASI.
The four modes are selected by setting the high
and low bits to the binary value of the mode.
00 - MOOEO
01 - MODE 1
10 - MODE 2
11 - MODE 3

010 -

,R/W selects the OMA direction
1 - OMA read is selected. Data is OMA'ed from
memory to the controller.

000 Up to eight controllers can be selected, one
at a time, by setting one of the eight bits of this
register '1 '. A T must be assigned to one bit in
this register before each controller command.
This register may be read to determine which
controller. was last selected.
POWER UP/RESET VALUE - Indeterminate

Controller Data Register

007 - 0 0 0 All data transfers with the controller must
be through this register. Data is specified as any

bytes (except for the controller select, the
command bytes, or the command status bytes)
transferred to or from the controller.
POWER UP/RESET VALUE - Indeterminate

CONTROLLER REGISTER LEGAL ACCESS
CONDITIONS
Table 5
REGISTER

BSY*

I/O

1

X

X
1
1
X

0
0

0
0

C*/D

REQ*

X

X

0

0
0

Register Access
All registers are read/write except the DMA STATUS
register which is read only. The byte registers which contain
all "don't care" bits are not accessible as byte registers. If
access to these "don't care" registers is attempted, the
SASI will not respond with a bus DTACK*.

WRITE SELECT
WRITE COMMAND
WRITE DATA
READ SELECT
READ STATUS
READ DATA

Registers can be accessed as byte registers, with the above
restrictions, or as word registers on even addresses.

X - DONTCARE

While DMA operations are in progress (DMAEN bit set in
DMA CONTROL register), the writes and reads of some
registers are inhibited to prevent the DMA operation from
being corrupted. If an illegal access is attempted, the SASI
will not respond with a bus DTACK*. Illegal register reads
and writes, occurring during DMA operations, are listed in
Table 4.

0
0

1
X

0
1

X

0
0

Interrupt Requests
Interrupt requests can be programmed to levels 1 -6 via the
CSR register. Programming the interrupt level to 0 or 7
disables any interrupt requests from being generated.
Interrupt requests are issued for the following conditions:
a) After any DMA operation is completed. Completion of a
DMA is defined to be when the byte counter counts down to
zero or the controller has completed a command.
b) After a bus error occures during a DMA operation. The
address where the error occurred remains in the DMA
address register.

ILLEGAL/LEGAL REGISTER ACCESS DURING DMA
Table 4

REGISTER

CSR
DMACOMMAND
INTERRUPT VECTOR
DMASTATUS
BYTE COUNT
DMA ADDRESS UPPER
DMA ADDRESS LOWER
CONTROLLER
COMMAND/STATUS
CONTROLLER SELECT
CONTROLLER DATA

(I = ILLEGAL.
WRITE

L= LEGAL)
READ

I
L
I
I
I
I
I

L
L
L
L
L
L
L

I
I
I

L
L
I

Operating Modes
One of four operating modes can be selected for DMA
operations. The mode is selected by setting the MODE bits
of the CSR register to the binary value of the mode number
desired. The four modes are described below.
Mode 0

A restriction for slave access to the controller register, when
the DMA is not enabled, is that they be accessed per SASI
protocol. That is, the COMMAND/STATUS register can
only be accessed when a command or status transfer is
required; the SELECT register may be accessed only when
the controller is to be selected; the DATA register may only
be accessed when data is to be transferred. If access to any
of these registers is attempted when the SASI interface is in
the wrong phase, the VME-SASI will not respond with a
DTACK*. Table 5 specifies the SASI signal conditions
required for legal access to the controller registers. Note
that for any slave access to be legal, the DMA must not be
enabled (DMAEN=O in CSR).

This mode allows data transfers with the controller actually
transferring the data to memory. Each data transfer from or
to the controller requires a handshake sequence to be
performed. When the DMA is enabled, handshakes are
performed until the byte counter goes to zero. Then an
interrupt request is issued, and the DMA is disabled.
Mode 1
This is the byte DMA mode. The SASI performs DMA byte
data transfers to the same short I/O address in the DMA
address reg ister. The Address Modifier codes placed on the
bus are for short I/O. The DMA is complete when the byte
count goes to zero or when the controller command is
completed. An intrrupt request is issued and the. DMAEN bit
is reset on completion of the DMA operation. The DMA
address does not increment in this mode; the same address
is used for all byte data transfers.

111-19

into write DMA's. During read DMA's, the data at the SASI
bus ry during is' going out and cannot be checked.

Mode 2
This is the word DMA mode. The SASI performs word DMA
transfers to the address in the DMA address register. The
Address Modifiers are set for Data accesses. The DMA is
complete when the byte count goes to zero or when the
controller command is completed. An interrupt request is
issued and the DMAEN bit is reset on completion of the
DMA operation. The DMA address continues to the next
even address after a DMA transfer.
Mode 3
This mode is similar to MODE 0; however, the handshakes
are performed with the controller until the command has
been completed. In Mode 0, they are performed until the
byte count goes to zero. DMA data transfers do not occur in
this mode; the data is thrown away. An interrupt request is
issued when the controller command is completed.
User/Supervisor Access
The level of access to the SASI is determined by the state of.
the U/S bit in the CSR register. When the U/S bit is '0', only
the supervisor may access the SASI. When the U/S bit is
'1 " both the user and supervisor may access the SASI.
When both the user and supervisor are allowed access, the
mode of the DMA operation is the same as the mode of the
master that programmed the SASI to do the DMA operation.
That is, if the SASI is programmed in the user mode to do a
DMA transfer, then the address modifier code used for the
DMA transfer will be a user code. If the SASI is programmed
in the supervisor mode, the address modifier codes for the
DMA will be a supervisory code.

This test mode allows the user to verify most of the DMA
master logic used during an actual DMA operation.
Using the VME-SASI with a SASI Controller
An example of how to use the VME-SASI with a SASI
controller for programming purposes is given in this section.
The basic SASI protocol must always be followed, or errors
will occur. The basic SASI protocol is described below, and
an example of a DMA read or write is presented.
SASI Protocol
The protocol discussed here is only applicable to the
software and hardware protocol which must be monitored
by the user program while using the VME-SASI. Interface
signals, which provide status of the present condition of the
interface, are available in the DMA status register. The
description of the status bits is given in the register
definition section. Table 6 presents typical interface phases
identified by the state of the status bits.
The DMA STATUS BSY* bit signifies that the controller is
selected and is either awaiting a command or executing a
command. When the BSY* bit returns high, the command
has been completed, including all of the data and status
transfers to and from the controller.

Using the Test Mode of the SASI

If the controller is in an unknown state, or if execution is
beginning from power up, the controller should be reset. To
reset the controller, set the reset bit of the DMA CONTROL
register highthen low. The STATUS register bits BSY*, I/O,
C/D, and MSG* should be '1' following a reset.

The SASI provides a diagnostic test mode which allows the
SASI to test the SASI interface and perform DMA
operations without a controller connected. The test mode
should be used only when the controller is disconnected.
When the TEST ENABLE bit in the CSR is set high, the test
mode is selected and the SASI signals are controlled as
follows:

The controller sequence to execute a command is constant.
The sequence is as follows. When reading or writing bytes
to the controller command/status, select, or data registers,
ensure that the REQ* bit in the DMA status register is '0'.
REQ* low means the controller either wants data or has
data ready. If the controller registers are accessed before
the controller is ready, a bus timeout will probably occur.

REQ* -'
BSY*-

1) Set the byte count - Write the number of bytes to be
transferred by a DMA operation into the BYTE COUNT
register.

ACK* is connected to REQ*
SEL* and TBSY are logically or'ed and inverted
and then connected to BSY*
1/0R/W is connected to I/O
C/O TC/D is inverted and then connected to C/O
MSG* - TMSG is inverted and then connected to MSG*
RESET* - RESET* is controlled normally through the CSR
register. The RESEP signal itself is read through
the DMA STATUS register.
.
When the TEST ENABLE bit is selected, a DMA read or write
transfer may be performed by setting the SASI signals to the
proper state and then enabling the DMA. Since the SASI
data bus is not connected to anything, all 'O's will be written

2) Set the DMA address - Write the starting address for the
DMA operation into the DMA ADDRESS register.
3) Select the' controller - The controller is selected by
writing a '1 'to the bit number representing the controller to
be selected. Controller selection is done through the
CONTROLLER SELECT register.

111-20

SASIINTERFACE PHASES
Table 6

BSY*

1/0

C/O

MSG*

1

1

1

1

0

1

0

1

0
0
0
0

1
0
0
0

1
1
0
0

1
1
1
0

INTERFACE CONOITION
After a RESET has been issued, or after command status bytes
have been read.
The controller is receiving or is ready for a command from the
SASI. This condition exists after controller selection.
The controller requests data from the SASI.
The controller is putting data on the bus for the SASI.
The controller command status byte is available to the SASI.
The controller sends a message byte to inform the SASI that the
command is complete including the status byte. The next state of
the status bits will be all l's indicating the controller is ready for
selection.

ENDING STATUS: 1/0 = 1, C/D = 0, BSY* = 0, MSG* = 1
4) Send command to the controller - The controller expects
a six or ten byte command. All command bytes must be
written through the CONTROLLER COMMAND register.
The format and exact data for specific commands are
controller dependent.
ENDING STATUS after:
Write command - 1/0 = 1, C/D = 1, BSY* = 0, MSG* = 1
Read command - 1/0 = 0, C/D = 1, BSY* = 0, MSG* = 1
End of command - 1/0 = 0, C/D = 0, BSY* = 0, MSG* = 1
5) For DMA transfers (reads or writes), set DMA direction,
DMA mode, and enable DMA. The final step to initiate the
command sent to the controller and perform the associated
DMA transfers is to set the appropriate DMA MODE, DMA
direction (read or write), and DMAEN bits in the DMA
CONTROL register. The mode and direction should be set
prior to this step. The DMA operation is actually started by
setting the DMAEN bit to '1 '. This is the last step. When the
DMA is completed, the SASI will issue an interrupt request.
ENDING STATUS: The completion of a DMA operation may
not actually be the completion of the command. This
condition may occur if the set byte count is less than the
number of sectors commanded to be read or written.
Therefore, two status conditions can exist at this point.
End of Command Status: 1/0 = 0, C/D = 0, BSY* = 0,
MSG* = 1
Not End of Command Status: 1/0 = X, C/D = 1, BSY* = 0,
MSG* = 1
X = 1 for DMA read, 0 for
DMAwrite

the transaction for any command. The status byte 'must be
zero for a no error status. The status bytes must be read
through the CONTROLLER COMMAND/STATUS register.
When reading the status byte, the REQ* signal must be true
for valid status. The DMA STATUS register bits are given
below.
STATUS AFTER Error Status Byte read:
1/0 = 0, C/D = 0, BSY* = 0, MSG* = 0
7) After the status byte is read, the controller presents a
messag'e to the SASI indicating that the controller is
through with both the command and status phases and will
be ready for a new command after the message is read. The
message must be read through the CONTROLLER
COMMAND/STATUS register. Note that when reading the
message byte, the REQ* signal must be true for a valid
message. The DMA status bits after reading the message
are given below.
STATUS AFTER reading message byte:
1/0 = 1, C/D = 1, BSY* = 1, MSG* = 1
Notice that the BSY* bit went high after the last status byte
was read, indicating that the command was completed.
8) In step 5, if the command data transfer was not
completed, the rest of the data must be transferred by
resetting the byte count to the number of bytes left to be
transferred, or by using MODE 3. If MODE 3 is used, the
data is not used. Handshaking with the controller is
performed simply to complete the data transfer. Status is
then available when the end of the command is reached. If
status is not required, reset could be issued to the controller
to setup for a new command.

6) If the command was completed, the controller presents
one byte of status which must always be read to complete

111-21

ELECTRICAL SPECIFICATIONS
VMEbus Drivers

Power Requirements

Totem-Pole

VOL =0.6 V Max @ 48 MA
V OH = 2.4V [email protected]

Three State

VOL =0.6 V Max @ 48 MA
V OH =2.4 V Min @ 3 MA
loz +50 p.A. [email protected] 2.4 VorO.5 V

+5V

4.75 V to 5.25 V @ 3.5 A Typ. 4.5 A Max

MECHANICAL SPECIFICATIONS

=

Open-Collector

V OH = 0.6 V Max @ 48 MA
IOH = 50 p.A. Max @ 5 V

VM Ebus Receivers

Length:
Width:
Board Thickness:
Component Height:
Connectors:

630 inches (160 mm)
9.20 inches (233.68 mm)
0.062 inches (1.57 mm)
0.5 inches (14.73 mm)
96 pin DIN 41612 Compliant

ENVIRONMENTAL SPECIFICATIONS
'V1L =0.8 V Max
V 1H = 2.0 V Min
V 1L = -400 p.A. [email protected] V > 2.7

Operating:
Temperature Range
Relative Humidity

SASI Bus Drivers (Open-Collector)

Storage:

Bus terminated with 220/330 Ohms

Temperature Range

O°C to 60°C

o to 90% non-condensing

VOL =0.5 V Max @ 48 MA
V OH = 2.5 V Min
SASI Bus Receivers
Bus terminated with 220/330 Ohms
V 1L = 0.8 V Max @ 0.8 MA
V 1H =2.0 V Min
ORDERING INFORMATION

Designator

Description

Part No.

VME-SASI

VME SASllnterface Board with Technical Manual

MK75802

VME-SASI
Technical Manual

VME-SASI Technical Manual only

4420341

111-22

IJ

COMPUTER
PRODUCTS
DIVISION

UNITED
TECHNOLOGIES
MOSTEK

VME-SIO

FEATURES

VME-SIO
Figure 1

o Four independent full-duplex serial channels
• RS-232 Data Rates to 19.2 K Baud
• RS-422 Data Rates to 307.2 K Baud
o VMEbus compatible
o Software programmable Baud Rates
o Software Controllable front panel status LED
o ReadIWrite Control Register
o Software programmable self test mode
o All I/O via Back Plane Connectors
o Asynchronous Operation
• 5,6,7, or 8 bits/character
• 1, 1V2, or 2 stop bits
• Even, odd, or no parity
• X16, X32 and X64 clock modes
• Break generation and detection
• Parity, overrun, and framing error detection
o Binary Synchronous Operation
• Internal or external character synchronization
• Monosync or bisync operation
• Automatic sync character insertion
• CRC generation and checking
o HDLC and IBM SDLC Operation
• Abort sequence generation and detection
• Automatic zero insertion and detection
• Automatic flag insertion between messages
• Address field recognition
• I-field residue handling
• Valid message protected from overrun
• CRC generation and checking
VMESYSTEM
The VMEbus was designed jointly by Mostek, Motorola, and
Signetics and introduced in Oct. 1981. It offers a
combination of high performance timing parameters,
compact form factor, and advanced functional capability
appropriate for today's application of 16-bit microprocessors such as the MK68000.

VME-SIO
The VME-SIO (MK75801-0-01/02) serves as a four
channel full duplex serial communication module for the
VMEbus. The VME-SIO block diagram is shown in Figure 2.
A typical system configuration is shown in Figure 3.
The MK75801-0-01 offers four channels of RS-232(DCE);
the MK75801 -0-02 offers two channels of RS-232(DCE)
and two channels of RS422 data communications.
Each of the four channels is a full duplex serial link. Each
channel is supported with separately programmable Baud
Rate generation.
The VME-SIO can generate and check CRC codes in
synchronous mode and can be programmed to check data
integrity in various modes.
The VME-SIO is programmable for supervisor/user access.
When selected for user access, the SIO can be accessed in
either the supervisor or user state. However, when the
VME-SIO is selected for supervisor space, the module can

111-23

VME~SIO' Bi.6CK DIAGRAM
Figu~"2. '.'

.. ',

:Z>

A16·A01
DS1'

+

ADDRESS
SELECTION

11

~

A04·A01

ADDRESS
LATCH

8<
DECODE

LWORD'

BB,CB
4
r---

lORa', RD'

ce*.MI*

,...-

t----

TEST
2;1

4
SIO

r--oR
BA,CA

'----

4

AB,CC,CF

~

4

~

.. DATA
BUS: .

BUF~ER'

~. ;'007·000

N·;;·;··..

,, .
~

C
L
~

~

lACK'

'.

AMS.AM

0

\ADDRESS
jn.IODIFIER
DECODE

SIO

L-~
r-~

"

1

1
',.>

~

\1

1

~

SYSCLOCK
1

CLOCK
GEN

o

2

IACKIN'
IACKOUT'

1

DTACK'

1

WRITE

1

AS'

1

.Iflax

t-

2

.,

STATE
SEQUENCER·

J

r--

1

o....-L.

CLOCK
GEN

INTERRUPT
CONTROLLER

,1"

1

.6

111-24

RS232
B

~.;
R
RS232/RS422
I
V
BA,CA
E
R
4 ... ;
S
'---01
AB,CC,CF
R
E'
6
CD
C
2
E
DA
RS232/RS422
I
2
V
,.
DB,DD
E
2
R
TEST
2;1

bV
INT'

14

CLOCK
GEN

h

..

DSO'

I

I

J--

~

2

~

f-

f-

DB,DD

RS232

BB,CB

4
~

2

DA

r-

1

6

CD

I.,
V
E
R
S
1
R
E
C
E
I
V
E
R
~

SYSTEM CONFIGURATION DIAGRAM
Figure 3

r-

r~-~

V'

P2

~

VA

~

~

II

[~

ADDRESS
SELECTION

VME·SIO
,--

C

"'"
P1~
'---

SERIAL
CHANNEL

A

SERIAL
CHANNEL

B

SERIAL
CHANNEL

C

SERIAL
CHANNEL

D

'}

I

I

VMEbus

only be accessed in the supervisor state. When accessed by
the user state when programmed for supervisor state, the
module will not respond with DTACK*. Programming ofthe
user/supervisor state is via the module's control register
(CR).

the transmit of each channel is looped back into the receive
side of the same channel, thus enabling the use of self test
diagnostics. The switching is on the MK3887 side of the
channel driver/receivers, so it is not required that the
module be disconnected from the serial transmission lines
in order to use this feature.

The VME~SIO is programmable for interrupt priority levels
via the module's control register (CR). The module provides
an interrupt vector as described by the VMEbus Technical
Specification. Each MK3887-4 SIO chip may provide a
unique vector, thereby allowing separate service routines
for the RS~232 and RS~422 I/O ports.
The module's address strapping is accomplished via the P2
(J2 backplane) connector. The address strapping allows the
VME~SIO module to exist anywhere within the short I/O
addressing space on 32 byte boundaries. Only Byte (8 bit)
data transfers are supported. If a word or longword transfer
is attempted, the VME~SIO will not respond with a DTACK*.
A facility for on~line self test mode is provided via the self
test bit in the modules control register. When this bit is set,

111-25

VMEbus INTERFACE INSTALLATION
The VME~SIO mates with the VMEbus Standard
connections as defined by the VMEbus Technical
Specification. The P1 signals are defined in Table 1. The P2
signals are defined in Table 2.
Table 1 identifies the VMEbus backplane J1 /P1 connector
pin assignments for the VME~SIO. The table lists the pin
assignments by pin number order. (The connector consists
of three rows of pins labeled rows A, B, and C.) All signal
pins defined by the VMEbus Technical Specification are
listed; those not used by the VME~SIO are indicated as (NC).

J1/P1 PIN ASSIGNMENTS VME-SIO
Table 1

PIN
NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
. 23
24
25
26
27
28
29
30
31
32

I';'
"

!

ROWA
SIGNAL
. MNEMONIC

ROWB
SIGNAL
MNEMONIC

ROWC
SIGNAL
MNEMONIC

D01
D01
D02
D03
D04
,D05
D06
D07
,GND
SYSCLK
GND
DS1*
DSO*
WRITE*
GND
DTACK*
GND
AS*
GND
IACK*
IACKIN*
IACKOUT*
AM4
A07
A06
A05
A04 .
A03
'A02
A01
-12 V
+5V

BBSY* (NC)
BCLR* (NC)
ACFAIL* (NC)
BGOIN*
BGOOUT*
BG1IN*
BG10UT*
BG2IN*
BG20UT*
BG3IN*
BG30UT*
BRO* (NC)
BR1* (NC)
BR2* (NC)
BR3*(NC)
AMO
AM1
AM2
AM3
GND
SERCLK(1) (NC)
SERDAT (1) (NC)
GND
IRQ7* (NC)
IR06*
IR05*
IRQ4*
IRQ3*
IRQ2*
IR01*
+5 V SroBY (NC)
t5V

D08(NC)
D09(NC)
D10(NC)
D11 (NC)
D12 (NC)
D13 (NC)
D14(NC)
D15 (NC)
GND
SYSFAIL*
BERR*
SYSRESET*
LWORD*
AM5
A23(NC)
A22(NC)
A21 (NC)
A20(NC)
A19 (NC)
A18 (NC)
A17 (NC)
A16(NC)
A15
A14
A13
A12
A11
A10
A09
A08
+12 V
+5V

NOTE:
SERCLK and SERDAT represent provision for a special serial communication
bus proto,?ol still ,being fjnalized.

Table 2 identifies the VMEbus backplane J2/P2 pin
assignments for the VME-SIO. The table lists the pin

assignments by pin number order. (The connector consists
of three rows of pins labeled A. B. C.)

J2/P2 PIN ASSIGNMENTS VME-SIO
Table 2

PIN
NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

ROWA
SIGNAL
MNEMONIC

ROWB
SIGNAL
MNEMONIC

ROWC
SIGNAL
MNEMONIC

CA15
CA13
CA11
CA09
CA07
CA05
(TXA)BA
(RXA)BB
(RSETA)DD
(DSRA)CC
(DTRA)CD
(TSETA)DA
(TXB)BA
(RXB)BB
(RSETB)DD
(DSRB)CC
(DTRB)CD
(TSETB)DA
(TXC)BA
(RXC)BB
(RSETC)DD
(DSRC)CC
(DTRC)CD
(TSETC)DA
(TXD)BA
(RXD)DD
(RSETD)DD
(DSRD)CC
(DTRD)DD
(TSETD)DA
(N/C)
(N/C)

+5
GND
(N/C)
(N/C)
(N/C)
(N/C)
(N/C)
(N/C)
(N/C)
(N/C)
(N/C)
GND
+5
(N/C)
(N/C)
(N/C)
(N/C)
(N/C)
(N/C)
(N/C)
(N/C)
GND
(N/C)
(N/C)
(N/C)
(N/C)
(N/C)
(N/C)
(N/C)
(N/C)
GND
+5

CA14
CA12
CA10
CA08
CA06
(N/C)
(TSETA)DB
(RTSA)CA
(CTSA)CB
(GNDA)AB
(RSLDA)CF
(N/C)
(TSETB)DB
(RTSB)CA
(CTSB)CB
(GNDB)AB
(RSLDB)CF
(N/C)
(TSETC)DB
(RTSC)CA
(CTSC)CB
(GNDC)AB
(RSLDC)CF
(N/C)
(TSETD)DB
(RTSD)CA
(CTSD)CB
(GND DD)AB
(RSL DD)CF
(N/C)
(N/C)
(N/C)

111-27

ADDRESS STRAPPING

MK75602-0-01 TO RS-232 CONNECTOR

The VME-SIO module may be configured to reside on any
32 byte boundary within the short 1/0 page. The short 1/0
page is at base hex address FFOOOO through FFFFFF.
Therefore, eleven address lines must be configured by the
installer, A 15-A5.
All ofthese address straps are available on the P2 connector
per Table 3. By having the straps on P2, the system is
configured one time at the backplane and the VME-SIO has
no configuration straps at all.
These pins may be configured in any convenient manner on
the backplane. The polarity ofthe pins is logically true. Strap
the pins to ground if a zero address is desired; otherwise,
allow the pin to remain open. For example, the base address
with all pins open is FFFFEO; all pins strapped to ground
results in a base address of FFOOOO.
ADDRESS STRAPPING PINS

Table 4

SIGNAL PIN NO.
NAME
EIA
RS-232 RS-232

CA
CB
CC
AB
CF
DB
DO
CD
DA

7
8
15
17
20
24

a

b

c

d

7a
8a
8c
9c
10a
10c
11c
7c
9a
11a
12a

13a
14a
14c
15c
16a
16c
17c
13c
15a
17a
18a

19a
20a
20c
21c
22a
22c
23c
19c
21a
23a
24a

25a
26a
26c
27c
28a
28c
29c
25c
27a
29a
30a

MK758010-0-02 2 CHANNELS TO RS-232
CONNECTOR
Table 5

Table 3

A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15

2
3
4
5
6

BA
BB

VME-SIO P2 PIN
CHANNEL NO.

SIGNAL PIN NO.
NAME
EIA
RS-232 RS-232

P2-6a
P2-5c
P2-5a
P2-4c
P2-4a
P2-3c
P2-3a
P2-2c
P2-2a
P2-1c
P2-1a

BA
BB
CA
CB
CC
AB
CF
DB
DO
CD
DA

VME-SIO P2 PIN
CHANNEL NO.
a
b
13a
14a
14c
15c
16a
16c
17c
13c
15a
17a
18a

7a
8a
8c
9c
10a
10c
11c
7c
9a
11a
12a

2
3
4
5
6
7
8
15
17
20
24

NOTE:
The EIA RS-232 connector is a OB-25 type.

TEST POINTS
The 8-pin header labeled J1 on the silkscreen is intended
for factory test purpose only. No user strapping is required.

MK758010-0-02 2 CHANNELS TO MOSTEK RS-422
CONNECTOR
Table 6

SCRAMBLER CABLING

PIN NO.
MOSTEK
RS-422

Because of the use of P2 as the interface connector, a cable
must be constructed to obtain EIA RS-232 standard pin outs
or Mostek standard RS-422 pin outs. This may be done in
any manner convenient to the installer.
In order to connect the MK75801-0-01 (4 channels RS232) to standard RS-232 connectors, refer to Table 4.
In order to make standard connectors to the MK75801-002 (2 channels RS-232, 2 channels RS-422), refer to Tables
5 and 6.

SIGNAL
SIGNAL
RS-422

SIO PIN ON P2
CHANNEL NO.

c

d

5
1
2
8

TXD+
TXC+
TXCRXD-

19a
20a
20c
21c

25a
26a
26c
27c

9,10
4
6
7
3

GND
RXCTXDRXD+
RXC+

22c
23c
19c
21a
23a
24a

28c
29c
25c
27a
29a
30a

NOTES:
1. The RS-422 pin outs only apply to channels 2 and 3.
2. The Mostek RS-422 connector is a 10 pin header.

111-28

APPLICATIONS

CR-LED CONTROL

The registers of the VME-SIO are summarized in Table 7.
Their uses are detailed in the following section.
M1 REGISTER
Since the VME-SIO uses a Z80 serial 1/0 chip to perform its
function, a means of synthesizing the Z80 interrupt
behavior was devised. The MK3887 needs a signal called
M 1* to allow interrupts to be enabled. A Z80 CPU normally
would provide this signal. A register is available at hex
address 01 relative to the board base address for this
purpose.
After enabling interrupts on the MK3887, this register must
be written to. The data that is written to this register should
be a zero.

Bit 07 in the CR controls the led on the edge of the card. A
logical zero loaded in this bit lights red, a one lights green.
This lamp is intended for use as an indicator for diagnostics
performed on the VME-SIO module, but may be used for
any indicating function.
CR-SELF TEST
Bit 05 causes the transmit data to be connected to the
receive data for each channel. This allows diagnostics to be
written to test the VME-SIO.
CR-USERISUPERVISOR ENABLE

If hex data EO followed by 40 is written to this port, the
MK3887 serial 1/0 chip will perform a return from
interrupt, resetting all interrupt hardware.

Programming CR bit 06 to a logical one allows the card to be
available in user mode. The card is available to the bus in
supervisory mode at all times. If programmed to a zero, only
the supervisor can access the card. User requests will not
generate a OTACK* on the VMEbus when 06 =O.

CONTROL REGISTER

CR-INTERRUPT PRIORITY

The VME-SIO has a Control Register (CR) which contains a
variety of functions. It has an offset from the board base
address of 03 hex.

Bus interrupt priority levels 1-6 may be produced on the
VME-SIO. The desired priority level is programmed in CR
bits 02, 01, 00.

111-29

REGISTER SUMMARY VME-SIO
Table 7

AOOR OFFSET
FROM BASE
AOOR.

07

06

05

03

.04

02

01

DO

M1

01
03

i

i··· .
i'--

SIO REGISTER

STATUS
LED

USER
SUPV

SELF
TEST

X

X

I·
P

N
R

T
I

CONTROL

05

NOT USED

07

NOT USED

09

X

X

X

SYNC

B
R

A
A

U
T

0
E

CHANNEL 0

OB

X

X

X

SYNC

B
R

A
A

U
T

0
E

CHANNEL 1

00

X

X

X

SYNC

B
R

A
A

U
T

0
E

CHANNEL 2

OF

X

X

X

SYNC

B
R

A
A

U
T

0
E

CHANNEL 3

11

CHANNEL 0
DATA

13

CHANNEL 0
COMMAND

15

CHANNEL 1
DATA

17

CHANNEL 1
COMMAND

19

CHANNEL 2
DATA

1B

CHANNEL 2
COMMAND

10

CHANNEL 3
DATA

1F

CHANNEL 3
COMMAND

NOTE:
X = bit not used.

BAUD RATE REGISTERS
Baud rates on the VME-SIO are fully programmable. Each
channel has an independent register consisting of five bits.
Bit 4 selects the source of the Baud rate clock. When
programmed to a one level, the clock is provided via the

interface. This is the normal case in the synchronous mode.
When programmed as a zero, the clock is produced by an on
board generator. The rate ofthis clock is programmed by the
remaining four bits in the register as shown in Table 8.

111-30

BAUD SELECTION RATE
Table 8

03

02

01

DO

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0

0
0

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1
0
0
1
1
0
0
1
1
0
0
1
1

X1

X16
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200

800
1200
1760
2152
2400
4800
9600
19200
28800
32000
38400
57600
76800
115200
153600
307200

X32

X64
12.5
18.75
27.5
33.63
37.5
75
150
300
450
500
600
900
1200
1800
2400
4800

25
37.5
55
67.25
75
150
300
600
900
1000
1200
1800
2400
3600
4800
9600

NOTE:
The selection of the Xl, X16, X32, X64 divisor modes is a function of the
MK3887 serial 110 chip.

CHANNEL DATA REGISTERS
+5 volts +5%, -2.5% @ 3.5 A max
The channel data registers are the actual data registers on
the MK3887 SIO components. Refer to the Mostek Z80
Microcomputer Data Book for detailed programming
information.

+12 volts +5%, -3% @ 300 ma typical
-12 volts +5%, -3% @ 300 ma typical

CHANNEL COMMAND REGISTERS

PHYSICAL SPECIFICATIONS

The channel command registers are the actual command
(Vl/W0-->WW7, RWO-->RW3) on the MK3887 SIO
components. Refer to the Mostek Z80 Microcomputer Data
Book for detailed programming information.

LENGTH

6.30 inches (160 mm)

WIDTH

9.20 inches (233.68 mm)

BOARD THICKNESS

0.062 inches (1.57 mm)

WEIGHT

0.83 Ibs. (0.37 kg)

ELECTRICAL SPECIFICATIONS
VMEbus DRIVERS
CONNECTORS
Totem-Pole

VOL = 0.6V [email protected] ma
V OH = 2.4 V MIN @ 3 ma

96 pin, IEC Standard (603-2 IEC-C096-M)

Th ree-state

VOL = 0.6 V MAX @ 48 ma
V OH = 2.4 V MIN @ 3 ma
IOH = 50 Ila MAX @ 2.4 V or 0.5 V

OPERATING TEMPERATURE RANGE

Open Collector

VOL [email protected]
IOH = 5011 [email protected]>V>2.7V

RELATED PUBLICATIONS

RS-232 PROTOCOL
RS-422 PROTOCOL
POWER REQUIREMENTS

The following technical publications may be helpful in using
the VME-SIO:
VMEbus TECHNICAL SPECIFICATION
Z80 MICROCOMPUTER DATA BOOK
111-31

ORDERING INFORMATION

DESIGNATOR

DESCRIPTION

PART NO.

VME-SIO

4 channels RS-232 VMEbus compatible serial 1/0 board
with Technical Manual

MK75801-01-01

VME-SIO

2 channels RS-232, 2 channels RS-422 VMEbus compatible
serial liD board with Technical Manual

MK75801-0-02

VME-SIO
Technical Manual

Technical Manual only

4420343

111-32

I!I

COMPUTER
PRODUCTS
DIVISION

UNITED
TECHNOLOGIES
MOSTEK

VME-FDC
VME FLOPPY DISK CONTROLLER
MK75803
FEATURES

VME-FDC
Figure 1

o VMEbus compatible
o Word DMA or programmed byte data transfer over
VMEbus
o Programmable to control up to four 8 inch or four 51.4
inch drives
o Programmable VME Interrupt Priority levels
o Jumper selectable VMEbus Request level
o Selectable I/O address on P2 connector
o Single and Double density formats

o

51.4 inch Quad density capability

o Controls single and double sided disk drives
o Soft sector operation, including variable-length sectors
o IBM 3740 and System 34 diskette formatting capability
for single or double density format, and 8 inch or 514 inch
drives and selection of write precompensation are
programmable thro.ugh the on-board drive control register.
The capability to use 514 Quad density drives is provided by
jumper selections.

o Automatic track seek with verification
o Programmable step rate
o Single sector, multi sector or full track data transfers

Transfers are normally performed between the disk and
memory in standard addressing space, in a Direct Memory
Access (DMA) mode. DMA operations transfer 16 bit words
to conserve VMEbus time. Programmed data transfers can
also be performed using byte transfers. End of command
interrupt requests can be generated on one of the IRQ1-6
lines. Selection of the Interrupt Request level is
programmable through the control register. Bus request
levels for the DMA transfers are selected by on board
jumpers.

o Automatic CRC generation and checking
o Interrupt driven or polled operation
o Programmable write precompensation
o 1 Year Warranty
DESCRIPTION
VME-FDC is a floppy disk drive controller board for the
VMEbus. The VME-FDC board provides all required
controlling, formatting, and interface logic between the
VMEbus and one to four floppy disk drives.
VME-FDC can control single or double sided 51.4 or 8 inch
Shugart compatible disk drives. Also 8 inch or 514 inch
drives may be used. All controls to configure the VME-FDC

The VME-FDC provides a 256 byte FIFO data buffer. The
DMA controller writes data to or reads data from the FIFO
until the specified number of words are transferred. The
FIFO data buffer allows floppy data transfer rates to be
buffered between the VMEbus and the disk preventing data
overflow/underflow conditions. The FIFO data buffer is not
used during programmed data transfers.

111-33

VME-FDCBLOCK DIAGRAM
Figure 2
1.
TO FLOPPY

P2

WD1797 FLOPPY

DR~VES

CONTROLLER

AND DRIVE
INTERFACE

INTERRUPT
CONTROL

MASTER/SLAVE
CONTROL

BUS
REQUEST/
RELEASE

. CONTROL

SYSFAii iRQ i"Ac'Ki"N iACi iiSv
1·6

OUT

BR

BG

BG

0·3

IN;

OUT

AS

0S0 i5S1 WRiTEiiTACK iiE'R"R

VMEbus

The VME-FDC includes a WD1797 Floppy Disk Contoller
chip which provides advanced features including IBM 3740
or IBM System 34 diskette formatting capability, automatic
track seek witllverification, programmable step rate, and
automatic CRC generation and checking. In addition, single
sector, multi-sector, or complete track transfers are
possible.
"

Width
Board Thickness

9.20 in. (233.7 mm)
.062 in. (1.57 mm)

Connectors
96 Pin, IEC Standard (603-2 IEC-C096-M)
ELECTRICAL SPECIFICATIONS

The daisy chain bus request and interrupt request
configuration of the VMEbus allow multiple VME-FDC
boards to be used in a system. Each VME-FDC board 1/0
address, within short I/O address space, is selected (16
word increments) by jumpering on the P2' connector of the
board.
Functional control of the VME-FDC is provided through a
control register. Specific control for selection of Interrupts
levels, DMA mode, User/Supervisoraccess:ahd diag"nostic
status is provided. A red/green bi-color LED provides the
user a means of displaying the diagnostic status of the
board.
PHYSICAL SPECIFICATIONS
Board Dimension
Length

VMEbus compatible
Shugart compatible floppy disk drive interface
Power Supply Requirements
+5 V +5%, -2.5% @ 3.5 A lYP.
+12 V ±5% @ 1 ma Max.
OPERATING TEMPERATURE
Oto 60°C
HUMIDITY
10"A> to 90% non-condensing

6.30 in. (160 mm)
UI-34

SYSTEM CONFIGURATION DIAGRAM
Figure 3

1\

\

.-I

P2

'--

VME-FDC

.P1

,;

II

\
I

DRIVf 1

n

1\

\
.I

~DRLs

DRIVE 2

v

8" OR

SELECTION

DRIVES

~

)

;t

DRIVE 3

Y

\r
-

..

~

~

V

""-...7
VMEbus

111-35

DRIVE 4

ORDERING INFORMATION
Designator

D~scription

Part No.

VME-FDC

VME Floppy Disk Controller with Technical Manual

MK75803

VME-FDC
Technical Manual

VME-FDC Technical Manual only

4420341

111-36

!l

UNITED

COMPUTER
PRODUCTS
DIVISION

TECHNOLOGIES
MOSTEK

VME-DRAM256
VME DYNAMIC RAM MEMORY CARD
MK75701
FEATURES

MK75701
Figure 1

o 256KB of Dynamic RAM
o 5Vonly
o Byte parity with diagnostic support
o Control and Status register
o VMEbus slave
o 23 bit address
o Address and data-in latches
o On-board refresh
o LED indicates board status
o Software programmable starting address
o Byte, word, and longword transfer
o Dual connector, 160 MM Euro-card format
DESCRIPTION

Performance'

The MK75701 is Mostek's VMEbus compatible dynamic
RAM board. The board features self-contained parity
generation and checking on all data stored in its array. The
Control and Status Register allows software control and
diagnosis of board functionality, thus facilitating system
diagnostics. The programmable starting address register
allows automatic system configuration. Address modifiers
are decoded in a PAL which allows the possibility of custom
changes in the use of the modifiers. A board edge mounted
LED glows green to indicate proper operation of the card
and red in the event of a parity error. All refreshing of the
dynamic RAM's is controlled automatically by on-board
circuits.

Access Time
Cycle Type

Typ

Max

Typ

Max

Read, Non-parity

388

430

418

460

Read, parity

434

484

464

514

Write

200

236

377

413

Read/Modify/Write

680

776

710

806

Operating Temperature:
Storage Temperature:

SPECIFICATIONS

Humidity:

Power:

Operating Altitude:

Capacity:

+5 Vdc at 4.9 A
64K x 36 or 256 K byte

Memory Cycle Types:

Read, write, and read-modify-write

Cycle Time

0 to 60°C

-40 to 125°C

10 to 90% without condensation
10,000 feet

Dimensions:

160 x 233 mm (6.3 x 9.2 inches)

Compatiblity:

VMEbus compatible

111-37

BLOCK DIAGRAM - ADDRESS AND CONTROL
Figure 2

~~~B~E~RR~'______-4~
SYSFAIL'
(f) ffi
~-----------I
:;»

OTACK'

'"

~

'----

..
BGOOUP -BG30UP

"
BGOIN'-BG31N'

I
WRITE'3

,...---

WRITE'2

:I:

U

,...---

S
A16-A23

,...---

WRlTE'O
N

:::;

Ii:~~
;:O~

V

(f)«0:

:I:

U

f-

~

U

(f)

A1-A15

ell

v

(f)
(f)
W
0:
0
0
«
(f)
:;)

'"2W
>

,...---

AM5

0

2
W
2
f-

a;

~~w

y

>0:

cD

fJ5 ~
uOU
OW

8

«0

M

U

(3
0

..J
..J

0
0:
f2
0

U

CAS'
RAS'

0
2

r------

«
~

2

~
;:::

-

0:

AM4

':!:!w

!:!:o

AM3

00

ou
:ii 0W

AM2

(f),
(f):I:

AM1

SYSFAIL CTRL

wu

O:f-

AMO

0:

8~

W

-----

lACK'

f(f)

«

IACKOUP
IACKIN'

1\

~~
v

Jr~

II

CA1-CA15

r------

0:
0
2
(f)
(f)
W
0:
0
0
«

"
,...---

«

2

2(f)W
-Wf-

'---

0:

«

~(f)0:

0
0:
f2
0

>«
0:

W

v

'---

..J

WRITE'1

•

(f)
(f)
W
0:
0
0
«

-

I

(3
W

0:
(f)
:;)

S
(f)

ell

SYSRESEP
LWORO'
WRITE'
DS1'
OSO'

..J

,...---

ERROR/RESET
BANK

(f)
0:

~~
",w

ERROR BYTE 0-3

U
w

0:

AS'
'----

~

111-38

o

0:

~

o
u

.Bl~
c 0
c; C')
W,",

o

;'

'\
VME BUS DATA

'I

0

0

~

c;>

0

'"

V

. ..

0

0

0

CD

N

b

. '"

" ,.. '" ,.

0

~

b
N

b
0

"

loo-

l

DATA IN LATCH/RECEIVER

I

I

I

I

I

I

I

;:;;

~

DATA
BUFFER

•

LDOOO·LDOO7

CONTROL
AND
STATUS

0

;;::
0

is

is
CD

C

~

~

l-

,---

I--

I-I--

.... ....

.

l:

l:

0

0

is

g

"!7 U;!7

I

~

;;::
0
;:;

0

l:0"

.l:

. "',.
;:;

~!7

0

-'"

"C

N

~T1

~-

~-

OJ J .

STARTING
ADDRESS
REGISTER

Ii

DATA OUT
LATCH

m

PARITY
GENERATOR

;;::

o

0

f"

'"

''""

~

!7

4

»0.

I

>-

DATA OUT
LATCH

PARITY CHECKER

.

~.

~-

j>--

.~

I--

lil1111 >-

MD024·MD03l

I I I I I
;;::

N

~

V

~

II

0

-

LDOOS·LD015

~

I--

'\

0'"
~

DATA OUT
DRIVERS

-y

I

CD

a:
0
U;

0
0

~

loo-..

0 ... •

0

MD016·MD023

.
~..'"
:;;

'"
i';

~

'"

".'"

I I I
MDOOS·MD01S

0

~

~

'""'~

w

36-BIT MEMORY ARRAY

MDooo.MD007:

II

~::XJ
):0,
s:-

1

~
~

ORDERING INFORMATION
Part No:

Designator

Description

VME-DRAM256

MK75701-A-OO
VMEbus compatible memory board with 256 K bytes of
Dynamic RAM and 8ytewyde parity; includes Technical Manual

VME-DRAM256

VME-DRAM256 TM

•

VMEbus compatible memory board with 256 K bytes of
Dynamic RAM, without parity; includes Technical Manual

MK75701-8-00

Technical Manual only

MK75701-0-ZZ

111-40

l!J

UNITED

COMPUTER
PRODUCTS
DIVISION

TECHNOLOGIES
MOSTEK

VME-MMCPU
MEMORY MANAGING CENTRAL PROCESSING UNIT
MK75602
FEATURES

VME-MMCPU
Figure 1

o VMEbus compatible
o 68000 Processor and 68451 Memory Management Unit
o 128K bytes (to 512K bytes) on-board Dynamic Random
Access Memory (RAM)
o Byte parity generation and checking for RAM
o Dual-port RAM; accessible from 68000 and from
VMEbus
o Programmable VMEbus base address for RAM
o Programmable response to VMEbus Interrupt Requests

1-7
o Two on-board (EP)ROM sockets, 16K bytes (to 64K bytes)
o 8 MHz operation
o +5Vonly
vendors or by the user, Mostek VME boards are totally
compliant with the VMEbus Specification, ensuring fully
functional operation with all other VMEbus compatible
modules.

o 1 year warranty
o Suitable for multiprocessor systems
The VMEbus was designed jointly by Mostek, Motorola, and
Signetics, and was introduced in October, 1981. It offers an
attractive combination of high performance timing
parameters, compact form factor, and the advanced
functional capability appropriate for today's applications of
16-bit microprocessors such as the MK68ooo. With
features such as expansion to 32-bit address and data, an
independent serial communications bus, and open-ended
transaction coding, it provides for tomorrow's applications
as well, assuring the user of a compatible upward growth
path for years to come. The international-standard compact
board size promotes functional modularity and low board
cost, and allows the user to select only those functions
needed for his application.
Mostek's VME board product line provides an everexpanding family of general-purpose modules, applicable to
a wide variety of systems and applications including data,
word, and image processing, communications, industrial
automation and robotics, data acquisition, and software
development. For specialized functions provided by other

VME-MMCPU DESCRIPTION
The VME-MMCPU is a state-of-the-art, high density
processing element which includes a 68000 processor, a
68451 Memory Management Unit(MMU), and 128K bytes
of read-write memory. The DRAM subsystem includes byte
parity checking, and can be programmed to be accessible to
privileged external masters on the VMEbus. The base
address of DRAM on the VMEbus can also be programmed
to start at any multiple of 4K bytes.
The MMU stands between the 68000 and all on-board and
off-board elements of the system, providing address
mapping and access privilege checking on all cycles. The
MMU "completes" the architecture of the 68000 by
providing a meaningful distinction between the Supervisor
(operating system) and User (application) modes of
operation, as well as allowing a distinction between Code
(program) and Data address spaces and segments. Use of a
Memory Management facility is essential to prevent inter-

111-41

VME-MMCPUBLOCK DIAGRAM
FigureZ

t-1~------I [> I-"A.",A::;M..---I

!-,P;:.:H.:.:YS",'C",A:o.;LA",D""C2::':!...'

.

ADDR
DECODE
A7:1

MMU

ONTRO
SIGNALS

CTRL

V

V

M

M
E'

E


CSA'S

BUS BASE AD (12)

..-1--.........

[>

BUS
ARB'-

TRATION

t------.."..j

C>

LOCAlDATA(16}

D(16)

L-------fility to
multi-processor systems: the MMU facility, the VMEbus
accessibility of on-board ,RAM at a programmable base
address, and the fact that the MMCPU does not request or
use the VMEbus.except as necessary. Once it has acquired
use of the VMEbus, the MI\iICPU will retain VMEbus control
if no other master is requesting the bus, thereby improving
performance for subsequent cycles on the VMEbus.
Performance in a multi-master or multi-processor system is
further enhanced by the fact that the MMCPU will release
the Bus Busy signal during a cycle on the VMEbus, allowing
overlap of arbitration for the next master with the current
data transfer cycle by the MMCPU.
The. MMCPU design includes provIsion for future
expansibility in several areas to provide the user with a
product with compatible growth potential .as future LSI and
VLSI devices become available. The design includes
provision for the following types of expansion:
RAM:

Nine multiplexed address lines are provided,
allowing use of 256K DRAM chips when

available, for a total on-board read-write
memory of 512K bytes.
(EP)ROM: Address jumpering is provided for MK38000
masked ROMs, and for 27128 and pr.ojected
27256 type EPROMs, for a total non-volatile
memory of 32K bytes (27128) or 64K bytes
.(MK38000 or 27256).
Speed:

The basic design comprehends 10 and 12 MHz
operation, with some parts changes, when
enhanced-speed MMU's become available.

Additional MMCPU versions including these enhancements are in the planning stages at this time.
In the standard notation put forth by the VMEbus.
Manufacturers' Group in the VMEbus Specification, the
MMCPU is described as follows:
MASTER A24:D16:

Drives 23 address lines (16 Mbytes)
for Standard Address Space
transactions.
Drives 15 address. lines (64K bytes)
for Short 10. transactions.
Drives and monitors 16 data lines,
Word and Byte transfers.·

SLAVE A24:D16:

REQUESTER:

INTERRUPT
HANDLER:

Decodes 23 address lines for
Standard Address Space transactions.
Drives and monitors 16 data lines,
Word and Byte transfers.

ENVIRONMENTAL
OPERATING
TEMPERATURE:

Release on Request (ROR)
Early Release capability (during AS*
low)
Any of R(3), R(2), R(1), R(O) (STAT,
jumpered)

POWER:

o to 60°C ambient (allows for 10°C
local rise)
HUMIDITY: 0-90",,6 RH.

PHYSICAL
CONFIGURATION:
PHYSICAL:

Anyone of IH (x - y) (DYN,
programmed) where 1 :5 x:5 7 and
x:5y:57

5.5 A max @ + 5.25 VDC (4.3 A typ
at +5 VDC)

EXP (for power not bus expansion)
Length 6.30 in. (160 mm)
Width 9.20 in. (233.7 mm)
Board Thickness .062 in. (1.6 mm)
Weight 1.15 lb. (0.52 Kg)

ORDERING INFORMATION
Designator

Description

Part Number

VME-MMCPU

VME-MMCPU with Technical Manual

MK75602-8 (8 MHz)

VME-MMCPU
Data Sheet

VME-MMCPU Data Sheet only

4420374

VME-MMCPU
Technical Manual

VME-MMCPU Technical Manual only

4420375

111-43

111-44

m

UNITED

COMPUTER
PRODUCTS
DIVISION

TECHNOLOGIES
MOSTEK

VME BASELINE SYSTEM
MK75101
FEATURES
VME BASELINE SYSTEM
Figure 1

o 68000 CPU

o

Down load firmware

o

Five RS-232 Channels

o

Two Timer Counters

o

256K Bytes of Dynamic RAM with byte parity

o

12.25" high x 19" rack mount or Table Top Enclosure

o

VMEbus compatible backplane with extended address
and data paths

o

Seven VMEbus slots available for expansion

o Two I/O Panels (for serial I/O)

o

Provision for six additional I/O panels

o

500 watt power supply

o

Provisions for mounting three 5%" disk drives

o

Monitor/debugger firmware

o

Interfaces optional DEC-host cross-assembler

three 5%" disk drives. The standard 500 watt power supply
has 420 watts remaining to power drives and additional
boards.

BASELINE DESCRIPTION
The VMEbus Baseline System is intended for use by those
people who are developing VMEbus compatible boards. It
also allows for evaluation of the VMEbus by providing an
electrical baseline. as well as facilitating development of
dedicated applications. The system comes standard with a
10 slot VMEbus compatible backplane equipped with three
VMEbus boards:
VME-SBC
VME-SIO
VME-DRAM
Together. they provide the 68000 processor. five serial I/O
channels. 256K bytes of DRAM. 12K bytes of static RAM.
interrupt control. and two timer/counters. The seven
remaining slots allow for ample system expansion and
board development. There is also provision for mounting

The system comes standard with a firmware monitor/
debugger program. Optional DEC-host software is available
for cross-development of 68000 programs.

FIRMWARE
The monitor performs the following functions:
a) Initialization -

Sets up and conditions the proto system
for use; includes I/O ports and memory
boards.

b) Diagnostics -

Performs minimal memory confidence
tests and a checksum test on the
firmware.

c) Transport
mode -

111-45

Allows interfacing to a host system and
provides serial down line loading of

6Sooo binary files in Mostek Hex
. format or Motorola EXORmacs SRecord format.

-115 watts (this configuration)
720 watts (maximum)
Physical

d) Error
Processing -

e) I/O Drivers -

Height - 12.4 inches (315 mm)
Length - 25.9 inches (65S mm)
Width - 17.9 inches (455 mm)
Weight - 65 Pounds (29.5 kgs)

Handles errors from bus timeout,
sysfail, acfail, and I/O errors.
Provides interface to console device and
serial down line load channel.

Environmental
The debugger supports the following commands:
a)
b)
c)
d)
e)
f)
g)

Display/Modify memory
Display/Modify register
Set/Clear breakpoint
Start program execution
Step program
Fill, Locate, Verify memory contents
Convert hex to/from decimal
h) Disassembler
i) Help - Command usage summary
j) Read - Down load a program

Maximum ambient temp. with disk drives - 30°C
Maximum ambient temp. without disk drives - 45°C
ORDERING INFORMATION
DESCRIPTION

PART NO.

Baseline 115 V Table Top

MK75101-S-11

Baseline 115 V Rack Mount

MK75101-S-21

Baseline 230 V Table Top

MK75101-S-12

Baseline 230 V Rack Mount

MK75101-S-22

SPECIFICATIONS
Electrical
115 Vac (90-132) 47-63 Hz
230 Vac (1S0-264) 47-63 Hz

111-46

1983 COMPUTER PRODUCTS DATA BOOK

STD-Z80 Bus

IJ

UNITED

COMPUTER
PRODUCTS
DIVISION

TECHNOLOGIES
MOSTEK

STO-Z80 BUS SYSTEMS

INTRODUCTION

purpose STD BUS. This bus is defined extensively for the
zao microprocessor and its supporting peripherals. By
specifying the STD-ZaO BUS, exact functional pin
descriptions and bus timing can be given. A STD-ZaO
system will be guaranteed to work with all STD-ZaOdesigned boards. The STD-ZaO BUS fully supports the
powerful Mode 2 interrupt capability of the zao
microprocessor.

The STD BUS concept is a joint design between Mostek and
Pro-Log to satisfy the need for cost-effective OEM
Microcomputer Systems. The definition ofthe STD BUS and
the MD Series™ of OEM microcomputer modules is a result
of years of microcomputer component and module
manufacturing experience. The STD BUS uses a
motherboard interconnect system concept and is designed
to handle any MD Series™ card in any card slot. Modules for
the STD BUS range from CPU, RAM, and EPROM Modules
to Input, Output, AID, and TRIAC control modules.

The MD Series™ provides both STD-zao BUS expandable
modules, designated as MDX, and single-board stand-alone
modules, designated as MD. For those applications
requiring bus expandability, the MDX-CPU series provides
that capability; if a single-board microcomputer is sufficient,
the MD-SBCl provides the system designer with a
powerful ZaO-based microcomputer solution.

Printed circuit modules for the STD BUS are a compact 4.5 x
6.5 inches providing for system partitioning by function
(RAM, PROM,I/O). This smaller module size makes system
packaging easier while increasing MOS-LSI densities
provide high functional capability per module. Mostek has
defined the STD-ZaO BUS which is a subset of the general-

The MD Series™ of OEM microcomputer boards and the
STD-ZaO BUS offer the most cost-effective system
configuration available to the OEM system deSigner.

IV-1

BUS PIN

MNEMONIC

DESCRIPTION
:

1
2

+5V
+5V

+5 Vdc system power
+5 Vdc system power

3
4
5
6

GNO
GNO
-5V
-5V

Ground-System signal ground and OC return
Ground-System signal ground and OC return
-5 Vdc system power (see Note 1)
-5 Vdc system power

7
8
9
10
11
12
13
14

03
07
02
06
01
05
00
04

Oata Bus (Tri-state™, input/output, active high). 00-07
constitute an 8-bit bidirectional data bus. The data bus
is used for data exchange with memory and 1/0 devices.

15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

A7
A15
A6
A14
A5
A13
A4
A12
A3
All
A2
Al0
Al
A9
AO
A8

Address Bus (Tri-state™, bidirectional active high).
AO-A1 5 make up a 16-bit address bus. The address bus
provides the address for memory (up to 65K bytes) data
exchanges and for liD device data exchanges. liD
addressing uses the lower 8 address bits to allow the
user to select directly up to 256 input or 256 output
ports. AO is the least significant address bit.Ouring
refresh time, the lower 7 bits contain a valid refresh
address for dynamic memories.

31

WR*

Write (Tri-state™, active low). WR* indicates that the data bus
holds valid data to be stored in the addressed memory or I/O
device.

32

RO*

Read (Tri-state™, bidirectional, active low). RO* indicates that the
CPU wants to read data from memory or an I/O device. The
/
addressed I/O device or memory should use this signal to gate
data onto the CPU data bus.

33

10RQ*

Input/Output Request (Tri-state™, bidirectional active low). The
10RQ* signal indicates that the address bus holds a valid I/O
address for an I/O read or write operation. If STATUS 1* is also
asserted, the 10RQ* signal indicates the vector acquisition phase
of the interrupt acknowledge cycle. Interrupt Acknowledge
operations occur during Ml * time, while liD operations never
occur during Ml * time.

..

Tri-state is a trademark of National Semiconductor Corporation.
*following the signal nmernonic means a low active state.

NOTE:
1. Pin #5 may be redesignated as Battery Voltage (VSAl) in the future by the
STD-BUS Manufacturer's Group.

IV-2

MNEMONIC

DESCRIPTION

34

MEMRQ*

Memory Request (Tri-state™, bidirectional, active low). The
MEMRQ* signal indicates that the address bus holds a valid
address for a memory read or memory write operation. It is used
on memory cards and is gated with RD*, REFRESH*, or WR* to
designate memory operations.

35

10EXP

liD Expansion (high expand). A low signal enables primary I/O
operations. When high, this signal expands I/O port addressing.

36

MEMEX

Memory Expansion (high expand). A low signal enables primary
system memory. When high, this signal expands memory
addressing.

37

REFRESH*

REFRESH (Tri-state, output, active low). REFRESH* indicates that
the lower 7-bits of the address bus contain a refresh address for
dynamic memories and the MEMRQ* signal should be used to
perform a refresh cycle for all dynamic RAMs in the system.
During the refresh cycle, A7 is a logic 0 and the upper 8-bits of
the address bus contain the I register.

38

MCSYN,C*

Not generated by the MOSTEK CPU cards. MCSYNC* can be
generated by gating the following signals: RD* + WR* + INTAK*.
By connecting a jumper on the MDX-CPU1, 1A 2, 2A, this line
becomes DEBUG* (Input). DEBUG* is used in conjuction with
the DDT-80 operating system on the MDX-DEBUG card and the
MDX-SST card for implementing a hardware single step
function. When pulled low, the DEBUG* line will set an address
modification latch which will force the upper three address lines
A15, A14, and A13 to a logic 1. These address lines will remain
at a logic 1 until reset by performing any liD operation.

39

STATUS 1 (M1)*

Machine Cycle One. (Tri-state, output, active low.) M1 * indicates
that the current 'machine cycle is in the op code fetch cycle of an
instruction. Note that during the execution of two byte opcodes,
M1 * will be generated as each op code is fetched. These two
byte opcodes always begin with a CBh, DOh, EDh, or FDh. M1 *
also occurs with 10RQ* to indicate an interrupt acknowledge
cycle.

40

STATUS 0*

Not used on Mostek MD cards.

41

BUSAK*

Bus Acknowledge (Output, active low). Bus acknowledge is used
to indicate to the requesting device that the CPU address bus,
data bus, and control bus signals have been set to their high
impedance state and the external device can now control the
bus.

42

BUSRQ*

Bus Request (Input, active low). The BUSRQ* signal is used to
request the CPU address bus, data bus, and control signal bus to
go to a high impedance state so that other devices can control
those buses. When BUSRQ* is activated, the CPU will set these
buses to a high impedance state as soon as the current CPU
machine cycle is terminated and the BUSAK* signal is activated.

BUS PIN

IV-3

BUS PIN

MNEMONIC

DESCRIPTION

43

INTAK*

Interrupt Acknowledge (Tri-state, output, active low). The INTAK*
signal indicates that an interrupt acknowledge cycle is in
progress, and the interrupting device should place its response
vector on the data bus. The INTAK* signal is equivalent to an
10RQ* during an M1 *.

44

INTRQ*

Interrupt Request (Input, active low). The Interrupt Request
signal is generated by 1/0 devices. A request will be honored at
the end of the current instruction if the internal software
controlled interrupt enable flip flop (IFF) is enabled and if the
BUSRQ* signal is not active. When the CPU accepts the
interrupt, an interrupt acknowledge signallNTAK* (lORQ* during
an M1 *) is sent out at the beginning of the next instruction

45

WAITRQ*

Wait Request (Input, active low). Wait Request indicates to the
CPU that the addressed memory or 1/0 device is not ready for a
data transfer. The CPU continues to enter wait states for as long
as this signal is active. This signal allows memory or 1/0 devices
of any speed to be synchronized to the CPU. Use of this signal
postpones refresh as long as it is held active.

46

NMIRQ*

Non-Maskable Interrupt Request (Input, negative edge triggered).
The Non-Maskable Interrupt Request line has a higher priority
than the INTRQ* line and is always recognized at the end of the
current instruction, independent of the status of the interrupt
enable flip-flop. NMIRQ* automatically forces the CPU to restart
to location 0066H. The program counter is saved automatically
in the external stack so that the user can return to the program
that was interrupted. Note that continuous WAIT cycles can
prevent the current instruction from ending, and that a BUSRQ*
will override a NMIRQ*.

47

SYSRESET*

System Reset (Output, active low). The System Reset line
indicates that a reset has been generated either from an external
reset or the power on reset circuit. The system reset will occur
only once per reset request and will be approximately 2us in
duration. A system reset will also force the CPU program
counter to zero, disable interrupts, set the I register to OOH, set
the R register to OOH, and set Interrupt Mode O.

48

PBRESET*

Push Button Reset (Input, active low). The Push Button Reset
will generate a debounced system reset.

49

CLOCK*

Processor Clock (Output, active low.) Single phase system clock.

50

CNTRL*

Not used on MOSTEK MD cards.

51

PCO*

Priority Chain Output (Output, active high). This signal is used to
form a priority interrupt daisy chain when more than one
interrupt driven device is being used. A high level on this pin
indicates, that no other devices of higher priority are being
serviced by a CPU interrupt service routine.

IV-4

BUS PIN

MNEMONIC

DESCRIPTION

52

PCI

Priority Chain In (Input, active high). This signal is used to form a
priority interrupt daisy chain when more than one interrupt
driven device is being used. A high level on this pin indicates
that no other devices of higher priority are being serviced by a
CPU interrupt service routine.

53
54

AUX GND
AUXGND

Auxiliary Ground (Bused)
Auxiliary Ground (Bused)

55

+12 V

+12 Vdc system power

56

-12 V

-12 Vdc system power

NOTES:
2. Input/Output references of each signal are made with respect to MDX-CPU
module.
3. The following signals should have pull-up resistors on the processor board:

WR', RD',IORO', MEMRO', REFRESH', DEBUG'. Ml'. BUSRO'.INTAK'.
INTRO', WAITRO', NMIRO', SYSRESET', PBRESET'. and CLOCK'.

IV-5

IV-6

1983 COMPUTER PRODUCTS DATA BOOK
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!t

COMPUTER
PRODUCTS
DIVISION

UNITED
TECHNOLOGIES
MOSTEK

MATRIX-80/0EM

INTRODUCTION

MATRIX-80/0EM
Figure 1

The Mostek MATRIX-BOIOEM is a single floppy disk drive
based microcomputer system. The system includes the
following:
• MATRIX-BO/OEM enclosure with power supply
•
•
•
•
•
•
•

Fan
Six-slot card cage (MD-CC6)
Power cord
Fuse
B-inch floppy disk drive
MDX-CPU3
MDX-FLP2 module

II

System Documentation
A complete set of system documentation is supplied with
the MATRIX-BO/OEM. This includes the following
documents:
GENERAL INFORMATION
MDX-CPU3 Technical Manual. Pub # 4420261
MDX-FLP2 Technical Manual. Pub # 4420262
Schematics MDX-CPU3 #450-01065-10
MDX-FLP2 #450-00923-00
This manual gives a general introduction, unpacking
instructions, installation instructions, AC power selection,
flexible diskette handling instructions, and maintenance
guidelines. Appendix A details the preventive maintenance
procedures. Appendix B provides interfacing information to
standard terminal equipment.

programs designed to run under CPM (version 1.4 through
version 2.2). Programs written for other similar systems,
such as a Cromemco's CDOSTM, are also generally
compatible. For a more-complete understanding of the
compatibility issue, consult the M/OS-BO Operations
Manual Publications #4420064.

System Software
Hardware. Description
The MATRIX-BOlO EM does not come bundled with any
software. The decision as to which software package will be
run on the MATRIX-BOlO EM is left up to the purchaser.
However, it does come with the M/OS-BO-5 boot PROM
installed on the MDX-CPU3 board for ease of installation of
Mostek's operating system M/OS-BO.

The MATRIX-80/0EM system is based on the MDX family
of Microcomputer modules. The two modules used are
described below.

M/OS-80 is a disk operating system designed to make user
computer interaction as simple and self-explanatory as
possible. For program development, a set of sub-systems is
available to allow user programming. These include
FORTRAN, BASIC, PASCAL, and Assembler. For normal
use, many packaged applications are available from many
sources.

1. MDX-CPU3 (MK77857). This circuit board is a STD BUS
compatible, Z80 based proceSSing board that contains 64K
bytes of Random Access Memory (RAM). It also contains
the Z80-STI (Serial Timer Interrupt) device which, with
additional on-board circuitry, provides a full function serial
I/O port with programmable MODEM controls, an 8-bit
parallel printer port, and two timers. A single BYTEWYDE
(28-Pin) socket can be strapped to accept most industrystandard memory devices. See Table 1.

M/OS-80 is "upwards" -compatible with the popular 8080
operating system, CPIMTM. M/OS-80 will run virtually all

The M/OS-80-5 system boot PROM (2716 EPROM) comes
installed in the MDX-CPU3 as shipped from the factory. The

IVA-1

.5l~

~ .~
N:!:!
><

~

om
~

~

3 ADDITIONAL FLOPPY DRIVES

PRINTER

r~--

1 I

-,

I I

-----.

nl
~

o
o
o

C

til

5(")

II-]

"c

HARD-DISK
DRIVE

~:2l

»

J1

~

~

POWER SUPPLY

N
4 EXPANSION SLOTS
0

8·INCH
FLOPPY-DISK
DRIVE

C
P
U

30+
BOARDS
TO CHOOSE
FROM

3
CRT TERMINAL

"-POWER-ON
LED

RESET

0
0
0
'

0

MDX-SASI1 (HARD DISK)
MDX-PIO
MDX-SIO
MDX-422
MDX-DIOB1

STANDARD MEMORY DEVICES
Table 1

1/0 PANEL (REAR VIEW)
Figure 3

EPROMs

ROMs

2716 (2K x 8)
2732(4Kx8)
2764(8Kx8)

MK34000 (2K x 8)

Jl
PRINTER

MK37000 (8K x 8)
MK38000 (32K x 8)

J2

II

not used

II

not used

J4
not used

2716 contains the system boot routine to load tracks 0 and 1
from the floppy diskette. It also contains a rudimentary
debug monitor to allow the user to:

II
II

not used

J5

J6

J7

J8

~

~
used

used

1. (E)xecute from any location
2. (M)odify and tabulate memory locations
3. (P)ort modify and tabulate

J3
CONSOLE

J9
FLOPPY

2. MDX-FLP2 (MK77677). This module contains the
Western Digital 1797 LSI floppy disk controller and a
Mostek MK3883 Direct Memory Access (DMA) device. It
provides all required controlling/formatting/interfacing
logic between the STD-Z80 BUS and the floppy diskette
drives. It can control both single-density, single-sided and
double-density, double-~ided Shugart compatible drives. In
addition, the MDX-FLP2 can control up to four 8-inch or up
to three 5%-inch disk !lrives. The floppy disk controller is
IBM 3740 compatible.

cutouts for six(6) 25-pin "D" -type connectors, two (2) 9-pin
"D" type connectors, and a 50-pin ribbon connector. The
cutouts are labeled J 1 through J9. A view of the 1/0 panel is
shown in Figure 3. J3, the serial I/O connector, is
compatible with RS-232-C terminal devices. J2, and J4
thru J8 are not used. J9 is an expansion connector for use
with additional disk drives and is compatible with the
Mostek 60 Hz Dual Floppy Enclosure (MK78183-RMDFSS),
or the 50 Hz enclosure (MK78185-RMDFSS-50). Pinouts
for J3 are found in Figure 4. The pinouts for J9 are shown in
Figure 6.

1/0 Rear Panel
The inputloutput (1/0) panel for the MATRIX-8010EM has

J1 PINOUT (VIEWED FROM MATING SIDE)
Figure 4

STROBE

STB
GND

PRINTER DATA BIT 0

DO

2

PRINTER DATA BIT 1

D1

3

PRINTER DATA BIT 2

D2

4

PRINTER DATA BIT 3

D3

5

PRINTER DATA BIT 4

D4

6

PRINTER DATA BIT 5

D5

7

PRINTER DATA BIT 6

D6

8

PRINTER DATA BIT 7

D7

9

15
16
17
18
19
20
21
22
10
23
PRINTER BUSY

BUSY

11

PAPER EMPTY

PE

12

24

IVA-3

GND

•

J3 PINOUT (VIEWED FROM MATlNGSIDE)
Figure 5
CHASSISGND
RECEIVE DATA (input)
(RS-232) (BB) from terminal
TRANSMITIED DATA (output)
(RS-232) (BA) to terminal
REQUEST TO SEND (input)
(RS-232) (CA)
CLEAR TO SEND (output)
(RS-232) (CB)
DATA SET READY (output)
(RS-232) (CC)
GROUND

RDX

2

TDX

3

RTS

4

CTS

5

DSR

6

GND

7

RLSD

8

15
16
17
18
19
20

CARRIER DETECT (output)
(RS-232) (CF)

!TAO (TIMER A OUTPUT)

DTR DATA TERMINAL ROY (in)
(RS-232) (CD)

21
9
22
10
23

!TIMER C OUTPUT

TCO

11
24
12

J9 PINOUT (VIEWED FROM MATING SIDE)
Figure 6
2

!TG43 (TRACK GREATER THAN 43)

27

N/C
N/C
N/C

28
29
30
31
32

12 SIDED

N/C
ISELECT SIDE 1

33

N/C

34
35
36
37
38
39

49

IHEAD LOAD
IINDEX 8-INCH
IREADY
IINDEX 5-INCH
IDRIVE SELECT 0
IDRIVE SELECT 1
IDRIVE SELECT 2
IDRIVE SELECT 3
IDIRECTION CONTROL
ISTEP
!WRITE DATA
!WRITE GATE
!TRACKOO
!WRITE PROTECT
IREADDATA
IS ELECT S!DE 1

5

N/C

40
41
42

43
44
45
46
47
~

Pins 1 thru 25 are Ground
/ = Active Low

IVA-4

ELECTRICAL SPECIFICATIONS

Unpacking

WORD SIZE - 8 Bits Z80 Microprocessor

The MATRIX-80/0EM system should be removed from the
shipping container by removing the foam packing material
surrounding the enclosure carefully. The soft foam inserts
located in the diskette opening should.be removed. Open
the system by pulling the front bezel off of the system and
remove the foam packing supporting the inside enclosure.

MEMORY CAPACITY - 64K bytes
STORAGE CAPACITY - 486K Bytes flexible disk formatted
SYSTEM CLOCK - 3.6864 MHz internal oscillator

Inspection
BUS - Mostek STD-Z80 BUS

OPERATING TEMPERATURE RANGE - 15 - 49° Ambient
Celsius

Inspect the system for shipping damage. Check the printed
circuit boards located in the card cage to assure that they
are properly seated in the connectors. Check for loose
connectors or wires which may have unseated during
shipment. In case of shipping damage, place a claim against
the shipping agent who delivered the system.

INTERRUPTS - STD-Z80 BUS Prioritized Interrupts

Power Selection

MECHANICAL SPECIFICATIONS

The system has a 115/230 volt power selection switch S2
on the lower right-hand section of the rear panel to select
between 115 V ac ± 10% operation or 230 V ac ± 10%
operation. Set the switch so that the primary voltage
available shows through the hole in the rear panel. The disk
drive must be factory configured for either 50 Hz or 60 Hz
(verify correct frequency for your installation on the rear
panel label).

POWER REQUIREMENTS (MAX) - 110 V AC at 2 AMP or
220 V AC at 1 AMP.

DIMENSIONS -

HEIGHT:
WIDTH:
DEPTH:

8 inches (20.32 cm)
21.1 inches (53.59 cm)
20.7 inches (52.57 cm)

WEIGHT - 47 Ibs (21.32 kg)

INSTALLATION
The system can be operated at 100 V ac ± 10%; However,
the following wiring changes must be made.

This section provides installation instructions for the
Mostek MATRIX-80/0EM single disk microcomputer
system. Procedures described include unpacking, preliminary checks, and system power up. For more details,
refer to specific Technical Manuals (e.g. MDX-CPU3 or
MDX-FLP2.)

1. Disconnect AC power at the line cord.
2. Remove the top of the unit.
3. Use drawing in Figure 8 to help identify the wires to be
moved.

POWER SUPPLY PRIMARY WIRING 1151230 Vac

POWER SUPPLY PRIMARY WIRING 100 Vac

Figure 7

Figure 8

IVA-5

4. Unsolder and move all wires except the blue with white
stripe wire from pin 1 on the power transformer to pin 2
of that power transformer.
5. Place the power. selection switch (S2) in the 115 volt
position.
6. Replace top lid. The system is now configured for 100 volt
± 10% operation.

4.

5.
6.

Baud Rate Selection
Th MDX·CPU3 has the capability of software selectable
Baud rates. The system frequency of 3.6S64 MHz was
chosen to make the range 110 to 9600 Baud rate possible. If
the user chooses to use M/OS·SO, the driver routine will
select the Baud rate set by the terminal within the 110 to
9600 Baud rate range automatically. If a fixed Baud rate is
desired, refer to Applications Note # 10 for the fixed Baud
rate driver routine.
OPERATION
The MATRIX·SOIOEM has been fully tested and burned·in
by Mostek prior to shipment. If the unit fails to perform,
proceed according to steps outlined in the warranty policy.

7.
S.

its temperature to be changed suddenly over large
ranges. Store flexible diskette in an environment that is
between 50 degrees F and 125 degrees F with a relative
humidity between 0 and SO%.
Avoid contamination and warpage by returning the
diskette to its envelope when not in use. Store envelope
in its box. (verticle is better than horizontal)
Avoid placing heavy objects on the diskette.
Do not write on the diskette except on label with a
felt·tipped pen.
Do not attempt to clean the diskette:
The flexible diskette should be in the same temperature
and humidity enviroment as the disk drive for a minimum
of five minutes.

Diskette Unloading
Diskettes are removed from the disk unit by depressing the
latch button. The disk unit door will open and the diskette
will be pushed out of the unit.
MAINTENANCE
This section deals with the maintenance of the various sub
units of the MATRIX·SOIOEM system.

Floppy Diskette
Power Supply
The following are recommendations for extending the life of
diskettes used in the MATRIX·SOIOEM system. Every
attempt has been made to design the system for maximum
diskette life. However, poor handling practices may cause
premature failure of diskette media andlor loss of valuable
data.
CAUTION: Do not power the system up or down with a
diskette inserted in a disk drive unit. Doing so may destroy
the integrity of the data on the diskette. Spurious write
pulses may occur which could destroy data on the disk.
Also, "RESET" should not be pressed during disk accesses.

The power supply assembly requires no periodic
maintenance. If it is noticed that DC voltages have drifted
from the nominal values, adjustment facilities are available
on each regulator card. However, this determination should
be made only with a high impedance voltmeter at normal
operating temperature.
Fan
The temperature within the MATRIX·SOIOEM is very
important to achieve error·free operation. The diskette
DISKETTE LOADING

Diskette Loading

Figure 9

The diskette is a flexible disk enclosed in a plastic jacket. The
jacket is lined with a wiping material to clean the disk of
foreign material. Figure 9 shows the proper method of
loading a diskette into a disk drive. The diskette should be
loaded with power on. To load the diskette, depress the
latch, insert the diskette with the label facing upward: The
diskette is loaded when a "click" is heard. Move the latch
handle down slowly to 19Ck the diskette on the drive spindle.
Diskette Handling
The following are important handling suggestions:
1. Avoid touching exposed l)Ireas of magnetic medium.
2; Avoid exposure 'of diskette to ma'gnetic fields such as
motors, fluorescent lamps, transformers, telephones,
and.so on.
.
3. Avoid exposure of diskette to direct sunlight. Do not allow
IVA-6

material has an operating range of 10 degrees C (50
degrees F) to 49 degrees C (120 degrees F) for prolonged life
and error free operation. It is. therefore. important to keep
the fans located on the side of each subsystem free from
obstructions and in good working order. The power supplies
have a lBO degree F thermal breaker and should the
temperature inside the unit get too high. the breaker will
shut down the system. The fan screen should be cleaned
monthly.

CAUTION: Do not operate the MATRIX-BO/OEM ifthefan
is not functioning correctly.

Disk Drive Maintenance
The disk drive requires preventive maintenance every 12
months under normal usage. See Appendix B for complete
details. Cleanliness is very important to successful
operation of the MATRIX-BO/OEM system. The fan should
be free from dirt. lint. and so on. Do not lubricate the disk
drive unit; oil will allow dust to accumulate. The read/write
heads on the disk drive unit should be cleaned only when
signs of oxide build-up are present. Oxide build-up will
cause premature failure of diskette material. Occasional
inspection of read/write heads and diskette will monitor
this condition.

Disk Drive Removal
Preventive maintenance or inspection of the drive unit may
require its removal from the enclosure. The following
procedure describes how to remove the drive.
1. Remove all power from the MATRIX-BO/OEM system.
CAUTION: High AC voltages are present within the
system even with the AC switch OFF. Remove the line
cord from the wall outlet.
2. Pop off the lid of the system by pulling upward.
3. Remove Pl (signal). P4 (AC). and P5 (DC) connectors
from back of the drive. The P4 and P5 connectors are
removed by depressing the tabs extending from the side
of the connectors.
4. Carefully remove the bezel from around the face of the
unit by pulling forward.
5. Remove the front and rear screws (3) holding the bracket
below the drive to the baseplate.
6. Remove the disk drive unit out the front of the enclosure.
7. Lay the drive unit upside down on its top and remove the
four screws that hold the mounting bracket to the drive
frame.
B. To replace the disk drive unit. use the reverse procedure.
TROUBLE-SHOOTING
This section contains a trouble-shooting guide for some
specific problems which might occur with the MATRIXBO/OEM system.

SYMPTOMS

THINGS TO CHECK

1.

POWER ON indicator does not illuminate.

1. Is there Power to line cord?
2. Is Fuse Fl good?
3. Is LED defective?

2.

POWER ON indicator illuminates. fan runs. drive
spindle does not turn.

1 . Drive belt broken or off pulley
2. ACwiring

3.

POWER ON indicator OK fan runs. system returns
garbage characters or no characters to the CRT.

1.
2.

Is the Baud rate correct?
Are the Cable connections good?

4.

POWER ON indicator OK fan runs. upon carriage
return from the terminal. the floppy diskette seems
to read only the first two tracks and quits.

1.

Ensure jumpers on FLP2 are correctly installed. J12
should be pins 2-3.
Ensure pins l-B. and 20 are connected from the
terminal. (MODEM lines must be connected.)

2.

IVA-7

APPENDIX A
DISK DRIVE PREVENTIVE MAINTENANCE

INTRODUCTION

Preventive Maintenance Procedures

The prime objective of any Preventive Maintenance (PM)
activity is to provide maximum machine availability to the
user. Every preventive maintenance operation should assist
in realizing this objective. Unless a preventive maintenance
operation cuts machine downtime, it is unecessary.

Details of preventive maintenance operations are listed in
Figure A 1. During the normal preventive maintenance,
perform only those operations listed on the chart for that
preventive maintenance period. Observe all safety
procedures.

Visual inspection is the first step in every scheduled
maintenance operation. Always look for corrosion, dirt,
wear, binds, and loose connections. Noticing these items
during PM may save downtime later.
Remember, do not do more than recommended preventive
maintenance on equipment that is operating satisfactorily.

Cleanliness
Cleanliness cannot be over-emphasized in maintaining the
disk drive unit. Do not lubricate the disk drive; oil will allow
dust and dirt to accumulate. The read/write head should be
cleaned only when signs of oxide build-up are present.

MAINTENANCE PROCEDURES
FigureA-1

FREQ
UNIT

MONTHS

OBSERVE

ACTION

Read/Write Head

12

Oxide Build-up

Clean ReadlWrite Head ONLY IF NECESSARY

RIW Head Load Button

12

Stepper Motor and
Lead Screw

Inspect for nicks
burrs.

Clean off all oil, dust and dirt.

12

Belt

12

Frayed or weakened areas

Replace

Base

12

Inspect for loose screws,
screws, connectors, and
switches.

Clean base

ReadlWrite Head

12

Check for proper
Alignment.

Replace

IVA-8

APPENDIX B
PERIPHERAL INTERFACING INFORMATION
INTRODUCTION

Serial ASCII Terminal

This appendix provides peripheral interlacing information.
The content of this section will vary according to the
customized configuration.

The software driver port assignments
vary with the
operating software to be installed by the user. However, the
cable signal, and pin out will usually remain similar. The
information to build a cable is shown in Table B-1. This
cable is available from Mostek - order part number
MK78152.

will

CABLE INFORMATION
Table 8-1

RS-232-C/v.24
MDX-CPU3
SIGNAL

I/O
CONNECTOR

ASCII
TERMINAL

SIGNAL
NAME

CHASIS GND
RECEIVE DATA
TRANSMIT DATA
REQUEST TO SEND
CLEAR TO SEND
DATA SET READY
GROUND
CARRIER DETECT
DATA TERMINAL READY

J3-1
J3-2
J3-3
J3-4
J3-5
J3-6
J3-7
J3-8
J3-20

EIA-1
EIA-2
EIA-3
EIA-4
EIA-5
EIA-6
EIA-7
EIA-8
EIA-20

AA
BA
BB

CA

CB
CC

A13
CF
CD

The parts required to build the cable are listed below and are
not available from Mostek.

F10IJPV Disk Drive

25 pin "0" Connector
25 conductor cable

Table B-2 shows the pinout of various connectors to ease
the interlace of the floppy disk unit.

ANSLEY #609-25P (2 required)
#ANLSEY #171-26 (6 FT long)

IVA-9

CONNECTORS PINOUT
Table 8-2

MDX-FLP2
J3 CONNECTOR
PIN NO.

I/O PANEL

J9C~~~'if.TOR

2
4
·6'
8
10
12
14*
16
18
20
22
24
26
28
30
32
34
36
38

40
42

44
46
48*
50

FLOPPY DISK
SIGNAtNAME

26
27
28
29

ITG43

30

12 SIDED

N/C
N/C
N/C
N/C

31
32
33
34
35
36
37
38
39

SELECT SIDE 1

N/C
IHEAD LOAD
IINDEX 8-INCH
IREADY
IINDex 5"INCH
IDRIVE SELECT 0
IDRIVE SELECT 1
IDRIVE SELECT 2
IDRIVESELECT 3
IDIRECTION CONTROL
ISTEP
/WRITE DATA
/WRITE GATE
ITRACKOO
/WRITE PROTECT
. /READ DATA
ISELECT SIDE 1

40
41
42
43

44
45
46
47
48
49
50

N/C

* Pin 14 and 48 are tied together on. the MDX-FLP2 .board.
On the MDX-FLP2 board, all odd pins are GND.
On the 1/0 Panel. pins 1 thru 25 are GND.
Logic Levels are defined at the M DX-FLP2 edge connector.

IVA-10

!t

UNITED

COMPUTER
PRODUCTS
DIVISION

TECHNOLOGIES
MOSTEK

MATRIX 010,100
MK78220, MK78221
FEATURES

MATRIX 100, TABLE TOP VERSION
Figure 1

o 8-inch single-sided, double-density floppy disk drive
o 10-slot card cage, STD BUS compatible
o Multi-disk expansion capabilities

•

o Fully integrated power supply
o 50 or 60 Hz operation
o 1151230 Vac operation (factory wired)
o Standard 19" rack-mountable chassis
o Optional table-top version
o Front panel power-on indicator
DESCRIPTION
The MATRIX unit is a user-configurable microcomputer
system. It provides the user flexibility in packaging and disk
storage requirements by offering several configuration
options.
The MATRIX unit has a 10-slot card cage, utilizing the STD
BUS, power supply, and fan. The power supply provides all
the necessary voltages for both the card cage and floppy
disk drive. The unit has a structural foam front bezel with
quick release ball studs so it can be removed easily. The disk
drive may be removed from the front for ease of
maintenance. The rear panel has a hinged door for easy
access to the 1O-slot card cage and has an adjustable strain
relief mechanism for cabling to peripherals.

PACKAGING CONFIGURATION
POWER SUPPLY
The power supply provides all the necessary voltages for
both the card cage and floppy disk drive. The power supply
has the following voltages available:
+5 volts dc at 15 amps maximum
+12 volts dc at 0.5 amp maximum
-12 volts dc at 0.25 amp maximum
+24 volts dc at 3.4 amps maximum
The floppy disk drive (provided on the MATR IX 100) uses +5
volts at·1.0 amp maximum, and +24 volts at 1.7 amps,
leaving the following voltages available to the card cage:

The MATRIX 010 (MK78220)"has no disk drive, which
allows the unitto be used as a non-disk based system, or the
user can add a floppy-disk drive.

+5 volts at 14 amps
+12 volts at 0.5 amp
-12 volts at 0.25 amp

The MATRIX 100 (MK78221) has an 8-inch singlecsided,
double-density floppy-disk drive.

**CAUTION**

The MATRIX units are available in rack mount or table top
versions, with standard 115 or 230 volt operation. The table
top version has structural foam side skins and lid.

A minimum load of 1.5 amps is required on the
primary +5 volt supply in order to ensure proper
regulation on the other outputs.

IVA-11

CARD CAGE

10-SLOT CARD CAGE

The 1O-slot card cage is a vertical board mount cage and is
fabricated from steel. The card cage is mounted in the rear
left-hand side ofthe MATRIX unit (facing the rear). The back
panel contains a hinged door for access to the card cage.
Figure 2 is an illustration with dimensions of the card cage.

Figure 2

Power connections to the card cage are provifiled ph the
motherboard by a 2-pin and 4-pin AMP Universal MATE-NLOK connector. There is also a 3-pin AMP Universal MATEN-LOK connector for connecting a remote power lamp and
reset button. The pin assignments for these connectors are
shown in Table 1, with holes denoted from the comPonent
side left to right.
POWER CONNECTOR PIN ASSIGNMENTS
Table 1

CONNECTOR PINS
(LEFT TO RIGHT)
DESIGNATOR

FLOPPY DISK DRIVE
The floppy-disk drive provided on the MATRIX 100 is a
Shugart SA8oo-2 single-sided, double-density unit. Acable
is provided with a 50-pin card-edge connector that connects
to the internal disk drive, and a 50-pin socket connector for
connecting to a controller board (board not provided). The
floppy-disk drive is mounted in the front right-hand side of
the MATRIX 100 unit.

STb.BUS
PIN
DESIGNATOR

4-Pin
1
2
3
4

+5V
GND
-12 V
+12 V

1,2
3,4
56
55

1
2

AUXGND
-5V

53,54
5,6

1
2
3

GND
+12 V
/PBRESET

3,4
55
48

IN INCHES

The MATRIX unit has two mating connectors from the
power supply that provide AC and DC power to the floppy
disk drive. The DC power mating connector is a 6-pin AMP
PIN 1-480270-0 utilizing AMP pins PIN 60619-1. See
Table 2 for the 6-pin power designators.

2-Pin

The AC mating connector is a 3-pin AMP PIN 1-480303-0
or 1-480304-0both utilizing pins PIN 50519-1. See Table 3
for the 3-pin power designators.

3-Pin

6-PIN DC POWER DESIGNATORS
Table 2
PIN

1

I/O Expand/Memory Expansion
The 10-slot card cage motherboard has two stake pins
(lOEXP and MEMEX) that are connected to bus pins 35
(lOEXP) and 36 (MEMEX). If the 10EXP (110 Expand) pin is
not used it should be strapped to the logic ground stake pin
opposite pin 10EXP. If the i\iiEiiii"EX (memory expansion) is
not used it should be strapped to the logic ground stake pin
opposite pin iii1EK.iiEX:
Interrupt Priority
The interrupt priority for the 1O-slot card cage is from right
to left as viewed from the front of the card cage, with the
highest priority at the right-most side.

2
3
4

5
6

DC VOLTAGE DESIGNATOR
+24 Vdc
+24 V Return*
-12 V Return
-12 Vdc
+5Vdc
+5 V Return

*The +24 Vdc power requires a separate ground return line.
Ali DC grounds must be connected together near the power
supply. One line from this common ground DC connection
must go to one common frame ground connection.
3-PIN AC POWER DESIGNATORS
PIN
1

2
3
IVA-12

AC VOLTAGE DESIGNATOR
115 Vae
Safety GND
115 Vae Return

CONTROLS AND INDICATORS

DESIGN OPTIONS

The operator controls and indicators are located on the front
panel of the MATRIX unit. This panel contains the POWER
ON/OFF and system RESET switches.

The MATRIX unit is designed for use with Mostek MD
Series microcomputer boards. A complete line of data
processing, memory, input/output boards, and accessories
are available from Mostek (see the current Mostek catalog
for ordering information).

The POWER switch, when pressed, applies AC power to the
MATRIX unit. This switch is illuminated when the power is
on. The RESET switch asserts the PBRESET signal on the
STD BUS. Figure 3 illustrates the front panel of the MATRIX
unit.
FRONT PANEL OF THE MATRIX UNIT

Mostek also offers a complete line of compatible software
products for use with the configured MATRIX unit. Refer to
the Mostek Software Catalog for available software.
All Mostek software is available through a licensing
agreement to those users who wish to sell it as a part of
their own system. All Mostek software is copyrighted and
unauthorized copying is prohibited.

Figure 3

'CP1M is a product of Digital Research Corporation

INSTALLATION
UNPACKING AND INSPECTION
MATRIX

The MATRIX unit should be removed from the shipping
container by carefully removing the foam packing material
surrounding the enclosure.
REAR PANEL
The rear panel of the MATRIX unit has a hinged door for
easy access to the 10-slot card cage. The hinged door also
has an adjustable strain relief mechanism for the cables
which connect to peripherals. Figure 4 is an illustration of
the MATRIX rear panel.

Inspect the MATRIX unit for shipping damage. Remove the
top and check for loose connectors or wires which may have
been disconnected during shipment. In case of shipping
damage, place a claim against the shipping agent who
delivered the unit.
POWER SELECTION

The left side of the rear panel contains a fuseholder (with
fuse) and an AC power cable connector. The MATRIX unit is
shipped with a power cord.
REAR PANEL OF THE MATRIX UNIT
Figure 4

The MATRIX unit is shipped factory wired for either 115 V or
230 V operation.
The 50/60 Hz configuration for the MATRIX is a function of
the disk drive selected.
MAINTENANCE
POWER SUPPLY
The power supply assembly requires no periodic
maintenance. If the DC voltages drift from nominal values,
adjustments can be made. However, this determination
should be made only with a high impedance voltmeter at
normal operating ambient temperature under load.
FAN
The temperature within the MATRIX unit is very important
to achieve error-free operation. The diskette material used
on the floppy-disk drive has an operating temperature range
of 10°C (50°F) to 49°C (120°F) for prolonged life and error
free operation. Therefore, it is important to keep the fan
located on the side of the unit free from obstructions and in
good working order. The fan screen should be cleaned
monthly.

IVA-13

**NOTE**

INPUT Power;

Do not operate the MATRIX if the fan is not
functioning properly.

115/230 Vac

± 10%, 50 or 60 Hz

DC POWER SUPPLIED:
FLOPPY-DISK DRIVE
Cleanliness cannot be overemphasized in maintaining the
disk drive (MATRIX 100). Do not lubricate the disk drive; oil
will allow dust and dirt to accumulate. The ReadlWrite
head should be cleaned only when signs of oxide build-up
are present. Table 3 provides preventive maintenance procedures and schedule.
Figure 5 shows open space inside the MATRIX 100. When
using this space, care should be taken to avoid restricting
the air flow and changing the temperature characteristics of
the unit.

+5 Vdc at 15 A max.
+12 Vdc at 0.5 A max.

-12 Vdc at 0.25 A max.
+24 Vdc at 3.4 A max.

FUSING
3 Amp, 3 AG for 100/110/115 volts
1.5 Amp, 3AG for 230 volts
OPERATING TEMPERATURE RANGE
Matrix 010
O°C to 60°C

SPECIFICATIONS

Matrix 100

BUS

4.4°C to 35°C (disk drive limitation) or disk media
specification, whichever is more stringent.

STD-Z80 BUS
POWER REQUIREMENTS (MAX)
INSIDE OF MATRIX UNIT
Figure 5
;==

;==

iii.

r--

r-

~

"---'

WL-.J

'-'

Er-

L...-

POWER
SUPPLY
CARD CAGE 10

J~

n~~

r

r10"

DISK
DRIVE

~
A

~

t--

i
1.5"

i=

i

,==",

~

3

I--

EI---

I~ =1

III:Jl;l

[:8:]

.1

7"

IVA-14

I

SPECIFICATIONS (Continued)

DISK DRIVE

INTERRUPTS

Shugart SA800-2 or equivalent (MATRIX 100)

STD-Z80 BUS prioritized interrupts

INDICATORS AND CONTROLS

DIMENSIONS

FRONT PANEL INDICATORS

Rack Mount:

Power-on

Height: 7%"
Width: 19"
Depth: 22W'

FRONT PANEL CONTROL
Power-on switch
Reset switch

Table Top:
REAR PANEL CONTROLS
Height: 814"
Width: 21"
Depth: 22W'

AC Fuse Holder (with appropriate fuse)
AC Line Receptable/Filter

WEIGHT
45 pounds (21.32 kg.)
MOSTEK STD-Z80 BUS PINOUT

COMPONENT SIDE
PIN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55

CIRCUIT SIDE

MNEMONIC
+5V
GND
-5V
D3
D2
D1
DO
A7
A6
A5
A4
A3
A2
A1
AO

IWR
IIORO
IIOEXP
IREFRESH
ISTATUS 1
IBUSAK
IINTAK
IWAITRO
ISYSRESET
ICLOCK

IPCO
AUXGND
+12 V
IVA-15

PIN

MNEMONIC

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56

+5V
GND
-5V
D7
D6
D5
D4
A15
A14
A13
A12
A11
A10
A9
A8

IRD
IMEMRO
IMEMEX
IMCSYNC
ISTATUSO
IBUSRO
IINTRO
INMIRO
IPBRESET
ICNTRL
PCI
AUXGND
-12V

PREVENTIVE MAINTENANCE PROCEDURES·
Table 3

UNIT
Read/Write
head

FREn.
MONTHS

OBSERVE

12

Oxide build-up

Clean Read/Write
Head ONLY IF
NECESSARY

Check for
proper alignment

Align

ACTION

Read/Write
Head Load Button

12

Excessive
wear

Replace

Stepper Motor
a nd Lead Screw

12

Inspect for
nicks and burrs

Clean off oil.
dust, and dirt

Belt

12

Frayed or
weakened areas

Replace

Base

12

Inspect for
loose screws, connectors,
and switches

Tighten screws,
connectors, and
switches

ORDERING INFORMATION

DESIGNATOR

DESCRIPTION

PART NO.

MATRIX 010

Rack mountable, user-configurable unit with 1O-slot card
cage, fan, power supply. 115 V, 60 Hz operation. (Cards not
included.) .

MK78220-00-00

Same as above with 230 V, 50 Hz operation

MK78220-01-00

Table-top version, same as above with 115 V, 60 Hz
operation.

MK78220-04-00

Table-top version, same as above with 230 V, 50 Hz
operation.

MK78220~05-00

Rack mountable, MATRIX 010 with 8-inch single-sided,
double-density disk drive with 115 V, 60 Hz operation.

MK78221-10-OO

Same as above with 230 V, 50 Hz operation.

MK78221 -11 -00

Table-top version, same as above with 115 V, 60 Hz
operation.

MK78221 ~14-00

Table-top version, same as above with 230 V, 50 Hz
operation.

MK78221-15-00

Slide mounting kit

MK78193

MATRIX 100

SLD-KIT

WARNING: This equipment generates, uses, and can radiate radio frequency energy and if not installed and used in
accordance with the instructions manual, may cause interference to radio communications. As temporarily permitted by
regulation it has not been tested for compliance with the limits for Class A computing devices pursuant to Subpart J of Part
15 of FCC Rules, which are designed to provide reasonable protection against such interference. Operation of this
equipment in a residential area is likely to cause interference in which case the user at his measures may be required to
correct the interference.

IVA-17

ORDERING INFORMATION
D.esignator

Description

Part Number

Matrix 8O/OEM-RMUS

Single floppy disk drive based Microcomputer System
(115 Vac 5 Hz)

MK78231-10

Matrix 8010EM-RME

Rack mount single floppy disk drive based Microcomputer
System (230 Vac 50 Hz)

MK78231-11

Matrix 8010EM-TIUS

Table top single floppy disk drive based Microcomputer System
(115 Vac 60 Hz)

MK78231-14

Matrix 8010EM-TIE

Rack mount single floppy disk drive based Microcomputer
System (115 Vac 50 Hz)

MK78231-15

Matrix 8010EM
Technical Manual

Matrix 8010EM Technical Manual only

4420345

CPU3 Technical Manual

CPU3 Technical Manual only

4420261

FLP2 Technical Manual

FLP2 Technical Manual only

4420262

IVA-1S

I!I

UNITED

COMPUTER
PRODUCTS
.. DIVISION

TECHNOLOGIES
MOSTEK
.

MATRIX 200
USER-EXPANDABLE COMPUTER
MK78222
FEATURES

MATRIX 200, RACK-MOUNT VERSION
Figure 1

o Z80-based, using STO Bus
o 64 KB memory
o Two 8-inch, double-sided, double-density floppy-disk
drives

II

o 3.2 MB storage capacity (unformatted)
o Includes:
• Two cards (MOX-CPU3 singlecboard computer and
MOX-FLP2 floppy disk controller), leaving 8 of 10 slots
available for user expansion
• Centronics-compatible parallel printer interface
• RS-232C-compatible seriarinterface
o Power supply: 115 VAC, 60 Hz or 230 VAC, 50 Hz
o Standard 19" rack-mount chassis or table-top version
o M/OS-80, Mostek's CPIMTM-compatible operating system
is available, providing access to large application
software base
o Also available: Microsoft's Z80Assembler, BASIC and
FORTRAN

DESCRIPTION
MATRIX 200 is a Z80 based user-expandable microcomputer system targeted for, but not limited to, industrial
control and instrumentation applications. It is designed
around the industry-proven STO BUS. Both rack-mount and
table-top versions are available.
The system contains 64 KBytes of memory. It has two
thin-line 8-inch double-sided double-density floppy-disk
drives, providing 3.2 MBytes of storage capacity
(unformatted). A Centronics parallel printer interface and an
RS-232C compatible serial interface are standard with the
system.
A card cage with ten slots, only two of which are used,
provides for user expansion options. The power supply will
operate on 115 VAC, 60 Hzor 230VAC, 50 Hz. MATRIX 200
complies with FCC requirements.
TM

The system runs M/OS-80, Mostek's CP/M compatible
operating system, thus providing access to a large
application software base. Also available through Mostek
are Microsoft's Z80 Assembler, BASIC, and FORTRAN.
The boot firmware for M/OS-80 is provided as part of the
system. This allows for "phantom" operation, which means
that once the system boots, the boot PROM is removed from
the address space yielding full 64 KByte address space for
program execution.
Another feature included in firmware is a minimum
debugger. This provides the capability for memory access,
port access, and execution at a given address.

CONTROLS AND INDICATORS
The operator controls and indicators are located on the front
panel of the MATRIX 200 unit. This panel contains the
POWER and system RESET switches.
The POWER switch, when pressed, applies AC power to the
unit. The switch is illuminated when the power is on. The
RESET switch resets the SYSRESET signal on the STO BUS.

CP/M is a trademark of Digital Research Corporation.

IVA-19

REAR PANE;t

POWER

The rear panel of th~ MATRIX 200 unit has a hinged door for

Input:

115/230 VAC50/60Hz @355 VA

Output:

[email protected]
+12 VDC @ 1.5 A
-12 VDC @ 1.5 A

easy access to the ten-slot card cage. The hinged door also
has an adjustable strain relief mechanism for the cables
which connect to peripherals.
The leftside of the rear panel contains a fuse holder and an
AC power cable connector. (A power cord is shipped with
the MATRIX 200.)

:.'

,"

"

Available for expansion options:
[email protected]
+12 VDC @ 1.375 A
-12 VDC @ 1.475 A

DESIGN OPTIONS .
PHYSICAL DIMENSIONS
The MATRIX 200 unit is designed for use with Mostek MD
Series microcomputer boards. A complete line of STD BUS
compatible data processing, memory, and input/output
boards is available from Mostek.
The operating system .offered to MATRIX 200 users is
M/OSc80 (V5 or higher). This CP/M compatible operating
system provil;fes access to mE/ny.available' application
packages.' Microspft's Z80 Assembler,BASIC interpreter,
BASCOM (Basic Compiler), and FORTRAN are also
avaHablfHhrough Mostek. Ci.istom drivers can be integrated
into M/OS-80'uslng Mostek's system generation software,
MOSGEN:
".
"."

.

Rack Mount:
Height:
Width:
Depth:
Table-Top:
Height:
Width:
Depth:

7%"

19"
.22112"
8%"
21"

22112"

OPERATING ENVIRONMENT
Temperature: 10°C - 35°C

ORDERING INFORMATION~ ,

DESIGNATOR

DESCRIPTION

PART NO,

MATRIX 200

Rack-mount version; 115 VAC, 60 Hz operation

MK78222-0-20

Rack-mount version; 230 VAC, 50 Hz operation

MK78222-0-21

. Table-top version; 115 VAC, 60 Hz operation

MK78222-0-24

Table-topversion; 230 VAC, 50 Hz operation

MK78222-0-25

NOTE:
1. All software items must be ordered separately.
2. Other system configurations are available.

.;:

1983 COMPUTER PRODUCTS DATA BOOK

.N"

"

'-''''',-',-, '_•. ""''''''''''''''''','''''' ,."' ....... ,,< ..... ,......... ~-,-"'......,..,""""""--..... ""' .... ,,-""............. "" ........."",,,,,,,.

t.:!·,:

;~;

~

-', ,'i {.,'::', ~ ..... ~::..i'.

MDX Series Data Processing
... '~ ,~

,

'

. . . .'.

<:~.,
)..,

Ij

UNITED

COMPUTER
PRODUCTS
DIVISION

TECHNOLOGIES
MOSTEK

MDX-CPU1 AND MDX-CPU1 A

FEATURES

MDX-CPU1 AND MDX-CPU1A

o STD-l80 BUS-compatible
o 4K x 8 EPROM (two 2716's, customer-provided)
o 256 x 8 Static RAM (compatible with DDT -80 debugger)
o Flexible Memory decoding for EPROM and RAM
o Four counter/timer channels

III

o Restart to OOOOH or EOOOOH (strapping option)
o Debug-compatible for single step in DDT-80
o 2.5 MHz version (-0) or 4 MHz version (-4)
o +5 Vonly
o Fully-buffered signals for system expansibility
GENERAL DESCRIPTION
The Mostek MDX-CPU1 is the heart of an MD Series l80
system. Based on the powerful l80 microprocessor, the
MDX-CPU1 can be used with great versatility in an OEM
microcomputer system application. This is done simply by
inserting EPROM memories into the sockets provided on
the board and configuring them virtually anywhere within
the lBO memory.
256 bytes of scratchpad RAM are provided on the board and
4K of EPROM can be user provided (2 2716s).ln addition, an
MK3882 Counter Timer Circuit is included on the MDXCPU1 to provide counting and timing functions for the l80.

There is also a version of this board, CPU1A, which is
targeted for the industrial control area. The CPU1A allows
system reset to be generated off the board, i.e., from the
MDX-PFD. CPU1 does not incorporate this feature. Due to
this difference, the user must be aware of the "one-way"
compatiblity of these two products. A CPU1A will work in
any application in which a CPU1 has been used but the
opposite is not the case.

The MDX-CPU1 can be used in conjunction with the MDXDEBUG and MDX-DRAM modules to utilize DDT-80 and
ASMB-80 in system development.
The MDX-CPU1 is also available in a 4MHz version (MDXCPU1-4). In this version, one wait state is inserted
automatically each time on board memory is accessed by a
read or write cycle. This is necessary to make the access
times of the 2716 PROMs and the 3539 scratchpad RAM
compatible with the MK3880-4 4 MHz l80-CPU.

IVB-1

FUNCTIONAL DESCRIPTION
The MDX-CPU1 is designed around the powerful l80 CPU
(3880) chip. A Block Diagram is shown in Figure 2.
CPU

l80 (MK3880) generates the address and control signals,
communicates with memory I/O and peripherals, fetches
and executes instructions, and provides most of the timing
signals for proper operation of the system.

BLOCK
DIAGRAM· '
..
Figure 2
','

~

CONTROL

OATA

12

USER
PROM

2
2716's

tl

-5V"""GND

v
STO BUS INTERFACE

COUNTER/TIMER CIRCUIT (CTC)

RESET/RESTART

The counter/timer circuit provides a four channel
counter/timer function under software control.

The MDX-CPU1 can be strapped so that reset execution
begins at either OOOOH or EOOOH. This logic is required for
use of standard Mostek hardware and software products
including DDl-80, FLP-80DOS/, MDX-SST, and MDXDEBUG.

EPROM
Two 24-pin sockets are provided for use with 2716
EPROMs(+5Vonly)foran EPROM memory capacity of 4Kx
8. This 4K x 8 of EPROM can be strapped on any 2K
bOundary within any 16K block.
RAM
A 256 x 8 static RAM is provided for general purpose
storage and stack pointer operations. The 256 x 8 RAM is
located at FFOO to FFFF and can be enabled or disabled via a
user installed strap.
CLOCK GENERATOR
TheMDX-CPU1 comes with a crystal-controlled clock
generator. This clock drives all the necessary components
on the board, and is buffered to drive off the board to the
other system peripherals. The crystal frequency for the
standard MDX-CPU1 card is 5.0 MHz or 8.0 MHz
respectively and is divided by two to yield a 2.5 MHz, or to
4.0 MHz or 8.0 MHz respectively.

BUS LINES, (DATA, ADDRESS, CONTROL)
All lines going onto or off of the board are TTL buffered
and/or terminated. The data bus lines are bidirectional so
that data can go in two directions. The direction of the data
bus buffer is controlled by the CPU, so that the data bus
buffer will always be enabled out when the CPU is
accessing on board memory or the CTC. The data bus buffer
will be enabled pointing onto the CPU card when an offboard memory, 110, or interrupt vector is addressed. The
data bus buffer will go to a high impedance whenever a
bus-acknowledge signal is issued from the CPU. The
address and control lines are unidirectional buffers and will
go to a high impedance level whenever a bus acknowledge
signal is issued by the CPU.
WAIT STATE GENERATOR
This function, if selected, causes on board memory read and
write cycles or I/O cycles to be lengthened by one clock

IVB-2

period in order to allow sufficient access time when slow
memory of I/O devices is utilized.

MEMORY INTERFACE
The MOX-CPU can be populated with up to 4K x S of
EPROM (two 27165). It comes with a 256 x S static RAM
that is decoded at FFOOH to FFFFH.

EPROM ADDRESS SELECTION
MDX-CPU1 AND MDX-CPU1A
Table 1

CPU1

CPU1A

CPU1

CPU1A

CPU1

CPU1A

U5 Jumpers
EPROMU6

J3Jumpers
EPROM U6

U5Jumpers
EPROM U7

J3Jumpers
EPROM U7

U10
Jumpers

J4
Jumpers

0-7FF
SOO-FFF
1000-17FF
1SOO-1FFF

Pins
5 to 9
"to 10
"to 11
"to 12

Pins
9 to 16
"to 14
"to 12
"to 10

Pins
4to 9
"to 10
"to 11
"to 12

Pins
7 to 16
"to 14
"to 12
"to 10

Pins
2 to 12
and
5 to 9

Pins
3 t06
and
9 to 12

2000-27FF
2S00-2FFF
3000-37FF
3S00-3FFF

"to
"to
"to
"to

13
14
15
16

"
"
"
"

to
to
to
to

S
6
4
2

"to
"to
"to
"to

13
14
15
16

"
"
"
"

to
to
to
to

S
6
4
2

4000-41FF
4S00-4FFF
5000-57FF
5S00-5FFF

" to
"to
"to
"to

9
10
11
12

"to
"to
"to
"to

16
14
12
10

" to
"to
"to
"to

9
10
11
12

"to
"to
"to
"to

16
14
12
10

6000-67FF
6S00-6FFF
7000-77FF
7S00-7FFF

"to
"to
"to
"to

13
14
15
16

"
"
"
"

to
to
to
to

S
6
4
2

s000-S7FF
SSOO-SFFF
9000-97FF
9S00-9FFF

" to
"to
"to
"to

9
10
11
12

"to
"to
"to
"to

AOOO-A7FF
ASOO-AFFF
BOOO-B7FF
BSOO-BFFF

"to
"to
"to
"to

13
14
15
16

"
"
"
"

COOO-C7FF
CSOO-CFFF
0OOO-07FF
OSOO-OFFF

" to
"to
"to
"to

EOOO-E7FF
ESOO-EFFF
FOOO-F7FF
FSOO-FFFF

"to
"to
"to
"to

Decoded
Address

"to 13
"to 14
"to 15
"to 16

"
"
"
"

to
to
to
to

S
6
4
2

16
14
12
10

" to
"to
" to
"to

9
10
11
12

"to
"to
"to
"to

16
14
12
10

to
to
to
to

S
6
4
2

"to
"to
"to
"to

13
14
15
16

"
"
"
"

to
to
to
to

S
6
4
2

9
10
11
12

"to
"to
"to
"to

16
14
12

10

" to
"to
"to
"to

9
10
i1
12

"to
"to
"to
"to

16
14
12
10

13
14
15
16

"
"
"
"

S
6
4
2

"to
"to
"to
"to

13
14
15
16

"
"
"
"

to
to
to
to

There are no EPROMs shipped with these assemblies.
IVB-3

to
to
to
to

S
6
4
2

II
!

Pins
9to 10
and
2 to 12

Pins
12 to 10
and
3to6

Pins
5 to 9
and
2 to 3

Pins
9 to 12
and
3t05

Pins
9 to 10
and
2 t03

Pins
12 to 10
and
3t05

MEMORY DECODING JUMPERS

WAIT STATE GENERATOR

Decoding for each of the EPROMs is shown in Table 1. The
256 x 8 static RAM may be disabled by disconnecting U5 Pin
2 from U5 Pin 3.

The wait state circuitry was added to allow 4 MHz operation
with standard memory and standard 1/0 devices. When the
wait state circuit is enabled as shown in Table 4, one wait
state is inserted in the current timing sequence, either in
memory access or 1/0 operation. Refer to. the CPU
(MK3880) section of the manual for wait state timing. The
wait state circuitry is normally. not enabled for 2.5 MHz
operation.

I/O PORTS
Counter/Timer 1/0 Ports
The CTC 1/0 ports are hardwired to respond to 1/0 Ports
7CH, 7DH. 7EH, and 7FH as shown in Table 2. For detailed
infqrmation on how to program the CTC, refer to the Mostek
erc Technical Manual.

Jumper pins, labeled E7 Pins 1-4 have been provided to
allow the Memory Expansion and 110 Expansion lines to be
tied to ground. This option can be implemented by
jumpering these pins as shown in Table 5.

1/0 PORT NO. VS. eTC CHANNEL NO.
Table 2

1/0 PORT

WAIT-STATE JUMPERS
Table 4

CTCCHANNEL

o
Wait
Operation State

1

2
3

RESET/RESTART JUMPERS
The MDX-CPU1 has the : capability to reset and begin
execution at location OOOOH or EOOOH. Table 3 shows the
jumpers for selecting OOOOH to EOOOH was to allow the use
of Mostek's DDT-80 (Designer's Development Tool)
operating system. However, if DDT-80 is not used, then the
reset to EOOOH can be used for user programs. The jump to
EOOOH is implementing in hardware and must be reset after
it is activated. To resetthe jump circuitry, the following code
must be placed at EOOOOH:
EOOOH CS 03 50
EOO3H DB FF (Any liD . operation will reset the address
modification latch)
EOOOH (User program begins)
When using DDT-80, it is not necessary to execute this code
since it is already in the ROM.

OnCPU1
Connect

On CPU1A

OOOOH

U10Pin6t07

J4Pin 11 to 13

U10 Pin 6 t08

(Open)
U10 P13-14
E3 to E4

-

Memory
Access

Disabled

Memory
Access

Enabled

(Connect)
(Connect)
U10 P13 to 14 J4 Pin 2 t04
J2 Pin 1 to 3
E3 to E4

liD

Disabled

(Open)
U10 P13 to 14
E5 to E6

1/0

Enabled

(Connect)
(Connect)
U1QP13 to 14 J4 Pin 2 t04
J2 Pin 2 t04
E5 to E6

-

MEMEX
10EXP

On
MDX-CPU1

On
MDX-CPlI1A

Memory
Expansion
(MEMEX)

Connect E7
Pin 3 t04

ConnectJ6
Pin2 t04

Connect E7
Pin 1 to Pin 2

ConnectJ6 .
Pin 3 to Pin 1

liD
Expansion

. EOOOH

On
MDX-CPU1A

MEMEX AND 10EXP JUMPERS
Table 5

RESTART JUMPERS
Table 3

Desired
Reset
Location

On
MDX-CPU1

J4 Pin 11 to 14

..

IVB-4

CPU1 AND CPU1A STRAPPING OPTIONS
Figure 3
U5

0

2
3
4
5
6
7
8

0
0
0
0

U10

0 16
01 5
01 4
01 3

0

01 2
01 1

0
0

0 1o
0 9

J4

J3
01 4

0
2 0
3 0
4 0

01 2
01 1

5 0
6 0
7 0

01 o
0 9
0 8

2

0
0

0
3 0
5 0
7 0

01 3

0
3 0
5 0
7 0
9 0
11 0
13 0

4

0

6
8

0

12

0

o 1o

9 0
11

0
13 0
15 0

o

14

0
0

2

0
0

6
8

0

10

4

0 12
0 14

01 6

MDX-CPU1

MDX-CPU1A

ASSEMBLY DESIGNATOR DIFFERENCES
Figure 4

Signal

E7

J6

J2

GND

Pin 1

Pin 1

Pin 1

E3

GND

Pin 3

Pin 4

Pin 2

E6

IOEXP

Pin 2

Pin 3

Pin 3

E4

MEMEX

Pin 4

Pin 4

Pin 4

E5

MDX-CPU1A. MDX-CPU1

MDX-CPU1. MDX-CPU1A

STRAPPING: MDX-CPU1 AND MDX-CPU1 A

Memory Capacity

Both assemblies have the same physical placement of the
strapping options. Figure 3 does denote the difference in the
numbering scheme used for each assembly. Please note
that only the numbering ofthe headers have been changed
and not the routing of the signals to the headers.

On-Board EPROM - 4K bytes (sockets only)
On-Board RAM - 256K bytes
Off-Board Expansion - Up to 65,536 bytes, with userspecified combinations of RAM, ROM, PROM
Memory Speed Required

Figure 4 further illustrates the difference in these two
assemblies designators.
ELECTRICAL SPECIFICATIONS
Word Size

Memory

Access Time

Cycle Time

2716*

450 ns

450 ns

*Single 5-Volt type required

Instruction: 8. 16. 24, or 32 bits
Data: 8 bits
Address: 16 bits

1/0 Addressing
On-Board Programmable Timer

Cycle Time
Clock period or T state
= 0.4 microsecond @ 2.5 MHz for MDX-CPU
= 0.25 microsecond @ 4.0 MHz for MDX-CPU1-4
Instructions require from 4 to 23 T States
Memory Addressing
On-Board EPROM: jumper selectable for any 2K boundary
within a 16K block of memory map.
On-Board RAM: FFOO-FFFF

IVB-5

PORT
ADDRESS (HEX)

MK3882
CHANNEL

7C
7D
7E
7D

o
1
2

3

110 CapacitY

MECHANICAL SPECIFICATIONS

Up to 252 Port addresses can be decoded off-board. (Four
port addresses are on-board. 252 + 4 = 256 total 110 ports).

Card Dimensions

Interrupts

4.5 in. (11.43 cm) high by 6.50 in. (16.51 cm) long
0.48 in. (1.22 cm) maximum profile thickness
0.062 in. (0.61 cm) printed-circuit-board thickness

Multi-level with three vectoring modes (Modes 0, 1, 2).
Interrupt requests may originate from user-specified 1/0 or
from the on-board MK3882 CTC.

Connectors

STD-Z80 BUS Interface
Inputs
Outputs

One 74LS load max
IOH =-3 mA min. at 2.4 Volts
IOL = 24 mA min. at 0.4 Volts

Function

Configuration

Mating Connector

STD Bus

56-pin dual

Printed Circuit
Viking 3VH28/1CE5

0.125 in. centers

Wire Wrap
Viking 3VH28/1CND5

System Clock

MDX-CPU1
MDX-CPU 1-4

MIN.
500 KHz
500 KHz

MAX.
Solder Lug
Viking 3VH28/1CN5

2.5 MHz
4.0 MHz

Power Supply Requirements
5 V± 5% at 1.1 A maximum
Operating Temperature

ORDERING INFORMATION
Designator

Description

Part No.

MDX-CPU1

Module with technical Manual less EPROMs. 2.5 MHz version.

MK77850-0

MDX-CPU1

Module with Technical Manual less EPROMs. 4.0 MHz version.

MK77850-4

MDX-CPU1 and 1A
Technical Manual

MDX-CPU1 and 1A Technical Manual only.

4420031.

MDX-CPU1A

Module with Technical Manual less EPROMs. 2.5 MHz version with
Bi-directional SYSRESET

MK77855-O

MDX-CPU1A4 MHz

Module with Technical Manual less EPROMs. 4.0 MHz version with
Eli-directional SySRESET.

MK77855-4

IVB-6.

I!I

UNITED
TECHNOLOGIES
MOSTEK

COMPUTER
PRODUCTS
DIVISION
MDX-CPU2A
MK77856-D, MK77856-4
Z8D CENTRAL PROCESSOR MODULE

FEATURES
CONNECTOR AND HEADER LAYOUT
o Utilizes the powerful Z80 Microprocessor

Figure

,,-------.=r-------.----..,
J3

o

Six 24-pin sockets are provided which may be strapped
to accept any combination of the following industrystandard memory devices:

EPROM

STATIC RAM

ROM

2758 (lK x 8)

MK4118(lKx8)

MK34000 (2K x 8)

2716 (2K x 8)

MK4801 (1 K x 8)

2732 (4K x 8)

MK4802 (2K x 8)

o

Memory decoding on any 1 K boundary

o

Bidirectional address, data, and control busses to permit
external DMA

o

Four cascadable counter/timer channels

o

Automatic, transparent dynamic memory refresh

o

Fully buffered signals for system expandablility

o

Selectable reset address to either OOOOH or EOOOH

o

Selectable wait-state generator

o

Bidirectional reset which allows operation with the
MDX-PFD (Power Fail Detect)

-~_.---..J

J4

J6

o

J1

o

4 MHz version available

o

Single +5 Volt supply

o

STD-Z80 BUS compatible

user may, by programming a new decoder PROM, assign
any of the six sockets to memory addresses as required by
his application needs. Address, data, and control busses
have been made bidirectional to allow external masters to
directly access CPU memory.

MDX-CPU2A DESCRIPTION
The MDX-CPU2A features six 24-pin memory sockets
which enable the user to populate the module with various
combinations of ROM, RAM, and EPROM. Flexible address
decoding allows the user to configure each memory device
within any 1 K boundary ofthe 64K memory map. A decoder
PROM is supplied which will allow the user to choose one of
four preselected memory configurations or, if desired, the

A4-channel counter/timer circuit(MK3882) is included on
board for software controlled counting and timing
functions. The counter/timer circuit (CTC) Trigger inputs
and Zero Count outputs are buffered and brought out to a
connectorfor external access. In addition, a strapping option
makes it possible to cascade the four CTC channels for
longer count sequences.
A 4 MHz version of MDX-CPU2A is also available (MDXCPU2A-4). To ensure sufficient memory access time at 4
MHz operation, a jumper option enables automatic
insertion of one WAIT state for those memory devices
idenified as "slow" by the decoder PROM. The standard
decoder PROM supplied with MDX-CPU2A-4 is preprogrammed for use with MK2716 EPROMs and MK4118
Static RAMs, and identifies 2716 sockets as "slow" and
4118 sockets as "fast".

IV8-7

MDX-CPU2A DIAGRAM
Figure 2

lClOCK~
GEN

BY_
2
_

.

f~
t~ CS1

MK3880
CPU

I''''....'"G~I-OPTIONS

STATE
GEN

~

<-

WAIT

r-

RESET

7
CH -3

:::>

~
~

+

A2· A7

~

<::-

ADDRESS

V
DATA

+ClK I

V

CASCADEJ
STRAPPING

J DIRECTION
DATA BUS

()

A15 - AO

V

II

II

D7 - DO

II

1\

\

:":
'""'"""'
••• A"D
CONTROL

I

lOGIC

I

r - ~ EXTERNAL TRIGGER

~

MK3882
CTC

~ORTSElECT

t

h
\

+


CSO

CONTROL
SYSTEM
RESET

I'

I

II

'---

~,RESET

PB RESET

_p

CONTROL
lOGIC

++

~DIR

OPTIONS

~

DECODE
lOGIC

"-

A15-A10

MEMORY

I"--"'""

DATA
BUFFER

P

STD·

zao

~ STRAPPING

CONT AD DR

DIR

;>

r---

P

~

ADDRESS
BUFFER

I

DECODE
OPTIONS

CPUMEM DECODE

BUS

<=-

~DIRp
--"
CONTROL

L

BUS
(J1)

BUFFER

CONTROL
BUFFER

~1
__

~
./

(6 SOCKETS)

'--'""'

MEMORY REFRESH:

1/0 CAPACITY:

The MDX-CPU2A generates all address and control signals
necessary to refresh dynamic RAM (such as MDX-DRAM)
modules. Refresh occurs automatically during each OP
code fetch cycle and is, therefore, transparent to system
throughput.

The MK3880 (Z80-CPU) utilizes the lower 8-bits of its
address bus for I/O addressing yielding a total of 256
possible port addresses.

1/0 ADDRESSING

The MK3880 (Z80-CPU) may be programmed to process
interrupts in any of three different modes (mode 0, 1, or 2).

The on-board 4-channel programmable timer is hard-wired
to the following port addresses:

MK3882 Channel

Port Address (Hex)

o

7C

1

7D

2

7E

3

7F

INTERRUPTS:

Multi-level interrupt processing is also possible with the
MK3880. The level of stacking is limited only by available
memory space.
The MDX-CPU2A will also accept nonmaskable interrupts
which force a restart at location 0066H.

IV8-8

CONNECTORS AND HEADERS

J3 Memory Address Decoder

J1 STD-Z80 BUS
56-Pin (see STD-Z80 BUS description). Pins not connected:
5, 6, 35, 36, 40, 50, 53-56.

One of four different memory configurations is selected by
J3. Additional memory may be added on the STD-ZSO BUS
to a maximum of 64K byte total. See Table 1 for J3
strapping.

J2 CTC Connector

J4 CTC Channel Cascading

The CTC signals are buffered and brought out to connector
J2.
Logical low .5 V at 24 rnA
Logical high 2.4 V at -3 rnA

J4 allows cascading of the CTC channels.

Function
CLKITRGO
ZCITOO
CLKITRG 1
ZC/TO 1
CLKITRG 2
ZCITO 2
CLK/TRG 3
NC
*NMI
NC
GND

Pin

1
2
3
4

5
6
7

8
9
10-13
14-26

Pin

Function

1
2
3
4
5
6
7
8

NMI (seeJ2)
CLKITRG 0
ZC/TOO
CLK/TRG 1
ZCITO 1
CLKITRG 2
ZCITO 2
CLKlTRG 3

J4 Strapping
4

2

*The CPU will respond to an externally generated nonmaskable interrupt. The signal is logically OR'ed with
NMIRQ, (pin 46) on the STD-Z80 BUS.

•
•

I

1

3

6

8

5

7

• •
• •

Example showing
channels 0 & 1
cascaded

Note: If the eTC channels are cascaded on J4, the corresponding pins of J2 must be

left open.

J3 STRAPPING
Table 1

Option 0
2

Option 1
2

4

I I
1

I
1

3

BEG

Option 2

4

2

4

•

I

•

•
•

1

3

BEG

Option 3
2

4

1

3

• •
• •

3

BEG

BEG

Size

AD DR

Speed

Size

ADDR

Speed

Size

ADDR

Speed

Size

ADDR

Speed

U7

2K

0000

Slow

2K

0000

Slow

2K

EOOO

Slow

2K

0000

Slow

U8

2K

0800

Slow

2K

0800

Slow

2K

E800

Slow

2K

0800

Slow

U9

1K

FOOO

Fast

1K

1000

Slow

1K

FOOO

Fast

1K

1000

Slow

U14

1K

F400

Fast

1K

1800

Slow

1K

F400

Fast

1K

1800

Slow

U15

1K

F800

Fast

1K

F800

Fast

1K

F800

Fast

1K

2000

Slow

U16

1K

FCOO

Fast

1K

FCOO

Fast

1K

FCOO

Fast

1K

FCOO

Fast

IVB-9

II

J5 Reset Address Strapping

2.~~.12

J5 sets the reset address to' OOOOH or EOOOH. If reset
address EOOOHis selected the first instruction in the
program at EOOOH must be a jump to E003H. Then, an
1/0 read must be performed before any address below
EOOO is accessed. If no 1/0 access is required in the
program, then a "dummy" 110 read or write to an unused
port address must be inserted:

Example

Address
EOOO
EOO3
EOO5

4

2
J5 •

•
1

2758 EPROM

2\~

2\

2.

\ y •• 12

1~.11
MK4118/4801 SRAM

\.y •• 12

1..1t'\\ • • 11

E1
Pin 1 and 2 ofthe El header must be connected when the
MOX-SST is used.

3

1

Reset
Address
OOOOH

2732 EPROM

2716 EPROM
MK34000 ROM

MK4802 SRAM

I

•

3

•• 12

1~""11

4

2
J5 •

•
•

1~"'.11 1~"'.11

Instruction
JP EOO3H
IN A. (nn)
First instruction of user
program.

Code
C303EO
OBnn

2\~ • • 12

Reset
Address
EOOOH

MEMORY ACCESS TIME

J6 Wait State Generator
One wait state must be inserted for on-board memories
which are designated "slow" for memory access time.

The time required to access on-board CPU2A memory by
external OMA controllers is tYpically 106 ns plus the access
time of the memory device. This is defined as the time
interval between the time memory address is valid on the
STO BUS and the time output data is valid on the STO BUS.
Maximum Memory Access Time From Chip Enable

2

J6

1

2

4

••
••
3

No wait
states

J6

4

•
I•
3

One wait
state for
selected
on-board
memories.

2

J6

•
•
1

I II
2

4

4

J6

3

One wait
state for
interrupt
acknowledge
cycles.

3

One wait
state
inserted
for both
cases.

J7-J12 Memory Configuration Headers
Each header configures one socket for a particular type of
memory device.

Jumper

J7

J12

Socket

U7

U16

System
Clock
2.5
4.0

No Wait States
(Fast)

One Wait State
(Slow)

517ns
252ns

917ns
502ns

CUSTOMIZING THE MEMORY DECODER PROM
The user may find that the decoder PROM supplied with the
MDX-CPU2A ,does not hav!! a preprogrammed memory
map suitable for the user's particular application. In this
case, a custom decoder PROM can be programmed.
The primary functions of this PROM are to provide the chip
enable, for each of the six on-board sockets, indicate
whether the device in that particular socket will require a
wait-state (should the device have a slow access time or
require it for 4 MHz operation), and control the direction of
the bus buffers (inward for on-board memory accesses and
outward for off-board memorY accesses). In addition, this
memory decoder PROM will permit four separate memory
schemes or maps.

IV8-10

Looking at Table 2 and the Figure below, we see that the
data that should be programmed in the PROM for option #3
should be as follows:

The 256 x 8 PROM can be visualized as four separate 64 x 8
blocks. The two most significant input pins to the PROM (A6
& A7) determine which of the four blocks you will be
operating in. The lower six input pins (AO through A5) are
connected to A 10 through A 15 of the Address Bus.
Because it takes address lines (AO through A 10) to address
1024 memory locations, the A 10 through A 15 address
lines will split memory into multiples of 1024 (1 K bytes).
Each location in the PROM represents a 1K boundary. This
is ideal case since we have 64 bytes in each section; each
byte will decode a 1K boundary, and we wish to decode a
64K memory map.

PROM DATA CALCULATIONS
Figure 3

LOCATION

DATA

CO
C1
C2
C3
C5
C6
C7
C8
C9
CA - FE

3E
3E
3D
3D
3B
3B
37
37
2F
2F
FF

FF

1F

C4

Selecting option number 3 (no jumpers on J3), the memory
decode PROM is set up for five 2K EPROMs (2716's) to be
addressed from OOOOH to 27FFH and one 1K device
(MK4118 Static RAM) to be addressed from FCOOH to
FFFFH.
PROM DATA
Table 2

SOCKET

t
t
t

U7 (2716)

t
t

U14(2716)

U8 (2716)
U9 (2716)

!J15 (2716)
No On-board
Sockets Selected
U16(MK4118)

WAIT STATES
WITH
WITHOUT
CS1 =
CS2 =
CS3 =
CS4=
CS5 =
CS6 =

3E
3D
3B
37
2F
1F

CS =

FF

This can be verified by comparing this table data to the data
found in the MK6289 listing. (The shipped PROM is
configured for slow devices, ie wait states are inserted.)

7E
7D
7B

The data to be entered into the PROM is computed by the
chart in Table 3. The signal to enable a particular socket is
an active low signal. This is indicated by the bar over the
signal name (lCS1 etc.) To select the first socket U7, a 0
(low) is the desired condition from output bit O. Output Bits
1-6 will be 1 's to ensure that only one socket is selected at a

77
6F
5F

(All selected memory is off-board)

MEMORY MAP
Figure 4

PROM
LOCATION

co I_

MEMORY
DECODE

PROM
LOCATION

1ST ••• 1 K··· -,0000,

Cl ,. 2ND ••• 1 K • • • • 1 0400 '\
C2 • 3RD ••• 1 K • • • • , 0800
'\
C3 ,. 4TH ••• 1 K • • •• o c o o ,

I· ••••••••••••

C4

00 , - -

I 1000,

C5 ,- • • • • • • • • • • • • I 1400
C6 • • • • • • • • • • • • • I 1800
C7 I ••••••••••••• I 1 COO

,

40
,
,

csl·············2000
C9

'\

CAI·············12800
..!1
EO II

FO

/
,.I'
,.I'

,

I

1

1

I

OPTION 1

I

I

1- - - - - - I

:

OPTION 2

'Col------

/

/'

'

,/

FEI·············1FBOO

FF

"

:8000

1

-

I
I
1- - - - - - I

.1

,

1

-

'.1

1 COOO
1
1

1..

,

1

I
I

I

80

:4000

I
1

I

-

OPTION 0

'I

• 10TH • • • lK • • • • , 2400

DO:

-

I

I·!~H,:, •..:1~~ ::':1 ~~~~

IV8-11

,/

1

I

I

OPTION 3

1

F~I------I

particular time. Output.8it6isa 0 if the user wants a wait
State to beiriserted every time. this particular socket is

accessed. Output 8it 7 controls the buffer direction, so if any
sOCket is selected oncboard, this output bit must be ,a 0 (low.)

PROM DATA CALCULATION
'c
Table 3
I
OUTPUT BIT
FUNCTION
LOCATION

I

I

ANYCS

I

.'

with
wait

, states

without

wait
states

i ';',

I

6

7

WAIT

4

3

2

CS5

CS4

U15

U14

CS3
Og',

5

-

CS6
' U16

0
0
0
0
0
0

0
CS2
UB

1

0
0
0
0
0
0

'1
1

0

0

' 1

CS1
' U7

1
0
1,

1
,0

=3E

0

=30
=3B, '
,1

=37
'"2F
=IF

0

, 1,

0
0
0
0
0
0

1
1
1

0
1

0

1

1

1
0
1 ,
1

0

=7E

0

=70

0

=7B
=77
=6F

1
.1

,1

=5F

no

=FF

'~elect

PROM DATA PATTERN,
MK6289
(NMI 6309-1J 25.6 X 8)
Table 4
LOC DATA LOC DATA LOCDATA LOC ,DATA LOC DATA LOC DATA LOC DATA LOC DATA

-----

----

05
06
07

" 3E
3E
3D
3D
FF
FF
FF
FF

20
21
22
23
24
25
26
27

FF
FF
FF
FF
FF
FF
FF
FF

08
09
OA
08
DC
OD
DE
OF

FF
FF
FF
FF
FF
FF
FF
FF

28
29
2A
28
2C
2D
2E
2F

FF
FF
FF
FF
. FF
FF
: FF
FF

00

01
02
03
04

40

41
42
43
44

45
46
47
,48
49
4A
48
4C
4D
4E
4F

--

-- --- -- - - -- ---

3E
3E
3D
3D
38
38
37
37

60
61
62
63
64
65
66
67

FF
FF
FF
FF
FF
FF
FF
FF

80
81
82
83
84
85
86
87

AO
FF
FF
A1
FF, A2
FF "A3
A4
FF
FF. A5,
A6
FF
A7
FF

FF
FF
FF
FF

68
69
6A
68
6C
6D
6E
6F

FF
FF
FF
FF
FF
FF
FF
FF

88
89
8A
88
8C
8D
8E
8F

·FF

FF,

FF'
FF
FF

IVB-12

FF
3E
CO
FF
C1
3E
FF
C2
3D
FF
3D
C3
FF "C4
38
FF
C5 .38
FF
G6
37
FF
C7
37

AS,
FF
fF
A9
FF
AA , FF
FF
FF
A8
FF
FF
AC
FF
FF
AD
FF
FF
AE
FF
FF ' AF
FF

"

C8
C9
CA
C8
CC
CD
CE
CF

2F
2F
FF
FF
,FF
FF
FF
FF

EO
E1
E2
E3
E4
E5
E6
E7

FF
FF
FF
FF
FF
FF
FF
FF

E8
E9

FF
FF
FF
FF
FF
FF
FF
FF

EA

E8
EC
ED
EE
EF

PROM DATA PATTERN (Continued)
MK6289
(NMI6309-1J 256 x 8)
Table 4

lOC DATA lOC DATA lOC
------ - - -

DATA lOC DATA lOC DATA lOC DATA lOC DATA LOC DATA

FF
FF
FF
FF
FF
FF
FF
FF

30
31
32
33
34
35
36
37

FF
FF
FF
FF
FF
FF
FF
FF

50
51
52
53
54
55
56
57

FF
FF
FF
FF
FF
FF
FF
FF

70
71

18
19
1A
1B
1C
10
1E
1F

FF
FF
FF
FF
FF
FF
FF
FF

38
39
3A
3B
3C
3D
3E
3F

FF
FF
FF
FF
7B

58
59
5A
5B
5C
50
5E
5F

FF
FF
FF
FF
FF
FF
FF
FF

77
6F
5F

---

----

10
11
12
13
14
15
16
17

73
74
75
76
77

FF
FF
FF
FF
FF
FF
FF
FF

90
91
92
93
94
95
96
97

FF
FF
FF
FF
FF
FF
FF
FF

BO
B1
B2
B3
B4
B5
B6
B7

FF
FF
FF
FF
FF
FF
FF
FF

DO
01
02
03
04
05
06
07

FF
FF
FF
FF
FF
FF
FF
FF

FO
F1
F2
F3
F4
F5
F6
F7

FF
FF
FF
FF
FF
FF
FF
FF

78
79
7A
7B
7C
70
7E
7F

FF
FF
FF
FF
FF
FF
6F
5F

98
99
9A
9B
9C
90
9E
9F

FF
FF
FF
FF
FF
FF
FF
FF

B8
B9
BA
BB
BC
BO
BE
BF

3E
3E
3D
3D
7B

08
09
OA
DB
DC
DO
DE
OF

FF
FF
FF
FF
FF
FF
FF
FF

F8
F9
FA
FB
FC
FO
FE
FF

FF
FF
FF
FF
FF
FF
FF
1F

72

TECHNICAL SPECIFICATIONS

6F
5F

System Clock
MOX-CPU2A:

Card Dimensions:
4.50 in. (11.43 em) wide by 6.50 in.(16.51 em) long
0.675 in. (1.71 em) maximum profile thickness
0.062 in. (0.16 em) printed circuit board thickness

77

2.5 MHz ± 0.05%

MOX-CPU2A-4:

4.0 MHz ± 0.05%

Operating Temperature:
O°C to 60°C

STD BUS Edge Connector:
POWER SUPPLY REQUIREMENTS
56-Dual Readout; 0.125 in. centers
5 V ± 5% @ 1.2A (excluding memory power
requirements)

Mating Connectors
PCB - Viking 3VH28/1 CE5
Wirewrap - Viking 3VH28/1 CN05
Solder lug - Viking 3VH28/1 CN5

RELATED PUBLICATIONS

ELECTRICAL SPECIFICATIONS

The following are related publications:
System Design Using the Mostek STO-Z80 BUS (User's
Manual) - Publication No. 4420237

STD Bus Compatible

Z80 Microcomputer Data Book - Publication No. MK79602

System Interrupt Units:
1 SIU

IVB-13

III

ORDERING INFORMATION
Designator

Description

Part No.

MDX-CPU2A

2.5 MHz CPU2A module (less memory and mating
connectors)

MK77856-O

MDX-CPU2A-4

4.0 MHz CPU2A module (less memory and mating
connectors)

MK77856-4

MDX-CPU2A
Data Sheet

Data sheet for MDX-CPU2A and MDX-CPU2A-4

4420259

IV8-14

I!

UNITED

COMPUTER
PRODUCTS
DIVISION

TECHNOLOGIES
MOSTEK

MDX-CPU3

FEATURES

MDX-CPU3

o Z80-STD Bus compatible CPU board

o

A 28 pin socket for industry standard Bytewide ROMs or
EPROMs

o Flexible memory decoding of ROM/EPROM memory on
any 2K boundary

o 64K x 8 of onboard dynamic RAM

o

Phantom ROM capability

o

Bidirectional address, data, and control busses to permit
external DMA to onboard memory

o

8 bit output port with handshake (Centronics printer
interface)

o

Full handshake serial RS232 I/O Port

o

Software programmable Baud rates to 9600 Baud

o

Bidirectional power on reset which allows operation with
power fail controllers

o

Two programmable 8-bit timers with output

o

Fully buffered signals for system expansibility

o

Supports multiple memory banks

o

Supports MEMEX capability

The 8 bit parallel output port with handshake lines is
configured to accomodate direct connection to a Centronics
type pri nter interface.
The RS232 serial port is configured to accommodate full
handshake capabilities (interface type D).
ELECTRICAL SPECIFICATIONS

MDX-CPU3 DESCRIPTION
STD-Z80 BUS COMPATIBLE
The MDX-CPU3 is a STD-Z80 Bus compatible single board
computer with 64K bytes of dynamic RAM, 2K to 32K bytes
of ROM/EPROM, an RS232-C serial port, and an 8 bit
output port with handshake for connection to a printer. The
CPU3 supports a very flexible memory map configuration by
the use of a memory configuration PROM. This allows the
RAM to be enabled/disabled in 2K byte increments and the
ROM/EPROM to be mapped on 2K boundaries anywhere
in the 64K memory map. Each different map is selectable
under software control. Address, data, and control busses
are bidirectional to allow external masters to access
memory on CPU3 directly.

SYSTEM INTERRUPT UNITS:
lSIU
SYSTEM CLOCK:
3.6864 MHz

± 0.05%

OPERATING TEMPERATURE:

IV8-15

O°C to 60°C

BLOCK DIAGRAM
Figure 2

....c'"

,

DATA

POWI;R SUPPLY REQUIREMENTS

8

SERIAL 1/0 CONNECTOR

+5 V ± 5% @ 2.3 A max
+12 V ± 5% @ 50 ma max
-12 V ± 5% @ 50 ma max

26 pin dual readout; 0.100 in. grid
MATING CONNECTORS

MECHANICAL SPECIFICATIONS

(P3)

FLAT RIBBON - Ansley 609-2600M
DISCRETE WIRES - Winchester PGB13A (housing)
Winchester 100-700205
(contacts 20-24 AWG)
Winchester 100-720265
(contacts 26-30 AWG)

CARD DIMENSIONS
4.50 in. (11.43 cm.) wide by 6:50 in. (16.51 cm.) long
0.675 in. (1.71 cm.) maximum profile thickness
0.062 in. (0.16 cm.) printed circuit board thickness

PRINTER CONNECTOR
STD BUS EDGE CONNECTOR

(J3)

(J2)

(Jl)
Same as Serial 1/0 Connector

56 pin dual readout; 0.125 in. centers
MATING CONNECTORS

(Pl)

PCB - Viking 3VH28/1 CE5
WIREWRAP - Viking 3VH28/1 CND5
SOLDER LUG - Viking 3VH28/1 CN5

I/O CAPACITY
The MDX-CPU3 utilizes 18 of the possible 256 port
addresses, leaving 238 port addresses available for
expansion by the user.

IVB-16

MEMORY REFRESH

CONNECTOR AND HEADER POSITIONS

All address and control signals necessary to refresh
external dynamic RAM modules are generated by
MOX-CPU3.

Figure 5

I/O ADDRESSING
The onboard ports are preprogrammed tothe following port
addresses:
PORT ADDRESS
Figure 3

DEVICE

PORT ADDRESS (HEX)

MK3801 STI
Parallel Output Latch
Memory Configuration

BO - BF
00
FF

----------------

1

J1

55

I/O MAP PROM PROGRAMMING GUIDELINES

STD BUS CONNECTOR

If it is desired to use port addresses other than those which
are supplied, then the following procedure should be used:

J1 The standard Bus pins used are buffered and brought
out to a 56 pin edge connector as shown:
SIGNAL
NAME

Each address in the I/O Map PROM corresponds
directly to a port address. The bits of the 4 bit control
word are defined as shown in Figure 4. Select the
desired port address and corresponding output bit
definitions for that address and program a new I/O
Map PROM with the new data.

·5 V
GNO
NC
07
06
05
04
A15
A14
A13
A12
A11
A10
A9
A8
RO"
MEMRO"
MEMEX (Note)
NC
NC
BUSRO*
INTRO*
NMIRO*
PBRESET*
NC
PCI
NC
-12 V

BIT DEFINITIONS
Figure 4

OUTPUT BIT DEFINITIONS
01
02
03
04

ACTIVE STATE

- Select STI
- Select Output
- Select Memory Config. Latch
- Any of the above Ports selected

High
High
High
Low

PROGRAMMING SERIAL CHANNEL AND TIMERS
Programming information for the serial channel and timers
can be found in the SERIAL TIMER INTERRUPT
CONTROLLER (ST!) Technical Manual, Mostek publication
number 4420250.
INTERRUPTS
The MDX-CPU3 will process external interrupts in theZ80CPU interrupt modes 0, 1, and 2. Internal (onboard)
interrupts can be processed only in modes 1 or 2.

PIN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56

J1

PIN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55

SIGNAL
NAME
+5V
GNO
NC
03
02
01
00
A7
A6
A5
A4
A3
A2
A1
AO
WR*
10RO*
NC
REFRESH*
STATUS 1*
BUSAK*
INTAK*
WAITRO*
SYSRESET*
CLOCK*
PCO
NC
+12V

SYSTEM RESET PRECAUTIONS
Oata in DYNAMIC RAM is not guaranteed to bevalid after a
PUSHBUTTON RESET has been initiated.

Note: If MEMEX is grounded on the motherboard. the
ground strap should be removed.

IVB-17

II

PRINTER CONNECTOR
J2 The printer port data and control signals are brought out
to a 26 pin connector as shown:

SIGNAL
NAME
/STB
01
02
03
04
05
06
07
08
NC
BUSY
PE
NC

J2

PIN
1
2
3
4
5
6
7
8
9
10
11
12
13

0
0
0
0
0
0
0
0
0
0
0
0
0

PIN

0
0
0
0
0
0
0
0
0
0
0
0
0

14
15
16
17
18
19
20
21
22
23
24
25
26

SIGNAL
NAME
GNO
GNO
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

GNO
RX
TX
RTS
CTS
OSR
GNO
RLSO
NC
NC
TCO
NC
NC

1
2
3
4
5
6
7
8
9
10
11
12
13

J3

0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0

PIN

SIGNAL
NAME

14
15
16
17
18
19
20
21
22
23
24
25
26

NC
NC
NC
NC
TAO
NC
OTR
NC
NC
NC
NC
NC
NC

1

U22 PIN 23

3

'5VDC
U22 PIN 26

5
7

'5VDC
U22 PIN 1

9
11

0
0
0
0
0
0

0
0
0
0
0
0

2

A11

4

·5VDC

6

A13

8

U22 PIN 26

10

A14

12

U22 PIN 1

J4 This header allows the ROM/EPROM socket U22 to be
configured to accept various devices. Figure 7 shows
the strapping needed for each device.
MEMORY STRAPPING CHART
Figure 7

J3 The serial comunication signals to perform an RS232
type interface are buffered and brought out to a 26 pin
connector as shown, the timer outputs are also
buffered and brought out on pins 11 and 18:
PIN

J4

U22 PIN 23

ROM/EPROM STRAPPING

SERIAL CONNECTOR

SIGNAL
NAME

PIN DEFINITION
Figure 6

DEVICE TYPE

STRAPS REQUIRED

2716
INTEL 2732
INTEL 2764
MK34000
MK37000
MK38000

J4 (3-4),
J4 (1-21,
J4 (1-21,
J4 (5-71
J4 (1-21
J4 (1-21,

(5-7)
(5-71
(9-11 )

(6-81, (10-12)

MEMORY MAP EXPANSION
The memory configuration PROM supplied with the MOXCPU3 utilizes maps 0, 4, 5, and 6 to support two types of
software packages. The first package is a system booted into
RAM then executed out of that RAM. It utilizes maps 0 and
5. The second utilizes maps 0, 4, 5, and 6; and supports a
bank memory scheme. If a custom map PROM which uses
all 8 memory maps is desired, then install J5 to get this
expansion.
MEMORY MAP PROM CONFIGURATION
The following chart shows the memory configuration maps
as supplied with each MOX-CPU3 module.

IV8-18

MEMORY MAP
Figure 8

MEMORY
ADDRESS

MAP

0

1

2

3

4

5

6

7

FFFF

RAM

NOT
USED

NOT
USED

NOT
USED

RAM

RAM

RAM

RAM

f~

_ ___

J:QQO___
DooO

- -

-- -

-

-- - - -- -

~~M& - --- - - - - - - -RAM

-- - -- - --

- - - -

-

OFF
BOARD
RAM

COOO

OFF
BOARD
RAM

ROM

RAM

Booo
Aooo

9000
aooo
7000
6000
5000
4000
3000
2000
1000
----

0000

ROM

MEMORY MAP PROM PROGRAMMING GUIDELINES

BIT DEFINITION LIST

Each memory MAP in the Memory Configuration PROM
consists of a series of nibbles which define wrich memory
is enabled. Each ofthese nibbles is4 bits wide. The functio,",
of each bit is defined by Figure 9.

1. SELECT EPROM: Causes the signal which enables the
RQM/EPROM for reading.

"

2. A 15 ADDRESS LINE OUTPUT: This bit generates the
4Ppermost address line to the onboard RAM memory.

BIT STATE CHART
3. S!=LECT RAM: Enables the onboard RAM. If SELECT
EPROM is also programmed, RAM will be write-only.

Figure 9

OUTPUT BIT DEFINITIONS

ACTIV~

01
02
03
04

LOW

- SELECT EPROM
- A 15 ADDRESS LINE OUTPUT
- SELECT RAM
- MEMORY EXPAND OUTPUT

LOW
HIGH

STATE
4. MEMORY EXPAND OUTPUT: This bit generates a
sign~1 which is defined by the STD-ZaO Bus specification
for the MEMEX signal. In most single board configurations, this bit is programmed low.

IVB-19

TESTCONNECTCR

PROGRAMMABLE LED

J6 This header is used for testing purposes only and is
strapped (Pin 2-3) a,t the factory. DO NOT REMQVE.

An LED is available to be programmed onloff at bit 04 (1X)
of port FFH. This may be used as a visual selftesti ndicator or
other appropriate user functions. This bit is also used in the
memory bank switching mode and the indicator will
illuminate when·addr?ssing bank 5.

ROMIEPROM ACCESS TIME
The time required for the ROM memory tdbeaccessed by
the CPU is defined by two specifications; ICS and 10E.
First, ICS access must 'be:::; 343 ns., Second, access time
from 10E must be :::; 242 ns. These requirements must be
met in order for data to meet the minimum setup time for
the CPU under worst case timing conditions. See Figme 10.
ACCESS·TIME'
Figure 10,

I"
343ns~
~L___________________~1_______

ICS

----i~

I

IOE

242ns

SQFTWARE PROGRAMMING GUIDELINES
The CPU3 can support a phantom HOM type of operation
where the ROM has just enough code to bring a larger
operating systen;l into RAM, then by switching to another
map, disables the ROM dynamically and begins operation in
a purely RAM configuration. A very simple method to do this
is to have memoiv map 0 in the configuration PROM act as
the boot-up map and then switch to a desired map
configuration. The following procedure is then followed:
A. Copy the ROM code into the RAM at the same address
range as the ROM.

-j

I

B. Switch maps by outputting a new map number to the
Memory Configuration port (OFFH), allowing the copy
of RAM code to enter the active memory.

DATA --------~(r~:::::::::::::j(~V_A_Ll_D_D_A_T_A
MULTIPLE MEMORY

B~NK

C. Execution Qf the program will continue at the next
. instruction now in the RAM.

OPERATION

The MDX-CPU3 supports a memory bank switching
operation which allows memory expansion beyond the
normal 64K byte limitation of the Z80.

Related Publications
The following are related publications:
Customizing the MDX-CPU3 PROMs Application'
Note #5 (4420301 )

Bank select is accomplished as follows. After the SYSTEM
BOOT operation has been performed and the first bank has
been selected, additional banks of memory can be enabled
and disabled by outputting a bank seJect byte to port FFH.
Figure 11 shows the control byte necessary to select each
additional bank of memory.

MDX-CPU3141/0 Drivers Application Note #1 0

MEMORY BANK OPERATION
Figure 11
It

SELECT
BYTE
01
02
04
08

BANK NO.
1
2
3
4

SELECT
BYTE

10'
20
40

8Q,',

"

,

J'

,BANK NO.
5 "
6
7
"
8

.,1"

,lVe;.20

'

...,,'

I!I

UNITED
TECHNOLOGIES
MOSTEK

COMPUTER
PRODUCTS
DIVISION

MDX-CPU4

FEATURES

o

MDX-CPU4
Figure 1

STD-Z80 Bus compatible CPU board

o Five 28 pin sockets for industry standard BYTEWYDETM
ROMs, EPROMs, or RAMs

o

Flexible memory decoding of RAM/ROM memory on
.
.
any 2K boundary

o

Phantom ROM capability

o

Bidirectional address, data, and control busses to permit
external DMA to onboard memory

o

8-bit output port with handshake (Centronics printer
interface)

o

Full handshake serial RS232-C I/O Port

o

Software programmable Baud rates to 9600 Baud

o

Bidirectional power-on reset allows operation with
power-fail controllers

o

Two programmable 8-bit timers with offboard outputs

o

Fully buffered signals for system expansibility .

o

Supports memory bank switching

o

Supports MEMEX (memory expand) capability

Centronics type printer interface using mass terminated flat
ribbon cable connectors .
. The RS232-C serial port is configured to accommodate full
handshake capabilities (interface type D).
All STD-Z80 signals are fully buffered to allow use of this
• board with other STD-Z80 compatible boards. This permits
future expansion of functional capabilities.

MDX-CPU4 DESCRIPTION
The MDX-CPU4 is an STD-Z80 Bus compatible single board
computer with five BYTEWVDE memory sockets'for ROM,
EPROM, or RAM, an RS232-C serial port, and an 8-bit
parallel output port with handshake for connection to a
printer. The CPU4 supports a very flexible memory map.
configuration by the use of a memory configuration PROM.
This allows the RAM/ROM to be mappe

s:

'ARAll£l

POWER SUPPLY REQUIREMENTS:
+5 V ± 5% @ 1.8 A max (excluding BYTEWYDE sockets)
+12 V ± 5% @ 50 rna max
-12 V ± 5% @ 50 rna max

I/O MAP PROM PROGRAMMING GUIDELINES

MECHANICAL SPECIFICATIONS

Each address in the I/O Map PROM corresponds directly to
a port address. The bits of the 4 bit control word are defined
as shown in Figure 4. Select the desired port address and
corresponding output bit definitions for that address and
program a new I/O Map PROM with the new data.

CARD DIMENSIONS
4.50 in. (11.43 cm.) wide by 6.50 in. (16.51 cm.) long
0.675 in. (1.71 cm.) maximum profile thickness
0.062 in. (0.16 cm.) printed circuit board thickness

If it is desired to use port addresses other than those which
are supplied, then the following procedure should be
used.

I/O MAP BIT DEFINITIONS
STD BUS EDGE CONNECTOR (J1)
56 pin dual readout; 0.125 in. centers
MATING CONNECTORS (P1)
PCB - Viking 3VH28/1 CE5
WIREWRAP - Viking 3VH28/1 CND5
SOLDER LUG - Viking 3VH28/1 CN5

Figure 4

SERIAL I/O CONNECTOR (J3)
26 pin dual readout; 0.100 in. grid
MATING CONNECTORS (P3)
FLAT RIBBON - Ansley 609-2600M
DISCRETE WIRES - Winchester PGB13A (housing)
Winchester 100-72020S
(contacts 20-24 AWG)
Winchester 100-72026S
(contacts 26-30 AWG)
PRINTER CONNECTOR (J2)
Same as Serial I/O Connector

OUTPUT BIT DEFINITIONS

ACTIVE STATE

01
02
03
04

HIGH
HIGH
HIGH
LOW

- Select MK3S01 STI
- Select Parallel Output Latch
- Select Memory Config. Latch
- Any of the above ports selected

PROGRAMMING SERIAL CHANNEL AND TIMERS
Programming information for the serial channel and timers
can be found in the SERIAL TIMER INTERRUPT
CONTROLLER (STI) Technical Manual, Mostek publication
number 4420250.

I/O CAPACITY

INTERRUPTS

The MDX-CPU4 utilizes 18 of the possible 256 port
addresses, leaving 238 port addresses available for
expansion by the user.

The MDX-CPU4 will process external interrupts in ZSO-CPU
interrupt modes 0, 1, and 2. Internal (onboard) interrupts
can be processed only in modes 1 or 2.

MEMORY REFRESH
SYSTEM RESET PRECAUTIONS
All address and control signals necessary to refresh
external dynamic RAM modules are generated by
MDX-CPU4.
I/O ADDRESSING

Data in DYNAMIC RAM is not guaranteed to be valid after a
PUSHBUnON RESET has been initiated.

CONNECTORS AND HEADERS

The onboard ports are preprogrammed to the port
addresses shown in Figure 3.
PORT ADDRESSES

The location of the connectors and headers is shown in
Figure 5.

Figure 3

STD BUS CONNECTOR
Device

Port Address (Hex)

MK3801 STI

BO-BF

Parallel Output Latch

DO

Memory Configuration

FF

J1

The STD Bus pins used are buffered and brought out

toa 56 pin edge connector as shown:

IVB-23

II

SIGNAL NAME PIN J1
+5V
GNO
NC

2
4
6

07

8

06
05
04
A15
A14
A13
A12
A11
A10
A9
A8
RO*
MEMRQ*
MEMEX (NOTE)
NC
NC
BUSRQ*
INTRQ
NMIRQ*
PBRESET*
NC
PCI
NC
-12 V
.

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56

PRINTER CONNECTOR

PIN SIGNAL NAME

--I

1

I

3
5
7

9
11
13
15
17
19
21
23
25

27
29
31

33
35

37
39
41
43
45

47
49
51
53
55

I
1
__

+5V
GNP
NC
03
02
01

J2
The printer port data and control signals are brought
out to a 26 pin connector as shown.
SIGNAL NAME PIN
/STB
01
02
03
04
05
06

00
A7
A6
A5
A4
A3
A2
A1
AO
WR*
IORQ*
NC
REFRESH*
STATUS 1*
BUSAK*
INTAK*
WAITRQ*
SYSRESET*
CLOCK*
PCO
NC
+12V

07
08
NC
BUSY
PE
NC

0

0
0

4

0

5
6

0
0

7
8
9

0
0
0

10
11
12
13

0
0

0
0

o
o
o
o
o
o
o
o
o
o
o
o
o

14
15
16
17
18
19
20
21

22
23
24
25
26

GNO
GNO
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

J3
The serial communication signals to perform an
RS232 type interface are buffered and brought out to a 26 .
pin connector as shown; the timer outputs are also buffered
and brought out on pins 11 and 18.
J2

SIGNAL NAME PIN

CONNECTOR. HEADER. AND BYTEWYDE SOCKET
POSITIONS
Figure 5 r----t
J3

o

1

2
3

PIN SIGNAL NAME

SERIAL CONNECTOR

*Indicates active low signal
NOTE: If MEMEX is grounded on the motherboard, the groundstrap should be
removed.

J2

J2

GNO
RX
TX
RTS
CTS
OSR
GNP
RSLO
NC
NC
TCO
NC
NC

1

2
3
4

5
6
7
8
9
10
11
12
13

o
o
o
o
o
o
o
o
o
o
o
o
o

PIN SIGNAL NAME

0 14
0 15
0 16
0

17

0 18
0 19
0

0
0
0
0
0
0

20
21

22
23
24
25
26

NC
NC
NC
NC
TAO
NC
OTR
NC
NC
NC
NC
NC
NC

J4

MEMORY MAP STRAP
J4
Ajumper on J4 allows all eight memory maps in the
memory configuration PROM (see section entitled
MEMORY MAP PROM) to be accessed. With J4 open,
access defaults to maps 4, 5, 6, and 7. The board is shipped
with J4 open.
RAM/ROM/EPROM STRAPPING

Jl

55

J5-9
These headers allow the BYTEWVPE sockets 1-5
(U6-U2) to be configured to accept various devices. Figures
6 and 7 show the headers and strapping needed for each
device. These are typical figures showing the relationship
between J9 and socket 1 (U6). The same relationship
applies between J8 and socket 2 (U5), J-] and socket 3 (U4),
IVB-24

MEMORY MAP PROM

J6 and socket 4 (U3), and J5 and socket 5 (U2). The board is
shipped with no straps installed in J5, J6, J7, J8, or J9.

The memory map PROM (U14) contains eight memory
configuration maps. As the chart in Figure 8 indicates,
resolution of the maps is 2K blocks. The numbers enclosed
in brackets [ ], represent BYTEWYDE memory sockets on
board as shown in Figure 5. The memory installed may be
either RAM or ROM. The indication (RAM) represents offboard RAM.

MEMORY CONFIGURATION HEADER
Figure 6

J9
AD13
U6 pin 1
AD14
AD11
NC

-

-

1
3
5
7
9

0
0
0
0
0

0
0
0
0
0

(TYPICAL)
2 - U6pin 26
4 - +5VDC
6 - +5VDC
8 - U6 pin 23
10- IMEMWR

If bank switching is desired, the section entitled MULTIPLE
MEMORY BANK OPERATION describes the use of jumper
J4 and the various memory maps in obtaining this.

CONFIGURATION STRAPPING CHART
Figure 7

DEVICE TYPE

STRAPS REQUIRED (TYPICAL)

2716
INTEL 2732
INTEL 2764
MK34000
MK37000
MK38000
MK4802

J9 (2-4), (6-8)
J9 (2-4), (7-8)
J9 (3-4), (7-8)
J9 (2-4)
J9 (7-8)
J9 (1-2), (3-5), (7-8)
J9 (2-4), (8-1 0)

MEMORY MAP PROM PROGRAMMING GUIDE
LINES

Each memory MAP in the Memory Configuration PROM
consists of a series of bytes which dtlfine what memory is
enabled. The function of each bit of the byte is defined by
Figure 9.
BIT DEFINITION LIST
1. SELECT SOCKET ONE TO FIVE: These bits generate the

MEMORY CONFIGURATION MAPS
Figure 8

MEMORY
ADDRESS

MAP

0

1

2

3

4

5

6

7

FFFF

(RAM)

(RAM)

(RAM)

(RAM)

(RAM)

(RAM)

(RAM)

[1]

£0Q9- - EOOO
---DOOO

(RAM)
[1]

---- ---- ---- ---- - - - - ----

(RAM)

(RAM)

COOO
BOOO
Aoq} _ _

---- ---- - --- --- ---- -- -8000
- - - - - --- ---- --

jlOOO _ _

7000

~
[1]

6000
5000
4000 _ _

---- ------- ------2000
3000

----1000
-- 0000

---[1]

*

-

~
[1]

[ ] =CPU4 socket no.

(RAM)
IVB-25

=off board RAM

•

conditions .. See Figure 10..

BIT STATE CHART
Figure 9

MULTIPLE MEMORY BANK.DPERATION
ACTIVE. STATE

OUTPUT .BIT DEFINlTlpNS
01
02
03
04
05
06
07

- SelectSoc! - - - - - _ - - - O I

EXTERNAL
CLOCK,

',.

OUTPUT
PORT'OO
p--~....-¢ DATA
OUTPUT
p--~....-¢ PORT 01
DATA
IO--~""-o OUTPUT
PORT 02
DATA

0---.
OIi!:BOARD
CLOCK

ADDRESS
BUS

~ENERATOR

1"-

6

t.
['
INPUT
PORTS

J1-J2

INPUT'
PORT 01 C>------;_---~'-'--_Q
DATA

BUS AND
DECODED STROBES
TO 1/0 PORTS 02-07

SHADING INDICATES SOCKETS ONLY

sockets provided on the MD-SBC1.

PROGRAM MEMORY LOCATIONS
Table 1

RAM ADDRESSES
Table 2

PROM
NUMBER

ADDRESSES

0

OOOOH to 07FFH

RAM
NUMBER

ADDRESSES

1

0800H to OFFFH

1, 2 (standard)

02000H to 023FFH

2

1POOH to 17FFH

3, 4 (optional) ,

02400H to 027FFH

3

1BOOH to 1FFFH
ON-CARD I/O PORTS

DATA MEMORY
RAM data memory Consists of two (standard) or four
(optional)2114 RAM deviceS. The2114 isa 1024x4 RAM;
each pair of 2114's provides 1024 eight-bit words
organized as four 256-word memory pages. The standard
MD-SBC1 provides RAM memory in pages 20 through 23.
Two additional 2114 devices add RAM pages 24 through
27; these are implemented by plugging the devices in the

The MD-SBC1 provides two eight-bit input ports and three
eight-bit output ports. These ports provide 16 input lines
and 24 output lines that are available at the edge connector.
They are TTL compatible.

IVB-36

ON-CARD PORT ADDRESS (HEX)
Input Ports
Output Ports

00 and 01
00, 01, and 02

PORT EXPANSION

Nonmaskable Interrupt (NMII has the highest priority and
cannot be disabled.

MO-SBC1 can directly address additional 110 via two 16pin dip sockets(J2 andJ31. Oip connectorterminated cables
can interconnect user designed liD boards such as AlO
and 01 A converters, or UARTs and USARTs. The MO-SBC1
can access additional six 8-bit input and five 8-bit output
ports or devices in this manner. The control signals provided
at J3 are input and output select lines. They combine a
decoded port address with Z80's port Read or Write and
timing signals. The Input Select lines (IS-2 through IS-71
apply directly to 3-state enable pins, which gate data to the
Oata In Bus(J2, 01-0, through 01-2); the Output Select lines
normally clock output port latches loaded by the Oata Out
Bus (J2, 00-0 through 00-71. Figure 3 shows examples of
external 110 port implementation.

Interrupt Request (IREal is enabledldisabled by the
(Ell/(Oll instructions. The user can select one of three
modes that define the action taken when IREa is
honored.
Mode 0 - Execute any instruction at Interrupt, but the
instruction must be supplied by the interrupting device to the data in bus (01 0-71, J2.
Mode 1 - Execute the RST 38H instruction.
Mode 2 - Restart at any memory address according to a
selected address vector (16 bitsl stored in two
memory locations. The interrupting device
must supply the first 8 bits of the restart
address vector. The page address is previously
loaded by the program.

I/O EXPANSION
A large number of external liD ports may be mUltiplexed
through the on-card MO-SBC1 liD ports. However, this
type of expansion requires more Processor execution time.
Each liD operation must be preceded by an output
instruction, which selects the port and followed by output
instructions, which provide the output strobes.
In this technique, one MO-SBC1 on-card input port and one
output port are committed for use as data in and out busses.
As required, other output port lines are used as liD port
select, port card select, and port strobes.
INTERRUPTS
The MO-SBC1 has two low activated, level sensitive
interrupts with several designer options:

Modes 0 and 1 are summarized in Table 3.

MD-SBC1 INTERRUPT EXPANSION SUMMARY
Table 3

Interrupt

Priority

Restart
Address (Hex)

Mode

Nonmaskable

Highest

Address .66H

Any

IREa

Second

Address 38H

1

1/0 EXPANSION
Figure 3

INPUT
PORT
OATA

8

-+...---<11

8

1-_--._.:.,81--+----1 J2 1-+-...;8+~~_-i
7400
SERIES
lOGIC

010-7

DO 0-7

EXAMPLE OF
EXTERNAL PORT
EXPANSION
IS'
(J3)

INPUT PORT
(TYPICAL)

P----.--;'-+
7400
SERIES
LOGIC

os·

BRS'

(J3)

(J3)

OUTPUT PORT
(TYPICAL)

IVB-37

OUTPUT
PORT
OATA

MD-SBC1 DESIGNER.OPTIONS
The MD-SBC1 has 5 spare edge connector pins (5, 6, 52,
55,56), which may be connected from pads provided to the
signals listed below.
RESET (Active High Output)
EXTERNAL CLOCK INPUT
DECODED PAGES 28-2F, 30-37, 38-3F (3 lines)
ADDRESS Lines A 13, A 14, A 15
BUFFERED WRITE,BWR (Active Low Output)

wait state
RAM: 2114 orequivalent(1 Kx4)267.6 nsmaxwith nowait
state
INPUTS
2 Interrupt requests
16 Data lines (2 input ports)
1 ROY control (active high)
1 Reset Control
Port Expansion Data Bus (J2; active high)
External clock input

SPECIFICATIONS
OUTPUTS

Mechanical Specifications

24 Latched Output Data lines (3 output ports)
1 clock signal
2 system resets (J3 and card edge)
Port Expansion Data Bus (J2; active high)
6 Input port strobes (J3)
5 Output port strobes (J3)

CARD DIMENSIONS
4.50 in. (11.43 em) high by 6.50 in. (16.51 cm) long
0.48 in. (1.22 cm) maximum profile thickness
0.062 in. (0.16 cm) printed circuit board thickness
CARD INCLUDES

POWER REQUIREMENTS

Card ejector
One Z80 Processor
1 K 8-bit bytes, 2114 RAM plus sockets for an added 1 K
bytes
Four ROM sockets for 2716 PROMs
Crystal clock circuit and provisions for external clock
Power-on and external reset
2 Input ports (8-bit)
3 Output ports (8-bit)

Vee =5Volts±5%at 1.2Amaximumfullyloaded(1oomA
per ROM,100 mA per RAM)
GND = Volts

o

OPERATING TEMPERATURE RANGE

CONNECTOR REQUIREMENTS
Electrical Specifications
MEMORY
PROM: 2716 or equivlent (2K x 8) 300 ns max with no

56 pin, 28 position dual-readout on 0.125 in. (0.318 em)
centers
Printed Circuit: Viking 3VH28/1 CE5
Wire Wrap: Viking 3VH28/1 CN5

IVB-38

MD-SBC1 J1 EDGE CONNECTOR PIN LIST
Table 4

Signal

Signal

Pin Number

+5 VOLTS

IN

2

1

IN

+5 VOLTS

GROUND

IN

4

3

IN

GROUND

I/O

6

5

1/0

SPARE

INO-5

IN

8

7

1/0

IN1-5

INO-6

IN

10

9

IN

IN1-6

INO-7

IN

12

11

IN

IN1-7

INO-8

IN

14

13

IN

IN1-8

INO-4

IN

16

15

IN

IN1-4

INO-3

IN

18

17

IN

IN1-3

INO-2

IN

20

19

IN

IN1-2

INO-1

IN

22

21

IN

IN1-1

OUTO-1

OUT

24

23

OUT

OUTO-5

OUTO-2

OUT

26

25

OUT

OUTO-6

OUTO-3

OUT

28

27

OUT

OUTO-7

OUTO-4

OUT

30

29

OUT

OUTO-8

OUT1-1

OUT

32

31

OUT

OUT1-5

OUT1-2

OUT

34

33

OUT

OUT1-6

OUT1-3

OUT

36

35

OUT

OUT1-7

OUT1-4

OUT

38

37

OUT

OUT1-8

OUT2-1

OUT

40

39

OUT

OUT2-5

OUT2-2

OUT

42

41

OUT

OUT2-6

OUT2-3

OUT

44

43

OUT

OUT2-7

OUT2-4

OUT

46

45

OUT

OUT2-8

INTA

I/O

48

47

IN

IREO

NMI

IN

50

49

IN

RDY

SPARE

I/O

52

51

OUT

TIll

RESET

IN

54

53

OUT

RST

SPARE

1/0

56

55

1/0

SPARE

SPARE

Pin Number

Signal Flow

Signal Flow

IVB-39

II

I/O PORT EXPANSION SOCKETS
Table 5

J2 Data
Signal

Signal Flow

Pin Number

01·4

IN

16

1

IN

01 ·1

00·2

OUT

15

2

IN

01·8

00·4

OUT

14

3

OUT

00·6

00·1

OUT

13

4

OUT

00·7

01·7

IN

12

5

OUT

00·3

00·5

OUT

11

6

IN

01·5

00·8

OUT

10

7

IN

01·6

01·3

IN

9

8

IN

01 ·2

Signal Flow

Signal

Pin Number

Signal Flow

Signal

J3 Control And Power
Signal

Signal Flow

Pin Number

Pin Number

GNO

OUT

16

1

OUT

GNO

IS·2

OUT

15

2

OUT

BRS

IS·3

OUT

14

3

OUT

OS·3

IS·4

OUT

13

4

OUT

OS·4

IS·5

OUT

12

5

OUT

OS·5

IS·6

OUT

11

6

OUT

IS·7

OS·6

OUT

10

7

OUT

+5 VOLTS

OS·7

OUT

9

8

OUT

+5 VOLTS

ORDERING INFORMATION
Designator

Part Number

Description

MO·SBC1
MO·SBC1
Technical
Manual

MK77851
MO·SBC1 Technical Manual only

IVB·40

4420083

1983 COMPUTER PRODUCTS DATA BOOK
..... '~«:.
".~

., .

',~."
~: ,-".

:...
~ :

<.:.. ':

. ~.

-'",,'

MDX Series Input/Output
\

,

..

'

',<, .~'

;: ..;'i

.,,~

"

"
.~

"

;,

,

"

::#

,

,~.

: "
"

1

l!

COMPUTER
PRODUCTS
DIVISION

UNITED

TECHNOLOGIES
,..jOSTEK

SYSTEM INTERRUPT UNITS

SYSTEM INTERRUPT UNITS

Card

SIU's

MDX-A/D12
MDX-A/DB
MDX-AIO
MDX-BCLK
MDX-BRAM
MDX-CPU1/1A
MDX-CPU2I2A
MDX-CPU3
MDX-CPU4
MDX-D/AB
MDX-D/A12
MDX-DEBUG
DIOBl
DIOP
MDX-DRAMB/16/32/64/12B
MDX-EPROM
MDX-EPROM/UART
MDX-FLP/FLP2
MDX-INT
MDX-ISIO
MDX-MATH
MDX-MODEM
MDX-PFD
MDX-PIO
MDX-SASlll2
SBCl
MDX-SC/D
MDX-SIO/SI02
MDX-SRAM4/B/16
MDX-SST
MDX-UMC/UMC2
MDX-422

IVC-1

1
1

0
0
0
1
1
1
1

0
0
0
0
0
0
0
0
1
1
1
1
1

0
2
1

0
1
1

0
0
0
1

II

I'
I
1

IVC-2

I!J

UNITED

COMPUTER
PRODUCTS
DIVISION

TECHNOLOGIES
MOSTEK

MDX-FLP2

SUMMARY OF MDX-FLP2 FEATURES

MDX-FLP2
Figure 1

o STD-ZBO Bus compatible
o Controls single and double density disk drives
o Controls single and double sided disk drives
o Controls up to four 8 inch drives; up to three 5% drives
o Jumper selectable to handle either 5% or B inch drives
o Up to 4 MHz operation
o Provision for priority DMA daisy chain operation
o Provision for external devices to use DMA Controller
o Jumper selectable port addresses in blocks of eight
o Jumper selectable in main port space or IOEXP space
o Jumper selectable write precompensation
o Soft sector operation, including variable-length sectors
o IBM 3740 and System 34 diskette formatting capability
o Automatic track seek with verification
o Programmable step rate
o DMA or programmed data transfer

FLP2 can control both single-density, single-sided and
double-density, double-sided Shugart compatible disk
drives. In addition, either 5% or 8 inch drives may be used.
Transfers to and from the di~k are normally handled by the
MK38B3 DMA Controller; programmed data transfer is also
possible. Multiple FLP2 boards can be operated simultaneously since daisy chained priority DMA operation is
possible.

o Interrupt driven or polled operation
FLP2 operates with a wide variety of disk drives, such as
drives by Shugart Associates and Remex. Either 5% or 8
inch drives may be used; a simple change of three straps
converts FLP2 from a 51,4 inch controller to an 8 inch
controller. Write precompensation is also strappable.

o Automatic CRC generation and checking
o Single sector, multi. sector or full track data transfers
o Compatible with Mostek's M/OS-BO

INTRODUCTION TO MDX-FLP2
MDX-FLP2 is a floppy disk drive controller board for the
STD-Z80 bus. The MDX-FLP2 board embodies all required
controlling, formatting, and interface logic between the
STD-Z80 bus and one to four floppy disk drives.

Since FLP2 is based on the WD1797 Floppy Controller,
many advanced features are available. These include IBM
3740 or IBM System 34 diskette formatting capability,
automatic track seek with verification, programmable step
rate, and automatic CRC generation and checking. In
addition, single sector, multi-sector, or complete track
transfers are possible.

IVC-3

MDX-FLP2 BLOCK DIAGRAM
INTERNAL Buses

Figure 2

s

0
I

T

0

S
K

a

u

0

DATA

S

R

I
V
E

S

MK388·4
DMAC

SPECIFICATIONS
Memory Addressing:

On board DMA capable of
addressing any memory
address.

Electrical SpecificationJ
Data Bus:

B bits. bidirectional
Power Requirements:

Address Bus:

16 bits. lower 6 bidirectional.
upper S output during DMA
activity

+12 V ± 5% @ 100 mA max
+ 5 V ± 5% @ 1.2 A max

Operating Temperature:

O°C to 60°C

STD-Z80 Compatible

Mechanical Specifications

Inputs:

One 74 LS Load Max

Card Dimensions

Outputs:

IpH

= 15 mA min at 2.4 V

4.5 in (11.43 cm) high by 6.50 in (16.51 cm) long

IOL

=24 mA min at 0.5 V

0.4S in (1.22 cm) maximum profile thickness

System Bus:

0.062 in (.16 cm) printed circuit board thickness

System Clock:

Upt04 MHz

I/O Addressing:

Sports on board selectable to
any of 32 eight port slots by
jumper options; board may be
placed in main I/O space or
expansion I/O space (IOEXP)

Connectors

IVC-4

STD-ZSO Bus (J1 ) - 56 pins with .125 in. center
Drive Interconnect (J3) - 50 pins with.1 in. center

SYSTEM INTER-CONNECTION DIAGRAM
Figure 3

50 PIN I/O CABLE
J1

FLOPPY DISK
DRIVE 1

MDX-FLP2 BOARD

•
•
•
•

~il

FLOPPY DISK
DRIVE 4

L_

I

--,

I

..J

STD-280 BUS

DMA Daisy Chain (J2) - 8 pin dual right angle, _1 in_
center
Mating Connector for STD Bus (J1)

explains the purpose of each strap, and how the strap is set
at the factory.
J4:

Auto Precomp - When open, double density write
precompensation is always in affect (provided
DDEN* is low). This is primarily for 51,4 inch drives
that require write precompensation on every track.
When strapped, write data is precompensated only
for tracks greater than 43; this is the factory setting.

J5:

Test Points - Test points for factory use only.

J6:

VCO Clock - This clock is either a 4 MHzclock(pins
1 and 2 strapped) for 8 inch drives or a 2 MHz clock
(pins 3 and 4) for 51,4 inch drives.

J7:

8 inch Ready - When using an 8 inch drive, this
strap connects the Ready signal to FLP2. When
using a 51,4 inch drive, this strap is not connected.
Thus 51,4 inch drives will always appear ready.

J8:

8 or 51,4 inch Clock - Strap for either a 4 MHz clock
(pins3 and4)for8 inch drives or a 2 MHzclock(pins
1 and 2) for 51,4 inch drives.

J9:

51,4 inch drive - This strap may be used by software
to determine whether 51,4 or 8 inch drives are used.
Strap J9 for 51,4 inch drives.

Jl0:

Port Acldress Select - This option allows the user to
place FLP2 on any of 32 possible 8-port
boundaries. Figure 4 shows the various straps.
Note that a strap installed implies a logic zero. The
factory setting is EOH (111OOXXX).

P.C. 3VH28/1 CE5 (Viking)
Soldertail3VH28/1CN5 (Viking)

w. W. 3VH28/1 CND5 (Viking)
Mating Connector for Drive Interconnect (J3)

609-5000 W/O Strain Relief (Ansley)
609-5001 with Strain Relief (Ansley)
Mating Connector for DMA Daisy Chain (J2)
1-86148-8 (AMP)
References
1. Western Digital 1797 Data Sheet
2. Z80A DMA Data Sheet
3. STD-Z80 Bus Technical Manual

STRAPPING OPTIONS
FLP2 is customized by changing straps. Figure 5 shows the
locations of the straps, J4 - J12. The following discussion

IVC-5

connecting the signals to J2, an 8-pin connector at the top
of the board. In addition, pin 8 of J2 may be used for external
devices -- for example a PIO or SIO -- to access the READY
pin of the MK3883 OMA Controller.

ADDRESS STRAPPING OPTIONS
Figure 4

Address

Corresponding
Pinson J10

Factory Setting

10 and 9
8 and 7
6 and 5
4and 3
2 and 1

1 (not strapped)
1 (not strapped)
1 (not strapped)
(strapped)
(strapped)

A7
A6
A5

A4
A3
J11:

J12:

The configuration of the connector is shown in Figure 6.
Twisted pair cables with two-contact connectors at each
end are used to connect the bus priority chain.
DMA DAISY CHAIN CONNECTOR

o
o

Figure 6

1/0 Expand - 10EXP* is normally not used on

7

Mostek boards. The factory straps pins 2 and 3. If
the user desires to use 10EXP*, strap pins 1 and 2;
also strap pins 3 and 4.

8

EXT Ready Level- This jumper determines whether
the EXT ROY input to the FLP2 OMA is active low or
active high. For an active low EXT ROY, strap pins 2
and 3 (factory setting); for an active high EXT ROY,
strap pins 1 and 2.

1:

x

x

x

X

:1

2

J2·TOPVIEW

Pin No.

Function

1, 3, 5, 7

Ground

2

BAI (Bus ACK In)

DMA DAISY CHAIN OPTION

4

BAO (Bus ACK Out)

MOX-FLP2 is designed to allow the option of multiple OMA
boards in the same system. The two signals -- BAI (Bus
Acknowledge In) and BAO (Bus Acknowledge Out) -- which
create the priority OMA daisy chain are implemented by

6

No connection

8

External OMA Request Input

FLP2 STRAPPING LOCATIONS

CONNECTION OF FLP2 TO DISK DRIVE

Figure 5
2-----8

I

J2
1
1-----7

J3

1

1

-------------1

The logic interconnection from FLP2 to the disk drive is
made from J3 on the FLP2 board to the appropriate
connection on the drive. The connection is made with a
standard.1 inch center 50 pin ribbon cable. Refer to Figure

8.
1

',-,-,
1 '

I

'

I

1 ,
J4

1

I ' I

'I "

1 ' ,

12

"I

1

J5

1, ,'

1 ,

I'

I,,!

"I

J8

J9

J6

12

'I
1

1

I "

1

I

!

I"
"
J1Q

"1

J7

I

, 1 21 , 1

'

x 1

1 xl
1

x

1

J12

J11

'1

x 1
1 x I
I x I

1

I

\- - - - - - - - - - - - - - ~ ~ -=..,-- - - _.
\

/

')

Jl

/

1

IVC-6

MDX-FLP2 MULTIPLE DMA BUS PRIORITY
CONNECTIONS
Figure 7

STD BUS CONNECTION

BUSRQ
J1-42
BUSAK
J1-41
MDX-CPU
J1-41

J1·42

J1-41

-- -- -- -- - - t-

-- -

-

MDX-FLP2

MDX-FLP2

BAI
J2-2

N.C.

BAO
J2-4

J1-41

J1·42

BAI
r---- J2-2

- f-

-

BAO
J2-4

J1-42

----MDX·FLP2

BAI
J2·2

-- --

BAO
J2-4

J2 EXTERNAL CONNECTION
HIGHESt PRIORITY

2ND-HIGHEST PRIORITY

3RD-HIGHEST PRIORITY ... ETC.

NOTE: EACH MDX-FLP2 CONTROLLER MUST BE STRAPPED FOR DIFFERENT 1/0 ADDRESS

CABLE CONNECTION PIN DEFINITIONS FOR J3

I/O PORTS

Figure 8

Signal

Description

Pin Number

Drive Select 1,2,3,4
Side Select
Step
Write Data
Write Gate
Direction
Head Load
Track greater than 43
Read Data
Index

Output
Output
Output
Output
Output
Output
Output
Output
Input
Input

Track 00
Write Protect
Drive Ready
2 Sided

Input
Input
Input
Input

26,28,30,32
14,48 (see note)
36
38
40
34
18
2
46
24 (5 in.) or 20
(8 in.)
42
44
22
10

The MDX-FLP2 board occupies a block of eight contiguous
1/0 port addresses. This block of eight can be strapped
anywhere in the main or 10EXP* address space. As shipped
from the factory, the eight ports reside at EOH through E7H
in the main port address space. Figure 9 shows the
utilization of the eight ports.

NOTES:
1. Please compare your drive interface connector prior to hooking up the
MDX-FLP2. Some exclusions to the standard interface are listed below.
2. Some 8" drives have an optional DATA SEPARATOR output on pin 48. If this
is true on your drive, cut the etch on the FLP2 board going to pin 48 on J3.
3. FLP2 board hasJ3 Pin 20 (INDEX8") and J3 pin 24(INDEX 5")tied together.
Pin 20 is used as SECTOR output on some 8" drives. Pin 24 is used as the IN
USE input on some 51,4" drives.
4. Drive SEL4 input is available on some 5%" drives at the FLP2 connection J3
pin 22.
5. J3-12, a no-connect on the FLP2 board, isa disk change status indicator on
some 8" drives.

IVC-7

PORT UTILIZATION ON FLP2
Figure 9
b7

bO

b7

bO

A2-AO

Read

Write

0 0 0

MK3883 OMA Controller IC

MK3883 OMA Controller

0 0 1

Undefined

Not used

0 1 0

XX FB

0 1 1

XX XX XX XX D4 03 02 01

SZ XX XX XX IR

Not used

55

SO Rs XX XX D4 03 02 01

1 0

0

1797 Status Register

1797 Command Register

1 0

1

1797 Track Register

1797 Track Register

1

1

0

1797 Sector Register

1797 Sector Register

1

1

1

1797 Data Register

1797 Data Register

Where:
xx = Don't care
FB = 1 FLP 1 Board; FB =0 FLP2 board
SZ = 1 8 inch drive; SZ =0 5 inch drive
IR = 1 1797 interrupt; IR =0 no 1797 IRQ
55 = 1 2-sided disk; 55 =0 single sided
sri = 1 single density; SO =0 double density

Rs
D4
03
02
01

IVC-8

= 1 1797 active; Rs =0 1797 RESET
= 1 select drive four; D4 =0 no select
= 1 select drive three; 03 =0 no select
= 1 select drive two; 02 =0 no select
= 1 select drive one; 01 =0 no select

!t

COMPUTER
PRODUCTS
DIVISION

UNITED

TECHNOLOGIES
MOSTEK

MDX-SASI*-1

SUMMARY OF MDX-SASI-1 FEATURES
o STD-Z80 Bus compatible

o

Supports Shugart Associates System Interface (SASI*)

o

Polled or interrupt driven

o

Up to 4 MHz operation

o

110 EXP supported

o

External ready output

MDX-SASI-1
Figure 1

o 5 Volt operation

o

Four address 110 port block

o

Auto acknowledge logic

o

Activity LED

•

INTRODUCTION TO MDX-SASI-1
MDX-SASI-1 interfaces the STD-Z80 bus to Shugart
Associates System Interface (SASI). SASI is a universal
systems interface that lets OEMs upgrade, mix, and
interchange peripherals without affecting software. SASI is
an intelligent systems interface, which results in easy
peripheral integration.

At 4 MHz, MDX-SASI-' has a maximum transfer rate of 1
byte/5 ~sec. As a comparison, a double-sided, doubledensity floppy disk has a transfer rate of 1 byte/16 ~sec.
SPECIFICATIONS

MDX-SASI- 1 may be strapped on any four port boundary. In
addition, the 10EXP signal is supported. The board contains
an external READY output. which may be used with an
external DMA board. For example, the external ready output
of MDX-SASI-1 may be connected to the external ready
input of the MDX-FLP2. Thus, the DMA on the MDX-FLP2
may be used with the MDX-SASI-1.

Electrical Spec:ifications
Data Bus:

8 bits, bidirectional

Address Bus:

8 bits (plus optionallOEXP)

SY$lem Bus:

STD-ZSO compatible

MDX-SASI-1 also contains an activity LED. The LED lights
when the board is addressed. This is useful for debugging
both software and hardware.
The board contains auto acknowledge logic. This logic may
be strapped to automatically assert the ACK signal after
reading or writing tolfrom the SASI bus. This allows ari
increase in throughput, since the software does not have to
"bit toggle" the ACK signal.

Inputs:

One 74 LS Load Max

Outputs:

IOH = 15 rnA min at 2.5 V
IOL = 24 mA min at 0.5 V

Interrupts:

MDX-SASI-1 is a low cost, medium performance interface.
*SASI is a trademark of Shugart Associates
IVC-9

Mode 2 Vectored Interrupts
generated. Interrupt vector
programmable upon
initialization. Daisy-chained
interrupt priority.

,

~'.;

;',

"MDX7SASI-1BLOCK DIAGRAM
F.igure2

"

".

50
PIN
1/0
CONNECTOR
DATA

zao PIO
MK3SS1

DATA
DIRECTION
CONTROL

EXT
ROY
LOGIC

EXT ROY

STDzao BUS

,

.

SYSTEM INTER-CONNECTION .DIAGRAM
, ~

Figure 3

CONTROL
UNIT 1

MDX SASIII BOARD

J1

I

I'. ~r''-'''''--I
."

I. . '

CONTROl.l·

I

.UNIT2

I

1-"L------1
1

~

I, ."r, ,'.,
.

'.,

"

-:

STD-Zao ,BUS.

IVC-10

I

'1-------,

CONTROL
UNITS

I

L __. ...,.-l

SPECIFICATIONS CONT.
System Interrupt Units

(S.I.U.) = 1

System Clock:

Upt04 MHz

I/O Addressing:

4 ports on board selectable to
any of 64 four port slots by
jumper options; board may be
placed in main 1/0 space or
expansion 1/0 space (lOEXP)

Power Requirements:

+5 V

Operating Temperature:

O°C to 60°C

± 5% @ .8 A

J5:

Port Select - The board may be placed on any four
port boundary by changing J5. The factory setting is
AOH. The pins on J5 are defined in Figure 4. Note
that a jumper installed gives a logic zero.

J6:

1/0 Expand - 10EXP* is normally not used on
Mostek boards. Thus, the factory straps pins 2 and
3. Ifthe user desires to use the 10EXP*, strap pins 1
and 2; also strap pins 3 and 4.

ADDRESS STRAPPING OPTIONS
Figure 4

max

Address

Corresponding
Pinson J5

A7
A6
AS

1 and 2
3 and4
5 and 6
7 and 8
9 and 10
11 and 12

Mechanical Specifications
Card Dimensions
4.5 in (1 1 .43 cm) high by 6.50 in (16.51 cm) long

A4

0.48 in (1 .22 cm) maximum profile· thickness

A2

A3
NOTE:

0.062 in (.16 cm) printed circuit board thickness

Factory Strapping
1 (not strapped)

o (strapped)

1 (not strapped)

o(strapped)
o (strapped)
o (strapped)

A Jumper Installed gives a logiC zero.

MDX-SASI-1 STRAPPING LOCATIONS
Figure 5

Connectors

STD Bus (J1):

56 pins with. 125 in. centers

SASI Interface:

50 pins with. 1 in. centers

External Ready:

2 pin right angle, .1 in.
centers

•

J3

STRAPPING OPTIONS

1:

.

Figure 5 shows the locations of the strapping options, J2,
J4, JS and J6. The following discussion explains the
purpose of each strap, and how the strap is set at the
factory.
J2:

2 I

IVC-11

I

,

External Ready Output (J2 pin 2) - This is an active
high signal which may be connected to an external
DMA board. External Ready goes HIGH when the
REO (request) signal goes low, which signals that
data is available on the SASI data bus. Clearing of
External Ready occurs by reading from the MDXSASI-1 data port (port 0). Note that pin 2 is the
External Ready Output, while pin 1 is ground.
Auto Acknowledge Enable - The factory straps J4
to enable the Auto Acknowledge logic. This results
in the SASI ACK signal being automatically
asserted when a read or write occu rs from the data
port (port 0); the ACK signal is cleared when the
SASI REO signal is deasserted. The auto
acknowledge feature allows a higher throughput
on the SASI bus, since the programmer does not
have to "toggle" the SASI ACK signal. If Auto
Acknowledge is not desired -- for example to debug
a controller board _. remove J4.

I

,

J4

1,
3'

,

51
71

,

91

1:

.

111

2

J5

,
I

x

:

X

I

31 )(
4 I

•

,
J4:

x
x

x

,
I

I

1

J,6

1
1
1

I
I

\-----------------------------1
,
I

\
\

J1

I

CONNECTION TO THE SASI BUS

PORT UTILIZATION

Figure 6 shows the pin definitions of J3, the 50 pin
connector for connecting the MDX-SASI-1 to the SASI bus.
Note that the SASI bus is divided into a data section and a
control section. All but two of the SASI bus signals are
supported by MDX-SASI-1. The data bus parity bit is not
supported by MDX-SASI-1. Also, ATN (attention) is not
suppported.

Figure 7

AO

0

0

PIO PortA Data (SASI Data Signals)

0

1

PIO Port B Data (SASI Control Signals)

1

0

PIO Port A Control Register

1

1

PIO Port B Control Register

To connect MDX-SASI-1 to the SASI bus, connect a 50 pin
cable from J3 on the MDX-SASI-1 board to the required
connector on the SASI controller board.

Read/Write

STD BUS CONNECTOR (J1)

PROGRAMMING NOTES

The STD Bus Connector is a standard 56 pin card edge
connector.. See STD-Z80 Bus Specification 4420094.

REFERENCE INFORMATION

I/O PORTS
The MDX-SASI-1 board occupies a block offour contiguol!s
I/O port addresses. The block of four can be strapped
anywhere in the main or 10EXP* address space. As shipped
from the factory, the four main ports reside at AO hex
through A3 hex in the main port address space. Figure 7
shows the utilization of the four ports.

lBO Data Book
lBO. Programming Manual
P10Dafa Sheet
MOS/SO USers' Manual
SASI Bus Specification - Preliminary

J3 CONNECTIONS
Figure 6

Pin No.
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32

34
36
38

40
42
44

46
48
50
NOTE:

Signal
DBO (data
DB 1 (data
Da2 (data
DB3 (data
DB4 (data

bit 0, LSB)
bit 1)
bit 2)
bit 3)
bit 4)
SASI Data Bus

lJ

Des ( - b;' 5)
DB6 (data bit 6)
DB7 (data bit 7, MSB)
Not used (data bus parity)
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used (ATN, attention)
BSY(busy)
ACK (acknowledge)
RST(reset)
MSG (message)
SASI Control Bus
SEL (select)
C/O (control/data)
REO (request)
I/O (input/output)

l

All odd pins are ground.

.

A1

J

IVC-12

PORT UTILIZATION ON MOX-SASI-1
Figura 8

Status Control Port Definitions (Port B on PIO):
b7
RES

b6
SEL

b5
ACK

b4
BSY

b3
MSG

b2

b1

bO

C/O

REO

I/O

Input/Output (input)
Request (input)
Control/Data (input)
Message (input)
Busy (input)
Acknowledge (input)
Select (output)
Reset (output

Note that Port B is programmed for BIT CONTROL MODE.
Bits bO-b5 are configured for inputs while b7 and b6 are
outputs.

IVC-13

IVC-14

IJ

UNITED
TECHNOLOGIES
MOSTEK

COMPUTER
PRODUCTS
DIVISION
MDX-SASI-2

SUMMARY OF MDX-SASI-2 FEATURES

MDX-SASI-2
Figure 1

o STD-Z80 Bus Compatible

o

5 Volt Operation

o

Supports Shugart Associates System Interface (SASI)*

o

Polled or Interrupt Driven

o

Mode 2 Interrupt Capability

o

2.5 to 4 MHz Operation

o

Eight Address I/O Port Block

o

I/O EXP Supported

o

Auto Acknowledge Logic

DOn-Board DMA Controller

o

External DMA Request Supported

o

DMA Daisy Chain Supported

o

External Wait Request Supported

operation. If finer control is required for debugging
purposes, the auto acknowledge can be disabled.

DESCRIPTION
The MDX-SASI-2 interfaces the STD-Z80 Bus to Shugart
Associates System Interface (SASI). SASI is a universal
systems interface that lets OEMs upgrade, mix, and
interchange peripherals without affecting software. SASI is
an intelligent systems interface, which results in easy
peripheral integration.
MDX-SASI-2 addressing may be strapped for any eight port
boundary in the STD-Z80 I/O space. In addition, the /IOEXP
signal is supported for maximum configuration flexibility.
The board contains an on-board DMA controller for
increased throughput. An external request input allows
other boards in the system to use this controller as well. The
STD-Z80 /WAITRQ signal can be used to speed-match the
DMA to slower memories, and DMA daisy-chaining is
provided for via an additional connector.
The board also contains auto acknowledge logic. This
strapping option provides automatic handshaking for SASI
information transfers, and is essential to the board's DMA
*SASI is a trademark of Shugart Associates.

MDX-SASI-2 is a medium cost, high performance interface.
At 4 MHz, MDX-SASI-2 has a maximum transfer rate of
570 Kbytes/sec. In comparison, a double-sided, doubledensity floppy disk has a transfer rate of 62.5 Kbytes/sec.

SPECIFICATIONS
Electrical Specifications
System Bus:

STD-Z80 Compatible

Inputs:
Outputs:

Interrupts:

One 74 LS Load Max
IOH = 15 mA min at 2.5 V
IOL =24 mA min at 0.5 V

Mode 2 Vectored Interrupts generated. Interrupt vector programmable upon initialization.
Daisy-chained interrupt priority.

System Interrupt Units (S.I.U.) = 2
System Clock:

IVC-15

2.5 t04 MHz

SYSTEM INTER-CONNECTION DIAGRAM
Figure 2

MDX-SASI-2
BOARD

CONTROL
UNIT 1
I

I
I

r------,

I

I

~
I:
I

I

•

I
I

I

."
•

I

I:
W

I

I

.. -------~

I

I

CONTROL:
UNIT 2
I

•

r--~---,

I

I

I

I

:

CONTROL
UNITS

I

I

I
I
I'- _ _ _ _ _ _ .JI

STD-ZSOBUS

1/0 Addressing:

8 ports on board selectable to any of 32
eight port slots by jumper options; board
may be placed in main 1/0 space or
expansion 1/0 space (lIOEXP)

Shrouded 2 x 2S, 0.02S" square pins;
0.1 inch centers, right angle
Mating connectors:
Winchester 51-1150
Berg 65485-022

+S V ± S% @ 1.1 A max

Power Requirements:

STRAPPING OPTIONS
Operating Temperature:

O°C to 60°C
Figure 4 shows the location of the strapping optionsJ4, JS,
J6, and J7. The following discussion gives the purpose of
each strap and how the strap is set at the factory.

Mechanical Specifications
Card Dimensions

J4:

IEXT REO Level cThis jumper determines whether
the IEXT REO input to MDX-SASI-2 is active low or
active high. For an active high IEXT REO, strap pins
1 and 2; for an active low IEXT REO, strap pins 2
and 3 (factory setting).

JS:

Auto Acknowledge Enable - The factory straps J5
to enable the Auto Acknowledge logic. This circuit
will carry out the SASI bus handshake on
information transfers without requiring the CPU to
bit toggle control lines (SASI ACK). JS must be
strapped if DMA operation is desired. If the user
needs to explicitly bit toggle the SASI ACK line
--e.g. to debug a contoller board -- the JSstrap
should be. removed.

J6:

Port Select - The board may be placed on any eight
port boundary by changing J6. The factory setting is
port AOH, for compatibility with Mostek's M/OS80 Flexible Disk Operating System (see reference
section), The pins on J6 are defined in Figure S.
Note that a strap installed implies a logic zero.

4.5 in (11.43 cm) high by 6.S0 in (16.51 cm) long
0.48 in (1.22 cm) maximum profile thickness
0.062 in. (.16 cm) printed circuit board thickness
Connectors
J1 - STD-Bus:
S6 pin dual readout edge connector;
0.1 25 iii. centers
Mating connectors:
PCB - Viking 3VH28/1 CES
WIW - Viking 3VH28/1CNDS
SDR LUG - Viking 3VH28/1 CN5
J2 - External Ready I DMA Daisy Chain:
2 x 4, 0.02S" square pins;
0.1 inch.centers, right angle
J3 - SASI Interface:
IVC-16

DIS:

~

en

l>
~

N

STD-Z80
BUS
~

J1

~
A

t..

\
V
~(

DATA
BUFFERS

tA

V

I\.,

I\.

\

vi

ADDRESS
BUFFERS

t
<:

...
"

C!

vi-

J..

\

f'.r---V

CONTROL
BUFFERS

+J

VL

DMA

[\s

-\

[\r

vi

11'--\
PORTA

~

PIO

Vt

rI -

I'r -

r-

-\

vi

PORTB

STATUS/CNT~,/\

~

""

II

~

r

,

t

L

IEXTREQ
(J21

j
BUSAK
LOGIC

vi

AUTO
ACK
LOGIC

READY
LOGIC

rBAI
(J21
BAO

IRQ
LOGIC

+

~

II

\

DATA

J\DRIVERS
AND
I\STATUS/CN-/
RECEIVERS

r7
I--

1\

IY-

I-

PORT
DECODE
LOGIC

VA

vt--

VL rl\r
t-

t.. r - DRIVERS
AND
RECEIVERS

DIRECTION
CONTROL

ROY

t..

"'7
DIRECTION
CONTROL

l;t

i

I

~

1/0 Expand - This jumper allows the IIOEXP lineto'
be included or ignored in the address dec9ding of
MDX-SASI-2. Strapping pins 2 and 3 causes
IIOEXP to be ignored (factory setting). If a given
board is to be selected on IIOEXP =0, strap pins 1
and 2, then pins 3 and 4. To cause board selection
when IIOEXP = 1, strap pins 1 and 2 only.

J7:

MDX-SASI-2 BOARD OUTLINE AND HEADER
LOCATIONS
Figure 4

J3

Multiple DMA Option
MDX-SASI-2 is designed to support the operation of
multiple DMA devices in a system. Two signals -- BAI (Bus
Acknowledge In) and BAD (Bus Acknowledge Out) -provide for the connection of a priority DMA daisy chain.
Figure 6 shows their locations on connector J2. As an
example, suppose a system requires the use of four MDXSASI-2 boards. As shown in Figure 7, the highest priority
board would be DMA device 1, while the lowest priority
board would be DMA device 4. Thus, MDX-SASI-2 boards
are prioritized for multiple DMA operation by their electrical
position in a system, as determined by their J2
interconnections, Typically, twisted pairs (signal + ground)
are used to connect the bus priority chain.

,H,

Pin 8 of J2 provides an external request input (/EXT REO),
whereby other STD-Z80 I/O cards without on-board DMA
capability can 'borrow' it from MDX~SASI-2. This is done by
feeding a card's DMA request signal through IEXT REO to
the READY pin of the MK3883 Z80-DMA chip on MDXSASI-2. IEXT REO can be active low or active high (strap
J4).

J6

[Y7

J2 CONNECTOR PIN DEFINITIONS
Figure 6

J1

BOARD

:I:

ADDRESS STRAPPING OPTIONS
Figure 5

x

x

x

x

J2-TOPVIEW

Address
A3
A4
A5
A6
A7

Corresponding
PinsonJ6
1 and 2
3 and4
5 and6
7 and 8
9 and'1Q

Factory Setting (AOH)
strapped
strapped
not strapped
strapped
not strapped

(0)
(0)
(1)
(0)
(1 )

IVC-18

Pin No.

Function

1,3,5,7

Ground

2

BAI (Bus ACK In)

4

BAD (Bus ACK Out)

6

No connection

8

External DMA Request Input
(/EXT REO)

CONNECTION OF DMA DAISY CHAIN
Figure 7
J1-42

J1-41

IBUSRQ

IBUSAK

MDX-CPU

1

2

3

4

J1-41 J1-42

J1-41 J1-42

J1-41 J1-42

J1-41 J1-42

J2-2

J2-4

J2-2

J2-2

BAI

BAD

BAI
BAD
MDX-SASI-2

N.C.- J2-2

J2-4

BAI
BAD
MDX-SASI-2

MDX-SASI-2

J2-4

J2-4

-

BAD
BAI
MDX-SASI-2

HIGHEST _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..... LOWEST
PRIORITY

PRIORITY

CONNECTION TO THE SASI BUS
Pin. No.
The following shows the pin definitions of J3, the 50 pin
connector to the SASI bus. Note that the SASI bus is divided
into a data section and a control section. Except for the data
bus parity line (pin 18) and the ATN (attention) line (pin 34).
MDX-SASI-2 fully supports the SASI bus. Parity is a SASI
bus option while ATN is not widely used by SASI peripheral
controllers.
NOTE: All odd pins are ground.

IVC-19

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

II

Signal
DBO (data bit 0, LSB)
DB1 (data bit 1)
DB2 (data bit 2)
DB3 (data bit 3)
DB4 (data bit 4)
DB5 (data bit 5)
.DB6 (data bit 6)
DB7 (data bit 7, MSB)
Not used (data bus parity)
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used (ATN, attention)
BSY (busy)
ACK (acknowledge)
RST (reset)
MSG (message)
SEL (select)
C/D (control/data)
REQ (request)
I/O (input/output)

SASI Data Bus

SASI Control Bus

Programmer's Model of MDX-SASI-2
beginning on any 8-byte boundary as strapped by the user.
This is illustrated in the table below.

MDX-SASI-2 is compatible with any STD-ZaO bus system.
The board consumes eight contiguous I/O port locations,

Function

A7

A6

A5

A4

A3

A2

A1

X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X

0
0
0
0

0
0

0 PIO Port A Data (Bidirectional)

1
1

0 PIO Port A Control

1
1
1
1

0
0

0 DMA Controller

1
1

0 Reserved

Where X
Board.

= Port

AO

1 PIO Port B Data (Bit Control M ode)
1 PIO Port B Control
1 Reserved
1 Reserved

Strapping options on the MDX-SASI-2

PIO Port A Data is used as a bidirectional data port. It is
connected in hardware to the data portion of the SASI bus.
PIO Port B Data is used in bit control mode in order to

implement the control portion of the SASI bus. The bit
definitions of these two ports are shown below.

SASI Data Port Definitions (PIO Port A):
a7

a6

a5

a4

a3

a2

al

aO

DB7

DB6

DB5

DB4

DB3

DB2

DBl

DBO

SASI Control Port Definitions (PIO Port B):
b7

b6

b5

b4

b3

b2

bl

bO

RES

SEL

ACK

BSY

MSG

C/O

REO

I/O

IL::==
I

Input/Output (input)
Request (input)
'--_ _ _ _ _ _ _ _ Control/Data (input)
'--_ _ _ _ _ _ _ _ _ _ Message (input)
'--_ _ _ _ _ _ _ _ _ _ _ _ _ Busy (input)
1..-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Acknowledge (input or

I

1..-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

Note that if auto ack is strapped for use, then b5 on the PIO
should be programmed as an input. If auto ack is disabled,
b5 should be programmed as an output.

IVC-20

output)
Select (output)
Reset (output)

STD-Z80 Bus Signals Used by MDX-SASI-2
not used by MDX-SASI-2. The signals are accessed via J1, a
56 pin PC edge connector.

The following is a list of STD-Z80 Bus signals used by the
MDX-SASI-2 board. Pin numbers without a description are
Pin Mnemonic Description
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55

+5
GND

5 VDC system power
System Ground

03
02
01
DO
A7
A6
A5
A4
A2
A1
AO
IWR
IIORO
IIOEXP

Data bit 3
Data bit 2
Data bit 1
Data bit 0
Address bit 7
Address bit 6
Address bit 5
Address bit 4
Address bit 3
Address bit 2
Address bit 1
Address bit 0
Write
10 Request
10 Expand

IM1
IBUSAK
IINTAK
IWAITRO
ISYSRST
ICLOCK
PCO

Machine Cycle
Bus Acknowledge
Interrupt Acknowledge
Wait Request
System Reset
System Clock
Priority Chain Out

A3

Pin Mnemonic Description
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38

+5
GND

5 VDC system power
System Ground

07
06
05
D4

Data
Data
Data
Data

IRD

Read

bit 7
bit 6
bit 5
bit 4

40
42 IBUSRO
44 IINTRO
46
48
50
52 PCI
54
56

Bus Request
Interrupt Request

Priority Chain In

REFERENCES
System Design Using the Mostek STD-Zao Bus
-- Publication No. 4420237
Mostek 1982/1983 Microelectronic Data Book

M/OS-80 Flexible Disk Operating System - Operation Manual
-- Publication No. 4420064
ORDERING INFORMATION

DESIGNATOR

DESCRIPTION

PART NO.

MDX-SASI2

SASI2 module (including Technical Manual)

MK77679

MDX-SASI2
Technical Manual

SASI2 Technical Manual only

4420346

IVC-21

IVC-22

IJ

UNITED

COMPUTER
PRODUCTS
DIVISION

TECHNOLOGIES
MOSTEK

MDX-488

processor, memory, a DMA controller, and hardware to
implement the full IEEE 488 specification for Talker,
Listener, and Controller. When used as GPIB controller in
multicontroller systems, the MDX-488 can be restricted
from being the system controller.

FEATURES

o IEEE 488- 1978 INTERFACE (GPIB)

o

Performs all functions of Talker, Listener, and Controller

o

Onboard Z-80 for local intelligence

o

Two BYTEWYDETM sockets for ROM/RAM

o

GPIB data rates of up to 400K bytes per second using
onboard DMA

1 SIU

STD-Z80 Bus compatable

Operating Temperature:

ELECTRICAL SPECIFICATIONS
STD-Z80 Bus Compatable
System Interrupt Units:

o

MDX-488 DESCRIPTION
The MDX-488 is an intelligent STD-Z80 module designed to
simplify the implementation of the IEEE 488 General
Purpose Interface Bus. The board has a Z-80 micro-

Power Supply Requirements:
+5VDC

IVC-23

•

IVC.-24

·
II

UNITED
TECHNOLOGIES
MOSTEK

COMPUTER
PRODUCTS
DIVISION
MDX-ISIO

FEATURES

o

STD-ZaO Bus compatible

o

On-board processor

DOn-board DMA controller for intra- and inter-bus data
transfers
o Two BYTEWYDETM memory sockets

o

Inter-bus command transfer via a two port register array

o

Two serial channels

o

Multi-mode operation:
- Full- and half-duplex operation
- Synchronous and Asynchronous modes
- Standard Baud rates to 19.2 K Baud

to the STD-ZaO bus as a block of 1/0 mapped registers.
Commands, command parameters, and status information
may be passed between the STD-ZaO bus and the LIB
through these registers. The on-board DMA controller may
be used for transferring data between the serial
communications controller and the local memory in a high
speed communications link (intra-bus transfer), or for
transferring data between the local memory and STD-Zao
system memory (inter-bus transfer).
The architecture of the MDX-ISIO allows the user to
implement any level of control through his firmware and
software. As a minimum, the local processor may be used to
initialize the on-board components and take care of "house
keeping" tasks. At the other extreme, the user might
implement a high level algorithmic controller for the . . . .
industrial environment.

IIiIiiiI

ELECTRICAL SPECIFICATIONS
STD-Z80 Bus Compatible

o

Multi-protocol support

o

Supports all zao interrupt modes

System Interrupt Units:

1 SIU
o Self-test capability with LED indicator
Operating Temperature Range:
MDX-ISIO DESCRIPTION
The MDX-ISIO is a general purpose intelligent STD-ZaO
module designed to simplify the implementation of serial
communications networks. The board contains a microprocessor and required support hardware, a DMA
controller, and a two port serial communications controller.
The local processor and its support components make up
the Local Intelligence Bus (LIB). The MDX-ISIO will appear

Power Supply Requirements:
+5 Volts
+12 Volts
-12 Volts

IVC-25

IVC-26

UNITED

~ TECHNOLOGIES

COMPUTER
PRODUCTS
DIVISION

MOSTEK

MDX-SI02

FEATURES

MDX-SI02
Figure 1

o

Two independent full-duplex channels

o

Independent programmable Baud rate clocks

o

Asynchronous data rates, 12.5 to 19.2K bits per second

o

Receiver data registers quadruply buffered

o

Transmitter double buffered

o Asynchronous operation
o Binary synchronous operation
o HDLC or SDLC operation
o Both CRC-16 and CRC-CCITT (-0 and -1) hardware
implemented
o Modem control
o Configurable as DTE or DCE
o Serial input and output as either RS-232 or 20mA
current loop
o Current loop optically isolated
o Current loop selectable for either active or passive mode
o Address programmable
o Compatible with STD-Z80 Bus

GENERAL DESCRIPTION
The Serial Input Output Module, MDX-SI02, is designed to
be a multiprotocol asynchronous or synchronous I/O
module for the STD-Z80 Bus. The module is designed
around the Mostek MK3887 Z80-S10 which provides two
full duplex serial data channels. Each channel has an
increase module flexibility. Both channels are capable of
handling asynchronous, synchronous, and synchronous
bit-oriented protocols such as BISYNC, SDLC, HDLC, and
virtually any other serial protocol.
The MK3887 can generate and check CRC codes in any

synchronous mode and can be programmed by the CPU for
any traditional asynchronous format. The serial input and
output is fully buffered and is provided at the connector as
either 20mA current loop or RS-232-C levels. A modem
control section is also provided for handshaking and status.
The MDX-SI02 module can be jumper-configured as a Data
Terminal (DTE) or as a modem (DEC) in order to facilitate a
variety of interface configurations.
Figure 2 is a block diagram of the MDX-SI02 module. It
consists of five main elements. They are the channelconfiguration headers, line drivers and receivers, MK3887
Z80-SIO, programmable Baud rate generator, and addressdecode and data-bus buffers. Input and output to the board
is provided via two 26-pin connectors. One connector is
dedicated for each channel.
Several features are available as options that are selected
via the channel-configuration headers. The headers are
used to select the orientation of the data communication
interface or the mode of the 20mA current loop. The MDXSI02 can be selected to act as either a terminal or processor
(Data Terminal Equipment DTE) or as a modem (Data
Communications Equipment DCE). The header allows

IVC-27

i~
c 0
iI 0

N~

·0

~

MODEM

PORTCONFIGURATION
HEADERS

cn
RS-232
RECEIVERSI
DRIVERS

CHANNEL A
RS-232 DATA
AND
MODEM CONTROL

io

."

s::

~

en

o
N

20mA
LOOP

<:

o

N

CO

STD-ZBO
BUS

20mASERIAL
,~/'NPUT/OUTPUT

ADDRESS
DECODE
AND
DATA-BUS

CHANNEL B

20mA
LOOP

RS-232
RECEIVERSI
DRIVERS

20mASERIAL
,~/'NPUT/OUTPUT

RS-232 DATA
AND
~_ _ _~, \,----,{MODEM CONTROL
PORTCONFIGURATION
HEADERS

J1 AND J2 CONNECTOR PINOUT
Table 1

PIN
1
2
3
4
5
6
7
8
12

DESCRIPTION

PIN

DESCRIPTION

Protective Ground (AA)
Transmitted Data (BA)
Received Data (BB)
Request To Send (CA)
Clear To Send (CB)
D.ata Set Ready (CC)
Signal GND (AB)
Carrier Detect (CF)
RX-(20mA Loop)

13
15
17
20
22
24

TX + (20mA Loop)
Transmission Signal Element Timing (DCE Source)
Receive Signal Timing Elel11ent (DCE Source)
Data Terminal Ready (CD)
Polarization Pin
RX+ (20mA Loop) or Transmission Signal Element
Timing (DTE Source) (DA)
TX- (20mA Loop)
Polarization Pin

25
26

configuration of both data interchange and modem control
signals. This allows the increased flexibility necessary to
link different hardware elements in OEM datalink systems
and networks. The module is shipped from the factory wired
as a DCE interface.

Binary Synchronous operation
Internal or external character synchronization
One or two Sync characters in separate registers
Automatic Sync character insertion
CRC generation and checking

The MDX-SI02 has different selectable options for the
20mA current loop. The receiver and transmitter input and
output lines can be reconfigured on the modules to allow
reorientation of these signals. Also, the receive and
transmit circuits can be selected to function in either an
active or passive mode. In the active mode, the MDX-SI02
module provides the 20mA current source. In the passive
mode, the module requires that the loop current be
provided. The latter is the same mode as that of a teletype.

HDLC or SDLC operation
Automatic Zero insertion and deletion
Automatic Flag
Address-field recognition
I-Field reSidue handling
Valid receive messages protected from overrun
CRC generation and checking

An EIA and 20mA current loop interface circuit is used to
provide the necessary level shifting and signal conditioning
between the MK3887 Z80-SIO and the connector. These
line drivers and receivers provide the current electrical
signal levels, slew rate, and impedance for interfacing
RS-232-C and 20mA current loop peripherals. Additionally,
optical isolation is provided for both transmit and receive
circuits in the 20mA current loop mode.
The Mostek MK3887 Z80-SIO is the central element of this
module. This device is a multifunction component designed
to satisfy a wide variety of serial data communications
requirements in microcomputer systems. Its basic role is
that of a serial-to-parallel, parallel-to-serial converter/
controller. But within that role it is configured by software
programming so that its function can be optimized for a
given serial data communication application. The MK3887
provides two independent full-duplex channels, designated
A and B. Each channel features the following:
Asynchronous operation
5, 6, 7, or 8 bits/character
1, 1Y2, or 2 stop bits
Even, odd, or no parity
X1, X16, X32, and X64 clock modes
Break generation and detection
Parity; Overrun and Framing-error detection

The MK3887 also provides modem control inputs and
outputs as well as daisy-chain, priority-interrupt logic. Eight
different interrupt vectors can be generated by the MK3887
in response to various conditions affecting the data
communications channel transmission and reception. For
more information concerning the MK3887, see the
MK3887 Technical Manual in the 1982-1983 Microcomputer Components Designers' Guide.
Address decoding, STD-Z80 Bus interface, and bus
management for the module is performed by the Address
Decode and Data Bus circuit. The MDX-SI02 contains
command registers that are programmed to select the
desired operational mode. The addressing scheme is as
follows:

XXXXXX 00 Channel A Data

XXXXXX 01 Channel A Command/Status
XXXXXX 10 Channel B Data
XXXXXX 11 Channel B Command/Status

The XXXXXX indicates the binary code necessary to
represent which of 64 starting port addresses is selected.
Each channel has an individual programmable Baud rate
generator. The X1 multiplier on the MK3887 muSt be used
in the synchronous modes. The X16, X32, or x64 MK3887
clock rate can be specified for asynchronous modes.
IVC-29

II

clocking signals on particular input pins to determine the
bit/Baud r a t e . ·
.

STRAPPING OPTIONS
Table 2 shows the strapping for different configurations of
the RS-232 and 20mA loop interface. When the board is
interfacing to a CRT or TTY, it should be strapped as DCE
(Data Communications Equipment). The 20mA loop can be
configured to sink or source current in addition to the ability
to be DCE or DTE. Ports should not be strapped for both
RS-232 and 20mA loop. Strapping both could result in
circuit damage and erroneous data reception. The strapping
is shown for port A; however, port B straps are identical
except for the numbering of jumpers.
STRAPPING FOR J3 OR J4
Table 2

TYPE OF PORT
RS-232 DCE (J3 and J4 as shipped)

JUMPERS
1-2
13-20
15-22
11-18
17-12
21-14
19-16

RS-232DTE

11-12
13-16
15-14
17-18
19-20
21-22

20mA Source-Loop DTE

23-24
25-26
27-28
29-30

20mA Source-Loop DCE

23-26
25-24
27-30
29-28

20mA Sink-Loop DTE

23-30
25-28
27-26
29-24

20mA Sink-Loop DCE

23-28
25-30
27-24
29-26

ASYNCHRONOUS CLOCKING
When a channel of the SIO is used for asynchronous
communication, it is programmed for 16X clocking.
Clocking is provided by the jumper-programmable BaudRate Generator. The rates for which the Baud-Rate
Generator can be programmed (see Table 3) represent 16X
multiples of commonly used communications Baud rates.
For the Transmit side of an SIO channel, each serial bit is
clocked out by every 16th transition on the clocking input.
For the Receive, the clocking signal does not clock the data
in itself, in the sense of being synchronized to it, but merely
provides a framework in which transitions on the input data
are considered. Thus, if an SIO channel is used for 16X
asynchronous communications, and the Transmit and
Receive Baud rates are the same (the typical case), there is
no reason why the channel's Transmit and Receive clock
input pins should not both be connected to the same output
of the Baud-Rate Generator.
SYNCHRONOUS CLOCKING
EIA Standard RS-232-C defines the interface between a
business machine (e.g. a computer), termed Data Terminal
Equipment (DTE), and a piece of communications
equipment (e.g. a modem), termed Data Communications
Equipment (DCE). Within RS-232, the terms "Receive(d)"
and "Transmit(ted)" are referenced to the DTE, so that the
"Received Data" signal is provided by the DCE to the DTE,
while the "Transmitted Data" signal is provided by the DTE
to the DCE. In a synchronous environment, clocking
information is in some way carried from one end of the link
to the other. The "Receive Clock" signal (RS-232-C
designation DO) is always provided by the DCE to the DTE,
along with the data; each transition from RS-232 positive to
negative voltage (SIO TTL ground to positive) serves to clock
the Received Data signal into the DTE. Transmit clocking
can be provided from either DCE to DTE, or vice versa.
Separate connector pins/signals are provided depending
on the direction: RS-232 designation DB is used for a
Transmit Clock provided by the DCE to the DTE, whereas
designation DA is used for a DTE-sourced Transmit Clock.
Whichever the source, the negative-to-positive transition
on the RS-232 signal is used by the DTE to change the data;
the opposite transition is used by the DCE to sample it.
As noted previously, the MDX-SI02 board can act as DTE or
DCE; in each case it can also source or receive the Transmit
Clock signal. For synchronous communication, the SIO chip
always operates at a 1X clock rate, acting on transitions in
the clocking signal(s) as described above.

CLOCK CONFIGURATION STRAPPING
Each channel of the SIO chip used must be provided with

When the MDX-SI02 card sources an RS-232-C clock, it is
from one of the outputs of the Baud-Rate Generator. The

IVC-30

BAUD RATE (Hz) PROGRAMMABILITY
Table 3

FREQUENCY
CODE

D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

C
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

SYNCHRONOUS

A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

ASYNCHRONOUS

X32
25
37.5
55
67.25
75
150
300
600
900
1000
1200
1800
2400
3600
4800
9600

X16
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200

X1
800
1200
1760
2152
2400
4800
9600
19200
28800
32000
38400
57600
76800
115200
153600
307200

X64
12.5
18.75
27.50
33.63
37.50
75
150
300
450
500
600
900
1200
1800
2400
4800

NOTE:
Current loop applications above 9600 Baud are not recommended

Strap = 0
No Strap = 1

transfer rates provided are commonly used for synchronous
communication (1200, 2400, 4800, 9600, 19200). These
rates are selectable from the X1 column of Table 3.

JUMPERS FOR BAUD-RATE GENERATOR
FREQUENCIES
The clock frequencies for fT and fR are selected with straps
on J8 as follows:

Pins

Channel A

Pins

ChannelB

7-8
5-6
3-4
1-2

LSB - A fR
B fR
CfR
MSB - D fR

15-16
13-14
11-12
9-10

LSB - A fT
B fT
C fT
MSB - D fT

JUMPERS FOR CONNECTION OF BAUD-RATEGENERATOR OUTPUTS TO SIO INPUTS

PINS
1-2
3-4

Connects fr to TRANSMIT CLOCK PORT A
Connects fr to RECEIVE CLOCK PORT A

Connects f t to TRANSMIT CLOCK PORT B
Connects f t to RECEIVE CLOCK PORT B
Connects fr to TRANSMIT CLOCK PORT B
Connects fr to RECEIVE CLOCK PORT B
Connects f t to TRANSMIT CLOCK PORT A
Connects f t to RECEIVE CLOCK PORT A

These straps are found on J7. Figures 3 thru 9 illustrate the
use of these jumpers. Figure 10 is a worksheet useable
during board configuration.
CONNECTION OF RS-232 SYNCHRONOUS CLOCK
SIGNALS DA. DB. DO TO SIO INPUTS

For frequencies selected refer to Table 3.

The clock configuration straps are defined as follows:

5-6
7-8
2-5
4-7
1-6
3-6

The RS-232 DTE-supplied Transmit Clock signal DA shares
the connector pin assignment of current loop signal RX+
(Port A = J1 pin 24 to J3 pins 28, 10; Port B = J2-24 to
J4-28, 10). The DCE-supplied Transmit Clock signal DB is
brought out from J1-15 to J3-8 (PortA) and J2-15 to J4-8
(Port B), and the (always DCE-supplied) Receive Clock DD
from J1-17 to J3-6 (Port A) and J2-17 to J4-6 (Port B).
Connections for synchronous clocking are made from pins
of J7 (which connect to the SIO clock inputs) to one side of
an EIA driver or receiver. The other side of the driver or
receiver is then connected to one of the clocks DA. DB, or
DD. Various cases of such connections are presented in the
following examples.

IVC-31

II

BOTH PORTS ASYNCHRONOUS
Figura 3

J7

2
fR

1

-

4
6

U10

fT

1

~

8

(BAUD-RATE
GENERATOR)

-

14
10

~

16

1

14

3

13

5

27

7

28

TXCA
RXCA
TXCB
U4

RXCB

(SIO)

13
9

0- I - 15

12

0- ~

75189

~
6

(PORTA
CONNECTOR)

J3
9

4

75189
U1
13
11

3

5

75189
U1
3

-

1

0- ~

ro

J1

28

24

6

17

8

15

~

7

75189
8 U1 10
75188

9

~8
10 U5 ./75188

--fi{-\}
13

PORT. A
Asynchronous
DTE or DeE
RCV&XMIT@ Rate fR

NOTE:

1

10

0- -

J2

3

28

24

5

6

17

7

8

15

U5

--"

PORT B
Asynchronous
DTE or DCE
RCV&XMIT @ Rate IT

This configuration is suitable for J1-to-J2Ioopback testing if tr = fRo

DO
DB
(PORT B
CONNECTOR)

J4

~

DA/RX+

DA/RX+

DO

DB

PORT A: SYNCHRONOUS. OTE. XMIT CLOCK
FROM OCE
PORTB:ASYNCHRONOUS
Figure 4

J7

2

fR~________~1~_4-r~

__

0-~1______________~1~4 TXCA

;:o-~3~____________~1~3 RXCA

r-~6~~ ,~;"J:J:~~5~____________~2~7~TXCB

U10

lo-t...:..7 _ _ _ _ _-..;2""i8

fT .--_ _ _ _..
1>--..::8f---j/Lf--;

(BAUD-RATE
GENERATOR)

r----------:-;t-

28

24

5

6

17

7

8

15

75189
U1
10
8
9

(PORTA
CONNECTOR)

J3

DB

0- ~

9

J2

75188
3 -"

~

28

24

--../

5

7

Synchronous
DTE
DCE Supplies XMIT Clock
RCV & XMIT Rate External,
Independent

DO

(PORT B
CONNECTOR)

J4

8

~11
13 U5

PORTA

DA/RX+

PORTB
Asynchronous
DCE or DTE
RCV & XMIT @ Rate IT

IVC-33

~

~

DA/RX+

6

17 DO

8

16

DB

•

PORT A: SYNCHRONOUS. DTE. XMIT CLOCK
PROVIDED TO DCE
PORTB:ASYNCHRONOUS
Figure 5

J7

2

1

IR

U10

4

6~

1

IT

Y

8

(BAUD-RATE
GENERATOR)

i~

14
10

-v

14

3

13

5

27

7

28

.....

12

0-

6

RXCA
TXCB
U4

RXCB

(SIO)

13
9

15

r!!-

75189

~

TXCA

0- t - -

16

'.'~ "

;:

1

(PORTA
CONNECTOR)

J3
9

4

0-

~

J1

75189

11

U1 13

3

3

28

24

5

6

17

7

8

15

r--

~

75189
U1
1

75189
8 U1 10
75188
10

DB

10

0- t--

J2

3

28

5

6

17 DO

7

8

15

24

~

Synchronous
DTE
XMIT CLOCK SUPPLIED TO DCE
XMIT Rate @ IR
RCV Rate External

DO

U5 /875188

---@"11
13 U5

PORTA

DA/RX+

(PORT 8
CONNECTOR)

J4
·9

~

f-o

PORT 8
Asynchronous
DTE or DCE
RCV&XMIT @ Rate IT

IVC-34

DA/RX+

DB

PORT A: SYNCHRONOUS, DCE, XMIT CLOCK
FROM DTE
PORTB:ASYNCHRONOUS
Figure 6

J7

2

1

fR

4

~

6
Ul0

1

fT

8

(BAUD-RATE
GENERATOR)

'\

14
~

10

1

14

3

13

5

27

7

28

TXCB
U4

RXCB

(SIO)

13

0- ~

~

16

15

12

0- .!.!.....

~

75189

~
6

(PORT A
CONNECTOR)

J3
4

9

10
Jl

75189
Ul
13
11

3

TXCA
RXCA

75189
Ul

3

r--5

1

28

f-o
"

"

7

24

6

17

8

15

75189
8 Ul 10

-12~11

~

7

PORTA
SYNCHRONOUS
OCE
OTE SUPPLIES XMIT CLOCK
XMIT RATE (RCV CLOCK SIG) @ IR
RCV RATE (XMIT CLK SIGl EXT

PORT B
ASYNCHRONOUS
OTEOR OCE
RCV & XMIT @ RATE IT

IVC-35

0- I--

3

5

DB

10

9

~8
10 U5 f75188

DO

(PORT B
CONNECTOR)

J4

75188

DA/RX+

~"

"

J2

28

24

6

17

8

15

DA/RX+

DO

DB

II

PORT A: SYNCHRONOUS. DCE. XMIT CLOCK
PROVIDED TO DTE
PORT B: UNUSED
Figure 7

J7

2

1

'R

U10

14

3

13

6

5

27

8

7

28

~

4

L

~

1

'T

1

(BAUD-RATE
GENERATOR)

RXCA
TXCB
U4

R'XcB

(SIO)

13

14
~

10

9

,0- r--

-v
16

15

0- ~

12

75189

~
6

4

...,-

1

0- ~

9

.-----3
5

75189
U1
3

1:\

7-"

75189
U
10
8
751B8
9
10

U5

(PORT A
CONNECTOR)

J3

75189
U1
13
11

\

J1

28

24

6

17

8

15

9

DA/RX+

DO
DB
(PORT B
CONNECTOR)

J4

8

0-

10

r-

J2

751B8
12
13

PORTA
SYNCHRONOUS
DCE
XMIT CLOCK SUPPLIED TO DTE
RCV-CLOCK SUPPLIED TO DTE
XMIT RATE (RCV CLOCK SIG) @ 'T
RCV RATE (XMIT CLOCK SIG) @ 'R

TXCA

U5

11

PORT B
UNUSED

IVC-36

24

3 -"

,..., 28

5-"

6

17 DO

7

8

16

DA/RX+

DB

PORT A: SYNCHRONOUS. DTE. XMIT CLOCK
PROVIDED FROM DCE
PORT B: SYNCHRONOUS. DCE. XMIT CLOCK
PROVIDED TO DTE
Figure 8

J7

2

1

IR

"'-

4

""

6
U10

1

IT

8

(BAUD-RATE
GENERATOR)

~.J',

14
~

10

'"

~

1

14

3

13

5

27

7

28

(SIO)

l.!....-

75189

~
6

4

~

75189
U1

3~

(PORT A
CONNECTOR)

J3

75189
U1
11
13

1

75188

0- ~

9

-

3

J1

28

24

5

6

17

7

8

15

75189
U
10
8

:..0

9

DA/RX+

DO
DB
(PORT B
CONNECTOR)

J4

8

0- ~

J2

75188

~1
L.23 U5 f

--

PORTA
SYNCHRONOUS
DTE
XMIT CLOCK SUPPLIED FROM DCE
XMIT & RCV RATE EXTERNAL.
INDEPENDENT

U4

R'XcB

0- ~

0-

~

10

TXCB

15

12

U5

RXCA

13

16

9

TXCA

PORT B
SYNCHRONOUS
DCE
XMIT CLOCK SUPPLIED TO DTE
RCV CLOCK SUPPLIED TO DTE
XMIT RCV@) Rate 'R

NOTE:
This configuration is suitable for J1-J2loopback testing if fR =

tr.

IVC-37

3

28

24

5

6

17

7

8

15

DA/RX+

DO

DB

II

BOTH PORTS SYNCHRONOUS. DTE. XMIT CLOCK
PROVIDED TO DCE
Figure 9

J7

2

1

fR

........

4

~

6
U10

1

fT

~:\

8

(BAUD-RATE
GENERATOR)

~~

14
10

r--

~

1

14

3

13

6

27

7

28

(SIO)

,0- ~

0- .l.!-

~

76189

~
6

4

~

1

3

r----

9

28

24

6

17

8

16

DA/RX+

DO
DB
(PORT B
CONNECTOR)

0- !£...

J2

76188

--

SYNCHRONOUS
DTE
XMIT CLOCK SUPPLIED TO DCE
XMIT @ RATE IT
RCV RATE EXTERNAL

~

J1

J4

8

~11
1. 13 U6 J

PORTA

f-o

7

76189
U
10
8
76188

0- ~

9

6

76189
U1

3~

(PORT A
CONNECTOR)

J3

76189
U1
11
13

10

U4

RXCB

16

12

U6

RXCA
TXCB

13

16

9

TXCA

PORTB
SYNCHRONOUS
DTE
XMIT CLOCK SUPPLIED TO DCE
XMIT@ RATE f~
.
RCV RATE EXT RNAL

IVC-38

3

28

24

6

6

17

7

8

16

DA/RX+

DO

DB

CLOCK-CONFIGURATION WORKSHEET
Figure 10

J7

1 -2

fR

U10

fT

1

1

14

4

3

13

6

5

27

7

28

(BAUD·RATE
GENERATOR)

-

-

8
14

TXCA
RXCA
TXCB
RXCB

U4
(SIO)

13

~

10

9

0- r--

v

16

15

r.

12

11

0- r--

75189
U1
6

4

9

75189
U1
13
11

3
r--

f-o

5J'>

75189
U1
3

(PORT A
CONNECTOR)

J3

7

1

0-

r!£-

,...

28

24

,...

6

17

r.

8

15

J1

DA/RX+

DO
DB

75189
8 U
75188

-

10
9

~8
10 U5./'75188
~~11
13 U5

-

PORTA

IVC-39

10

0- r-

J2

24

3

28

5

6

17 DO

7

8

16 08

J

PORT B

(PORT B
CONNECTOR)

J4

DA/RX+

common interrupt line (lNTRQ) will be pulled active low by
the SIO requesting the interrupt.

ADDRESS-CONFIGURATION STRAPPING
Address selection is done by wiring the proper straps on
Header J9. Installing a strap causes the respective Address
Bit to be compared for a zero. Address select straps are
defined as follows:
Pins

3-4
1-2

7-8

5-6
9-10
11-12

ADDRESS BIT 2
ADDRESS BIT 3
ADDRESS BIT 4
ADDfiESS BIT 5
ADDRESS BIT 6
ADDRESS BIT 7

Address Bits 0 and 1 are predefined for the MDX-SI02
board as follows:

A,

o
o
1
1

Sometime later, the CPU will send out an interrupt
acknowledge (INTAK). During INTAK, the interrupt logic of
the various peripheral chips in the system will determine
the highest-priority port which is requesting an interrupt.
This device then places the contents of its 8-bit interrupt
vector on the data bus for the CPU. The interrupt condition is
maintained until the end of the INTAK cycle. Lower priority
interrupts are inhibited until this device decodes an RETI
instruction or an equivalent command.
If more than one peripheral chip requests interrupt
servicing at the same time, a priority status is established.
Priority is determined by the interrupt enable lines -lEI and
lEO - and internal logic on each peripheral chip. The
following table defines interrupt priority status:

~

o
1

o
1

PORTA DATA
PORT A CONTROUSTATUS
PORTB DATA
PORT B CONTROL/STATUS

lEI

"0

o
1

lEO

o

1

o

The Shipping Configuration for J9 is no jumpers installed.

STATUS
higher priority device
requesting interrupt
undefined (not allowed)
requesting interrupt (no
higher priority interrupt)
no interrupt

INTERRUPT DESCRIPTION
DAISVCHAIN
The purpose of an interrupt is to allow peripheral devices to
suspend CPU operation in an orderly manner and force the
CPU to start a peripheral service routine. Usually this
service routine is involved with the exchange of data, or
status and control information, between the CPU and the
peripheral. Once the service routine is completed, the CPU
returns to the operation from which it was interrupted. The
block diagram of the interrupt circuitry of the MDX-SI02 is
shown in Figure 11.
Mode 2 interrupts are supported by the MDX-SI02. This
mode is the most powerful interrupt response mode. With a
single 8-bit bytefrom the interrupting device, an indirect call
can be made to any memory location.

All Z-80 devices include daisy-chain priority-interrupt logic
that automatically supplies the programmed vector (from
the highest-priority interrupting peripheral) to the CPU
during interrupt acknowledge. To ensure that more than the
on-board SIO chip can be included in the interrupt priority
loop, "look-ahead" logic has been implemented on the
board. Both ends of the board daisy chain logic have been
brought to edge connector P1 so that the board priority
within a larger daisy chain system can be established.
Board priority is determined in the same fashion as an
individual peripheral chip i.e., through the high or low state
of PCI or PCO.
ELECTRICAL SPECIFICATIONS

With this mode, the programmer maintains a table of 16-bit
starting addresses for every interrupt service routine. This
table may be located anywhere in memory. When an
interrupt is accepted, a 16-bit pointer must be formed to
obtain the desired interrupt service routine starting address
from the table. The upper eight bits of this pointer are
formed from the contents of the I register. The lower eight
bits of the pointer must be supplied by the interrupting
device.

Word Size
Data: 8-bits
110 Addressing:

8-bits

I/O Addressing
On-board fully-programmable

1/0 Capacity
INTERRUPT SERVICING
At some predetermined condition, such as data being
strobed into a SIO port, the SIO chip will generate a
condition for interrupting the CPU. During this time, the

Serial - Two full-duplex serial ports, either synchronous or
asynchronous. Special control register and circuitry to
permit programmed implementation of SDLC, BiSync,
Monosync, HDLC, and other formats.

IVC-40

PRIORITY INTERRUPT STRUCTURE
Figure 11

+5V

10K

INT

5

II

SIO

PORT loP.

A.
B.

+5V
EDGE
CONNECTOR

r----'
PI

PCI

52

lEI
1K

6

1

2
lEO

7

r.i...-------_---i
"LOOK AHEAD"

PCO
INTRQ

51~~----------------------~

44

>-+--------.

+5V

IN

-=

~

·12VIN

?

470l!

l r J5-'2

~O
U6

R6

-4N35
- - I'2

"0

G

31

~

.-~----------~.----~ ~ "--~.~~J..

CRl
IN914

l
nov

-

-

~

1
-6

IN914.

_

U12

_

6 R13
6

..,...

T2N39041cR3

91
111

_

•
6BK

25

v-------l
47011

1

----0

o
o

13 1

L

123
T• B

~'L
---,
'12

114

-1

128

RX+ IDA)I

.24

126

RX-

.12

o

o

I 24

TX-

.25
130

TX+

_-1

-

7406

II

1

I

I

.13

POlARIZATION~26
PLUG

...L
-

I

I

I

T
----:~N914~

..J
+~ bll~1
150(1

~

271

lBOl!

470!1

•

16 470 !1

.7

POlARIZATION_22
PLUG
,

.J R2

+12VIN~

-

I.

14 Rl1

~
::a

2

112

,

3900F

~l>

l>
-g

I

OTRAI 16

OCOAI19

• 4

GNOIAA)I

:
151

cC· 0
c: ::a
ca -I

Jl

.. 6

.-

17

OSRICC)I

0

r - J4- -,• 2

390pF
+12V IN

R3

1

~O

3Kll

TXDB~

1
13

})- •

'

1

0

I

151

""'f

U4

o

-=;'xfBA)1

o

211

CTSs 123

112

r, B

I

~
z

o

•

20

..

B

5

O~_1~20~______~R~Xf~B~B)~I.~

3

122

CTSfCB)1

I
19

RXDB 129

1

1

"::rmrn
PORTB

I

0

J,.

L

GNDfAB)1

~

-=- '~12VIN- - - ,

+5V

?

47011

R15
3.9K
5!

1r

p:
31

R8

UB - ,
~N35.2

5

1

L-----------~41
CR4
• "~L=lt~

J5 0

2

16 47011
~.

~~.------------

l

+12VIN

._.
/
R1.8
15011

IN914..
U12

5

-

6

I_.

6 R19

271

o

.L...L

.

25

1

o

47011

47011

RX+ IDA)I

.24

126

RX-

1

TX-

I
1
~ 25
I

1

18011

~

~

T2N39041cR6

1
..J

68K

6

12B

1

L_I_.JR4

R16

I

T
,B

91

110

111

112

13 1

114

~-~

7

POLARIZATION_22
PLUG
1

14 R17
~

IN914

+5V

I

.

~
1

29 1

I
o

o o

L_

24

130
I

_..J

~

~::u

!!1

~

o

Wrn
~

"P

2

1
DCDfCF)1

::u

~ -I
-'IJI

o

~

DTRfCD)\

c

~

1

I·

I

171

22

MK3B87

<

..

4

1

111
I

DTRB 25

DCDii

RTSICA)I

I

116

o

.. 6

GNDIAA)I

:

390pF

J2

1

114

0

,6!~

·

DSRICCII

12

TX+~
I
.13·
I
I
POLARIZATION_26
PLUG

ORDERING INFORMATION

Designator

Description

Part Number

MDX-SI02

MDX-SI02 SeriallnputlOutput Module with
Technical Manual

MK77670-0 (2.5 MHz.)
MK77670-4 (4 MHz.)

MDX-SI02 Technical Manual

MDX-SI02 Technical Manual Only

4420129

II

IVC-45

IVC-46

e

UNITED
TECHNOLOGIES

COMPUTER
PRODUCTS
DIVISION

MOSTEK

MDX-4221
MK77671
FEATURES

BOARD PHOTO
Figure 1

o STD-Z80 BUS compatible
o Two independent asynchronous/synchronous serial
channels
o Independent software programmable baud rate clocks
o Asynchronous rates of 50 to 19.2K baud
o Synchronous rates of 800 to 307.2K baud
o Asynchronous half-duplex communications between
serial control units and MDX-422's in any mix
o BiSync, HDLC or SDLC operation
o Both CRC-16 and CRC-CCITI error detection are
hardware implemented
o Receive data registers are quadruply buffered
o Transmitter data registers are double buffered
o RS-422 compatible input and output
o Up to 4000' data communication over RS-422 twisted
pair

MK3887 Z80-S10 which provides both full- and half-duplex
operation. Each channel has an independent programmable baud rate clock generator to increase module
flexibility.

o Common mode ground fault protection 400 Volts

DESCRIPTION

Figure 2 is a block diagram of the MDX-4221 module. The
figure consists of six main elements: address decode and
data bus buffers, MK3887 Z80-SIO, isolated supply voltage,
line drivers and receivers, programmable baud rate
generator and channel configuration headers. Input and
output to the board is provided via two 10-pin connectors.
One connector is dedicated for each channel. Figure 1
shows the board with overlay.

The MDX-4221 is a dual-channel, serial RS-422 interface
for use with STD-Z80 microcomputer systems. The module
incorporates RS-422 (balanced, differential) serial communication, allowing long-distance communication (4000
ft.) in noisy industrial environments between MDX-4221's
and/or SCU's (Serial Control Units). Each MDX-4221
channel is capable of driving forty devices in a party-line
configuration. The module is designed around the Mostek

The RS-422 interface on the MDX-4221 module is fully
isolated up to 400 volts above and below ground. This is
implemented to ensure protection from common mode
ground potentials associated with long-distance communications. The transmitter/receiver section also has protection against transients of up to 150 watts peak pulse power
for 1 ms. These transients are commonly induced on the
transmission lines in noisy industrial environments.

o Port block selectable
o 2.5 and 4 MHz capability
o 400 Volt optically isolated

™ MD Series is a trademark of Mostek Corporation

IVC-47

BLOCK DIAGRAM
Figure 2

CHANNel A
DATAIB)
PORT
CONFIGURATION
HEADERS

ADDRESS
DECODE
AND
DATA BUS
BUFFERS

RS-422
DATA

MK3BB7
SIO

CONTROL
(101

CHANNel B
PORT
CONFIGURATION
HEADERS

SPECIFICATIONS

*1
*1

o
1

RS-422
DATA

Baud rate generator
Baud rate generator

WORD SIZE
*The baud rate generator is decoded from A2, therefore it
may be programmed with any of the four available
addresses. The high order 4 bits program channel A while
the low order 4 bits program channel B.

8. bits
8 bits

Data:
I/O Addressing:

I/O CAPACITY
INTERRUPTS
Serial: Two full- or half-duplex serial ports both capable of
either synchronous or asynchronous operation. Special
control registers and circuitry to permit implementation of
SDLC, BiSync, Monosync, HDLC and other formats which
can be programmed.

I/O ADDRESSING

SYSTEM INTERRUPT UNITS (SIUs)

the high-order 5 bits of the I/O address are userprogrammable through the use of selecting straps. The
low-order three bits are decoded on-board, thus indicating
the need for eight consecutive port addresses. These ports
are assigned as follows:

A2

0
0
0
0
*1
*1

A1
0
0
1
1
0
0

AO
0
1
0
1
0

Generates vectored interrupts to 8 different locations
corresponding to conditions within both channels. Interrupt
vector locations are programmable. Daisy-chained interrupt
priority.

PortA data
Port A control/status
Port B data
Port B controll status
Baud rate generator
Baud rate generator

=1

CLOCK

MDX-4221

Min.
250 kHz

Max.·
4.0 MHz

STD-Z80 BUS INTERFACE
Inputs:
Outputs:

IVC-48

One 74LS Load Max.
IOL=24mA Min. @VOL = 0.5Volts
10H = -3mA Min. @VOH = 2.4Volts

CONNECTORS

OPERATING TEMPERATURE

o to 60 degrees C
POWER SUPPLY REQUIREMENTS
+5 Volts ± 5% at 2.0A max.
+12 Volts ± 5% at 25mA max.

FUNCTION

DESCRIPTION

STD-Z80 BUS

56-pin, dual

MATING
CONNECTOR
Viking 3VH281
1CE5
(printed circuit)

DIMENSIONS

Viking 3VH281
1CND5
(wire-wrap)

4.5 inches (114.3 mm) high by 6.5 inches (165.1 mm) long
0.675 inches (17.1 mm) maximum profile thickness
0.062 inches (1 .6 mm) printed-circuit-board thickness

Viking 3VH281
1CN5
(solder lug)
RS-422

Socket conn.
10-pin

Winchester
51-1110-01

TYPICAL APPLICATION.

MDXSYSTEM

I IIII

RS-422 LINK

MDX-4221

CONTROL
CIRCUITRY

CONTROL
CIRCUITRY

RSCU

ORDERING INFORMATION

DESIGNATOR

DESCRIPTION

PART NO.

MDX-4221

RS-422 interface module with operations manual

MK77671

Operations manual for the above

4420071

Z80-SIO Technical Manual

MK78583

tVC-49

IVC-50

fJ

UNITED

COMPUTER
PRODUCTS
DIVISION

TECHNOLOGIES
MOSTEK

MDX-422N
MK77676
FEATURES

MDX-422N

o Two independent asynchronous/synchronous serial
channels

o

Independent software programmable baud rate clocks

o

Asynchronous rates of 50 to 19.2K baud

o

Synchronous rates of 800 to 307.2K baud

o

Asynchronous half-duplex communications between
serial control units and MDX-422's in any mix

o

BiSync, HDLC or SDLC operation

o

Both CRC-16 and CRC-CCITT error detection are
hardware implemented

Figure 1
\

~,'

>

•

o Receive data registers are quadruply buffered

o

Transmitter data registers are double buffered

o

RS-422 compatible input and output

o

Port block selectable

o

STD-Z80 BUS compatible

o

2.5 and 4 MHz capability

configuration headers. Input and output to the board is
provided via .two ·'O-pin con\1ectors. One connector is
dedicated for ea~h Channel.
SPECIFICATIONS

DESCRIPTION
WORD SIZE
The MDX-422N is a dual-channel, serial RS-422'interface
for use with MDX microcomputer systems. The module
incorporates RS-422 (balanced, differential) serial communication, allowing long-distance communication in
noisy industrial environments between MDX-422's and
MDX-422N's and/or RSCU's (Serial Control Units). Each
MDX-422N channel is capable of driving forty devices in a
party-line configuration. The module is designed around the
Mostek MK3887 Z80-S10 which provides both full- and
l1alf-duplex operation. Each channel has an independent
programmable baud rate clock· generator to increase
module flexibility.

Data:
I/O Addressing:

8 bits
8 bits

I/O CAPACITY
Serial: Two full- orhaJ.f-dupIIlX seriai,ports both capable of
either synchronous or asyn<;:hronous operation. Special
control registers and circuitry to permit implementation of
SDLC, BiSync, Monosync, HDLC and other formats which
can be programmed.
I/O ADDRESSING

Figure 2 is a block diagram of the MDX-422N module. The
device consists of five main elements: address decode and
data bus buffers, MK3887 Z80-SIO, line drivers and
receivers, programmable baud rate generator, and channel

The high-order 5-bits of the I/O address are userprogrammable through the use of selecting straps. The
low-order 3-bits are decoded on-board, thus indicating the

TMMDX Series is a trademark of Mostek Corporation

IVC-51

SLOCK QIAGR.AM
Figu", 2

CHANNEL A

RS-422
DATA

ADDRESS
DECODE
AND
DATA BUS
BUFFERS

MK3887
SIO

CONTROL
CHANNELB

(10)

RS·422
INTERFACE
LINE
DRIVERS

need for eight consecutive port addresses. These ports are
assigned as followS:
A2
0
0
0
0
*1
*1
*1
*1

A1
0
0
1
1
0
0
1
1

AO
0
1
0
1
0
1
0
1

RS·422
DATA

CLOCK
Max.
4.0 MHz

MDX-422N
POrl A data
Port A control/status
Port B data
Port B control/status
Baud rate generator
Baud rate generator
Baud rate generator
Baud rate generator

STD-zao BUS INTERFACE
Inputs:
Outputs:

OPERATING TEMPERATURE

*The baud rate generator is decoded from A2, therefore it
may be programmed with any of the four available
addresses. The high-order 4-bits program channel A while
the low-order 4-bits program channel B.

o to 60 degrees C
POWER SUPPLY REQUIREMENTS
+5 Volts ± 5% at 1.0 A max.
+12 Volts ± 5% at 25 rnA max.

INTERRUPTS
Generates vectored interrupts to eight different locations
corresponding to conditions within both channels. Interrupt
vector location programmable. Daisy-chained interrupt
priority.
SYSTEM INTERRUPT UNITS (SIUs) = 1

One 74LS Load Max.
IOL= 24mA Min. @ VOL = 0.5 Volts
IOH = -3mA Min. @VOH= 2.4Volts

DIMENSIONS
4.5 inches (114.3 mm) high by 6.5 inches (165.1 mm) long
0.675 inches (17.1 mm) maximum profile thi.ckness
0.062 inches (1.6 mm) printed-circuit-board thickness

rVC-&2

TYPICAL APPLICATION:
Figure 3

MDXSYSTEM

I IIII

RS-422 LINK

MDX-42210R
MDX-422N

CONTROL
CIRCUITRY

CONTROL
CIRCUITRY

RSCU

OTHER
RS-422
DEVICES

II

CONNECTORS

FUNCTION

DESCRIPTION

STO-Z80 BUS

56-pin, dual

MATING
CONNECTOR
Viking 3VH281
1CE5
(printed circuit)
Viking 3VH281
1CND5
(wire-wrap)
Viking 3VH281
1CN5
(solder lug)

RS-422

Socket conn.
lO-pin

Winchester
51-1110-01

ORDERING INFORMATION

DESIGNATOR

DESCRIPTION

PART NO.

MDX-422N

RS-422 interface module with operations manual

MK77676

Operations manual,only.

4420053

Z80-S10 Technical Manual

MK78583

IVC-53

IVC-54

Il

UNITED
TECHNOLOGIES
MOSTEK

COMPUTER
PRODUCTS
DIVISION
RSCU
MK77983
REMOTE SERIAL CONTROL UNIT

FEATURES
D

RSCU (MK77983) PHOTO
Figure 1

Utilizes the MK3873 Microprocessor

D Asynchronous Serial I/O
D Half-duplex operation
D

Data rate of 9600 Baud

D 24 Parallel I/O bits individually strappable as input or
output
D Single 5 Volt power supply
D Eight-bit selectable unit address

•

D Operation with up to 4000 feet of cable
D Up to 40 units on a RS-422 link
D Serial receiver/transmitter I/O protected against
transients with up to 150 watts peak pulse power for 1
ms

RSCU SYSTEM CONFIGURATION
DESCRIPTION

Figure 2

MAXIMUM

4000·

The RSCU (remote serial control unit) is an asynchronous
serial-to-parallel conversion unit that is used for remote
digital control over an RS-422 serial data link. Serial data is
received and transmitted by using a half-duplex RS-422
(balanced differential) at 9600 Baud. The transmitter/
receiver is capable of communicating up to 4000 feet from
the host in noisy industrial environments. A system can use
up to 40 RSCUs on one RS-422 link. See Figure 2 for an
illustration of an RSCU system configuration.
The RSCU is packaged in a black ABS plastic container for
mounting purposes. The container also protects the board
in industrial environments. Four mounting holes are
provided in the back of the container. The mounting holes
are easily accessed by removing four screws and the cover.
The unit's 24 parallel bits provide interface for up to 241/0
devices such as optically isolated solid-state relays. Parallel
devices, such as analog converters, may also be controlled.
The RSCU has five main elements: MK3873 microprocessor, address select logic, reset logic, serial line transmitter/
receiver, and parallel I/O with data-direction jumpers (as
illustrated in Figure 3).

LESS CABLE
DROP LENGTH

~I

MK3873
The MK3873 single-chip microprocessor has a serial I/O
port that provides data for the RS-422 driver and receiver
which communicates with the host system. The MK3873
also provides 29 bits of parallel I/O (Three bits used
internally on the board and two that are unused.), of which
24 are available for off-board use.

ADDRESS SELECT LOGIC
The address select logic consists of an 8-bit parallel-in,
serial-output shift register. The shift register inputs are
jumper-selectable to the desired unit address for the RSCU.
Power-up reset or push-button reset causes the microprocessor to load and read the shift register by serially
shifting in the 8-address bits.

IVC-55

RSCU BLOCK DIAGRAM
Figure 3
RS422
DATA

JI

~

"\
I

RS422
TRANSMITTERI
RECEIVER

V
1\

1\

\
/
v
PROCESSOR

SELECT

/

\

LOGIC

\

I

8 BITS

BUFFERS

~

A

MK3873

ADDRESS

PARALLEL

PARALLEL 1/0

\

/
\,

I

1/0

AND

V

DATA

1\

....

DIRECTION
JUMPERS

/"

POWER-UP
AND
PUSHBUTTON
RESET LOGIC

RESET
Power-up reset and push-button reset cause a reset pulse
of approximately 20 ms to be generated. A comparator
circuit also generates this reset signal and holds the reset
line active if 5 Vdc power falls below 4.60 volts.

RS-422 RECEIVER AND TRANSMITTER
Bidirectional serial data is transmitted and received by an
RS-422 line driver and receiver. Transient suppressors are
provided to protect the serial 110 channel against transients
of up to 150 watts peak for 1 ms duration. The serial data
format is shown in Figure 4.

selected as an input or output by installing a jumper in the
appropriate position.

CONNECTORS AND HEADERS LAYOUT
Figure 5 illustrates the layout of connectors and headers on
the RSCU board. Figures 6,7, and 81istthe pinoutsforSK1,
J5, and J6, respectively.

CONNECTORS AND HEADERS LAYOUT
Figure 5

SERIAL DATA FORMAT
Figure 4

~EE~:iGE > 2 CHARACTER
FORMAT

TIMES

DEFINES DATA

,:0:,

DEFINES
MESSAGE LENGTH

DATA LENGTH
DETERMINED BY
COMMAND CHARACTER
LONGITUDINAL
REDUNDANCY
CHECK

2~1

••

INPUT10UTPUT

J5

9 ••••• 1
10' •••• 2

The 24-bit parallel 1/0 from the microprocessor is buffered
in both input and output directions. Each bit must be

IVC-56

STRAPPING

SK1 Pinout
Figure 6

ADDRESS STRAPPING
Pin #

Pin #

Pin #
1

PO-O

2

3

PO-1

5

Pin #

27

P4-5

28

4

29

P4-6

30

PO-2

6

31

P4-7

32

7

PO-3

8

33

P5-0

34

9

PO-4

10

35

P5-1

36

11

fiO-5

12

37

P5-2

38

13

PO-6

14

39

P5-3

40

15

PO-7

16

41

P5-4

42

17

P4-0

18

43

P5-5

44

19

P4-1

20

45

P5-6

46

GND

A total of 255 (0 through 254) separate addresses may be
chosen using the 8-address jumpers as shown in Figure 9.
Address selection is accomplished by installing the address
jumpers on header J4 in the desire configuration. Installing
a jumper is equivalent to selecting the particular address bit
to be zero.
NOTE: Jumpers must be placed on J4. All jumpers are
installed on J4 when RSCU is shipped. Leaving J4
unstrapped gives the RSCU the address OFFH
which is not a recognized RSCU address.
Address bit AO is the least significant bit, address A7 is the
most significant and is the first bit shifted into theMK3873
when the address is loaded.
ADDRESS DECODING
Figure 9

• 5V

J4

21
23

P4-2
P4-3

22
24

47
49

P5-7
+5V

48
50

--1

0--2. ~
o----! -0

I,

.........z. -0
,........! -0
,........!.!.
,......E.

:

GND

,.......1! -0

25

P4-4

AOA

4

Al

•

B

A2 C

8

A3 0

10

A4 E

,.
,.

12

AS F

AG G .
A7 H

6"

SE;:tIAL
~ADDRESS

OUT

26
Figure 10 shows an example of strapping J4 for address 36
(24 H)·

J5 Pinout
Figure 7

J4 STRAPPING EXAMPLE

Pin #

Figure 10

1

NC

6

TXRX

2

NC

7

TXRX

3

NC

8

TXRX

4

NC

9

GND

5

2

TXRX

10

ADDRESS

BIT

BIT

VALUE

GND

,rr

'J4

--""'l.,

PIN
NUMBER - - ,

AO---O--- 1

0

0

2

A1---0 - - - 3

0

0

4

A2---1 - - - 5

0

0

6

A3--- 0 - - - 7

0

0

8

AA--- 0 - - - 9

0

0

10

A5---1 ---11

0

0

12

A6--- 0 ---13

0

0

14

A7--- 0 ---15

0

0

16

J6 Pinout
FigureS

Pin #

r-B

[E]

DATA DIRECTION JUMPERS
The 24 parallel 1/0 signals are provided with jumpers so
any bit may be configured as input or output. To configure
the bit as input, jumpers are added between pins of J1 and
J2. To configure the bit as output, jumpers are added
between pins of J2 and J3. The RSCU board is shipped
configured as input with jumpers installed between J1 and
J2. See Figure 11.
IVC-57

terminating resistor (R9). Only' an- RSCU" placed on the
extreme end of the transmission line requires termi,n!!tjon.
LOW-VOLTAGE RESET ADJUSTMENT

DATA DIRECTION JUMPERS
Figure 11
PIN NUMBER

HEADER

JJ21~' ~:
1

2

0

0

Adjustment of Rp establishes the voltage level at which the
loss of power: This level is factory set at
MK3873 is reset
4.6 volts and should not be changed, If R6 has been
inadvertantly changed the foliow,ing procedure should be
used to reset the voltage level,

on

NUMBER

J3

1

t +

STR,APPED
FOR INPUT

WARNING
Mostek does not assume any responsibility for
module failure if this adjustment is made.

STRAPPED
FOR OUTPUT

Table' ,1' is' an example of data direction jumpering and the
corresponding output signai mnemonic, associated jumper
number, and I/O device (24-module opto I/O panel is used).

1. Adjust the power supply so that 4.6, volts is present on
the 5 volt input (Pins ,1 and 2 on J6).,
2. Connect an oscilioscopeor a voltmeter to the output of
the ICL8211 (Pin 4 cif U12),

LINE TERMINATION RESISTOR
The RS-422 transmission line should be terminated on
each end with a 200 ohm resistor. The purpose of this
resistor is to reduce reflections from the end of the cable.
Two printed circuit board holes are provided for ~ % watt

3. Adjust R6 until the voltage on Pin 4,of the ICL8211
,goes tQa high level (greater than 2.4 V).
, 4. Slowly adjust the R6 in the opposite direction until the
voltage goes to !'I low level (less than.7 V).

EXAMPLE OF D4TA OIRECTION JUMPERING
Table 1
' "~
DATA DIRI;CTION
JUMPER
NUMBER
"

IJOPORY
NUMBER

,OPTOI/O
MODULE NUMBER

OPTO 1/0"
OUTPUT TERMINAL NUMBERS

23
22
21
20
19
18
17
16

4748
4546
43-44
41-42
39-40
37-38
35-36
33-34

15
14
13
12
11
10
9
8

31-32
29-30
27-28
25-26
23-24
21-22 '
19-20
17-18

::-,:',

"

PO-O
PO-1
PO-2
PO-3
PO-4
PO~5
(,.'
PO-6
PO-7

,

"

1
2
3

4
5
6
7
8

,

P4-0
P4-1
P4-2
, P4-3
P4-4
P4-5
P4-6
P4-7
P5-0
P5-1
P5-2
P5-3:
P5-4
P5-5
P5-6,
P5'7

,

9
10

11·
12
13,
14
15
16

,

,
"

17
18
19
20
21
22
23
24

"

15-16
13-14
11-12
9-10
7-8
5-6
34
1-2

7
6
5
4
3
2
1
0

.:'

"

i

"

..
IVC-58

,

SPECIFICATIONS

SERIAL BAUD RATE

WORD SIZE

9600 Baud

Data:

8-bits

110 addressing:

24-BIT PARALLEL INPUTIOUTPUT BUS
8-bits

MEMORY CAPACITY

=-2.7 rna

Inputs:

IlL

Bus Outputs:

IOH open collector
IOL = 24 rna maximum at 0.5 volts

32 bytes RAM

POWER SUPPLY REQUIREMENTS
UNIT ADDRESSING
+5 volts ± 5% at 1.5 A maximum
On-board 8-bits jumper-selectable

OPERATING TEMPERATURE
I/O CAPACITY
O°C to 60°C
Serial:

One half-duplex serial port capable of
asynchronous operation

SERIAL COMMUNICATION INTERFACE
One Port Signal:
Transmitted Data:
Received Data:

RS-422
Output
Input

ENCLOSURE DIMENSIONS
6.5"(165.1 mm) widex5.5" (139.7 mm) deep x 1.5"(38.1
mm) high

WEIGHT
1 lb.

II

CONNECTORS
FUNCTIONS

CONFIGURATION

MATING CONNECTOR

RS-422
Interface

Socket connector
10-Pin

Winchester
51-1110-01

1/0 Bus
Interface

Socket connector
50-Pin

Winchester
51-1150-01

Power

2-Pin connnector

Molex
Connector 26-03-4020
Pins
08-50-0189

IVC-59

I

TYPICAL APPLICATION
Figure 12

o

2
RSCU #1

23

o
1
RSCU #2

23

s= 4000'

RSCU #40

OPTO PANEL

DODD
LIMIT SWITCH
LINE

l_. .

NEUTRAL _ _ _ _ _ _ _

NEUTRAl_~~_~

WARNING: This equipment generates, uses, and can radiate radio frequency energy and if not installed and used in
accordance with the instructions manual, may cause interference to radio communications. As temporarily permitted by
regulation it has not been tested for compliance with the limits for Class A computing devices pursuant to Subpart J of Part
15 of FCC Rules, which are designed to provide reasonable protection against such interference. Operation of this
equipment in a residential area is likely to cause interference in which case the user at his measures may be required to
correct the interference.

IVC-60

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NO.

RSCU

Microprocessor-based remote controller with Technical
Manual

MK77983

MDX-4221

RS-422 interface card (isolated) with Operations Manual

MK77671

MDX-422N

RS-422 interface card (non-isolated) with Operations Manual

MK77676

Technical Manual for RSCU

4420164

Operations Manual for MDX-4221

4420071

Operations Manual for MDX-422N

4420053

ISCU User/Programming Manual (used with RSCU)

4420174

II

IVC-61

IVC-62

l!J

UNITED

COMPUTER
PRODUCTS
DIVISION

TECHNOLOGIES
MOSTEK

RIOC
MK78208
REMOTE 1/0 CONTROLLER
FEATURES

RIOC (MK78208) PHOTO
Figure 1

o Utilizes the MK3873 Microprocessor

o Asynchronous Serial I/O

o

Half-duplex operation

o Data rate of 9600 Baud

o

24 Parallel I/O bits individually strappable as input or
output

o Single 5 Volt power supply

II

o

Eight-bit selectable unit address

o

Operation with up to 4CXJO feet of cable

o

Up to 40 units on a RS-422 link

o

Serial receiver/transmitter I/O protected against
transients with up to 150 watts peak pulse power for 1
ms

RIOC SYSTEM CONFIGURATION
Figura 2

DESCRIPTION

MAXIMUM
4000'

~I

lESS CABLE
DROP lENGTH

The RIOe (remote I/O controller) is an asynchronous serialto-parallel conversion unit that is used for remote digital
control over an RS-422 serial data link. Serial data is
received and transmitted by the RIOe in the half-duplex
mode at 9600 Baud. The transmitter/receiver (RS-422,
balanced differential) is capable of communicating up to
4CXJOfeet from the host in noisy industrial environments. A
system can use up to 40 RIOes on one RS-422 link. See
Figure 2 for an illustration of an RIOe system configuration.

MAXIMUM
---40RIOC - UNITS

which communicates with the host system. The MK3873
also provides 29 bits of parallel I/O (Three bits are used
internally on the board and two are unused.), of which 24
are available for off-board use.

The unit's 24 parallel bits provide interface for up to 241/0
devices such as optically isolated solid-state relays. Parallel
devices, such as analog converters, may also be controlled.

ADDRESS SELECT LOGIC

The RIOe has five main elements: MK3873 microprocessor, address select logic, reset logic, serial line
transmitter/receiver, and parallel I/O with data-direction
jumpers (as illustrated in Figure 3).

The address select logic consists of an 8-bit parallel-in,
serial-output shift register. The shift register inputs are
jumper-selectable to the desired unit address for the RIOe.
Power-up reset or push-button reset causes the microprocessor to load and read the shift register by shifting
serially in the 8-address bits.

MK3873
RESET
The MK3873 single-chip microprocessor has a serial I/O
port that provides data for the RS-422 driver and receiver

Power-up reset and push-button reset cause a reset pulse

IVC-63

RIOC BLOCK DIAGRAM
Figure 3
RS422

A

DATA

'I

\
-/

RS422
TRANSMITTER
RECEIVER

V
r-..

"

~

\
/
v
MK3B73
PROCESSOR

/

LOGIC

\

"

1/0

BUFFERS

V
\

\

/

•

ADDRESS
SELECT

PARALLEL

PARALLEL 1/0
A

AND
DATA

/
\

~

v

DIRECTION
JUMPERS

\
.I
v
.......

POWER-UP
AND
PUSHBUTTON
RESET LOGIC

of approximately 20 ms to be generated. A comparator
circuit also generates this reset signal and. holds the reset
line active if 5 Vdc power falls below 4:.60 volts.

selected as an input or output by installing a jumper in the
appropriate position.
CONNECTORS AND HEADERS LAYOUT

RS-422 RECEIVER AND TRANSMllTER
Bidirectional serial data is transmitted and received by an
RS-422 line driver and receiver. Transientsuppressors are
provided to protect the serial 1/0 channel against transients
of up to 150 watts peak for 1 ms duration. The serial data
format is shown in Figure 4.

Figure 5 illustrates the layout ofthe jumpers and headers on
the RIOe board. Figures 6 and 7 list the pinout for SK1 and
J5. respectively.
CONNECTORS AND HEADERS LAYOUT
Figure 5

SERIAL DATA FORMAT

1A
1C

Figure 4

I
J1
J2
J3

SERiAl
MESSAGE
FORMAT

I

ISK1

I

H

> 2 CHARACTER
TIMES

,D'
J4

DATALENOTH

DETERMINEDBV ---------~
COMMAND CHARACTER

15

LONGrTUDlNAL

16

REDUNDANCY
CHECK

J5

INPUTIOUTPUT

9 ••••• 1
10· •••• 2

The 24-bit parallel 110 from the microprocessor is buffered
in both input ,md output directions. Each bit must be
IVC-64

STRAPPING

SK1 Pinout
Figure 6

Pin #

Pin #

Pin #

ADDRESS STRAPPING

Pin #

A total of 255 (0 through 254) separate addresses may be
chosen using the address jumpers as shown in Figure S.
Address selection is accomplished by installing the address
jumpers on header J4 in the desired configuration.
Installing a jumper is equivalent to selecting the particular
address bit to zero.

1A

+5V

1C

+5V

17A

GND

17C

P4-1

2A

+5V

2C

+5V

1SA

~

1SC

P4-2

3A

NC

3C

NC

19A

19C

P4-3

4A

GND

4C

GND

20A

20C

P4-4

5A

GND

5C

GND

21A

21C

P4-5

6A

NC

6C

NC

22A

22C

P4-6

7A

NC

7C

NC

23A

23C

P4-7

SA

GND

SC

PO-O

24A

24C

P5-0

~

9C

PO-1

25A

25C

P5-1

Address bit AO is the least significant bit, address A7 is the
most significant and is the first bit shifted into the MK3S73
when the address is loaded.

10A

10C

PO-2

26A

26C

P5-2

ADDRESS DECODING

11A

11C

PO-3

27A

27C

P5-3

12A

12C

PO-4

2SA

2SC

P5-4

13A

13C

PO-5

29A

29C

P5-5

9A

NOTES
Jumpers must be placed on J4. No
jumpers on J4 is a condition which is not
allowed.
All jumpers are installed on J4 when RIOC
is shipped:

Figure 8

II

• BV

14A

14C

PO-6

30A

15A

15C

PO-7

31A

16A

GND

16C

P4-0

32A

It
GND

30C

P5-6

31C

P5-7

32C

+5V

J'

~
~

~
~
~~
~
P ~
~
~~

""A

2

•

Al

,.

•

6

A2c

8

A3 0
A4 E

",.

AB,

,.

A6 G
A7 H

SERIAL

ADDRESS
a..~ OUT

J5 Pinout
Figure 7

Pin #
1

NC

2

NC

3

NC

Figure 9 shows an example of strapping J4 for address 36
(24H).
J4 STRAPPING EXAMPLE
Figure 9

4
5
6
7
S

NC
TXRX
TXRX
TXRX
TXRX

9

GND

10

GND

IVC-65

ADDRESS

BIT

BIT

VALUE

r, r

J4
PIN
--,
NUMBER - , ,

AO---O--- 1

0

0

2

A1---0 - - - 3

0

0

4

A2---1 - - - 5

0

0

6

A3~0---

7

0

0

8

A4---0--- 9

0
0

0

10

A5---1 ---11

0

12

A6--- 0 ---13

0

0

14

A7--- 0 ---15

0

0

16

DATA DIRECTION JUMPERS

WARNING

The 24 parallel 1/0 signals are provided with jumpers, so
any bit may be configured as input or output. To configure
the bit as iripLitjumperS are added between pins of J1 and
J2. To configure the bit as output jumpers are added
between pinl~; of J2 and :J3. The' RIOC board is shipped
configured as input with jumpers installed between J2 and
J3. See Figure 10.
DATA DIRECTION JUMPERS
Figure 10

HEADER
NUMBER

J2

J3

1

2

~
0

0

~24
O.

2. Connect an oscilloscope or a voltmeter to the output of
the ICL8211 (Pin 4 of U12).. '

4. Slowly adjust the R6 in the opposite direction until the
voltage goes to a low level (less than .7 V).
SPECIFICATIONS

t.

. 'STRAPPED
FOR INPUT

1. Adjust the power supply ~o that 4.6 volts is present on
the 5 volt input (Pins 1 and 2 on J6).

3. Adjust R6 until the voltage on Pin 4 of the ICL8211
goes to a high level (greater than 2:4 V).

PIIII NUMBER

J1

Mostek ~oes not assume any r~sponsibility for
module failure if this adjustment is made.
,'

.

WORD SIZE

t,

Data:

a-bits

STRAPPED
I,::

FOR OUTPUT

I/O addressing:

Table 1 is an example of data direction jumpering and the
corresponding output signal mnemonic, associated jumper
number, and 1/0 device (24-module
.' .
. opto 1/0 panel is used).
LINE TERMINATION RESISTOR

MEMORY CAPACITY,
32 bytes RAM
UNIT ADDRESSING

.

,

8-bits

The RS-422 transmission line should be terminated on
thi~
each end with a 200 ohm resistor. The p~rpose
resistor is to reduce reflections from the end of the cable.
Two printed circuit board holes are brovided for a,JAwatt
terminatinll resistor (R/9). Only an'RIOe placed on the
extreme end of the, transmission line requires termination.

or

LOW-VOLTAGE RESET ADJUSTMENT

On-board 8-bits jumper:selectable

1/0 CAPACITY
Serial:

One half-duplex serial port capable of asynchronous operation .

SERIAL COMMUNICATIONS INTERFACE

Adjustment of R6 establishes the voltage 'level at which the
MK3873 is reset on loss of power. This level is factory set at
4.6 voltS and should not 'be changed. If R6has been
inadvertantly changed the following proced'tJre should be
used to reset the voltage level.

One Port Signal:
Transmitted Data:
Received Data:

RS-422
Output
Input

EXAMPLE O',FDATA DIRECTION JUMPERI.NG
T~le1

..

,

,

I/O'PORT

' JUMPER

1/0 PORT

JUMPER

1/0 PORT

JUMPER

P4-0
P4-1

9
10
11
12
13
14
15
16

P5-0
P5-1
P5-2
P5-3
P5-4
P5-5
P5-6
P5-7

17
18
19
20
21
22
23
24

.",

P()-O
.:!

PO-1
PO-2
PO-3
00-4
PO,5

" ,1"0-6"
PO-7

1
2
3
4'
5
,,6
7
8

;

P4~2

P4-3
P4-4
" P4-5
P4-6
P4-7

I\lC·66

"

OPERATING TEMPERATURE

SERIAL BAUD RATE
9600 Baud

24-BIT PARALLEL INPUTIOUTPUT BUS

CARD DIMENSIONS

Inputs:

IlL =

Bus Outputs:

IOH open collector output
IOL =24 ma maximum at 0.5 volts

3.9 in (100 mm) high by 6.3 in (160 mm) long
0.675 in (1.71 cm) maximum profile thickness
0.062 in (0.16 cm) printed circuit board thickness

-2.7 ma

POWER SUPPLY REQUIREMENTS
+5 volts

± 5% at 1.5 A

maximum

CONNECTORS
FUNCTIONS

CONFIGURATION

MATING CONNECTOR

RS-422
Interface

Socket connector
10-Pin

Winchester
51-1110-01

Power and
1/0 Bus
Interface

Socket connector
64-Pin

Winchester
968-6033-0522-1

II

IVC-67

TYPICAL APPLICATION:
Figure 11

o

2
Rloe #1

23

o
1
Rloe #2

23

Rloe #40

OPTO PANEL

DODD
LIMIT SWITCH
LINE
NEUTRAL -

l_,..J

______

NEUTRAl_~~_~

WARNING: This equipment generates, uses, and can radiate radio frequency energy and if not installed and used in
accordance with the instructions manual, may cause interference to radio communications. As temporarily permitted by
regulation it has not been tested for compliance with the limits for Class A computing devices pursuant to SubpartJ of Part
15 of FCC Rules, which are designed to provide reasonable protection against such interference. Operation of this
equipment in a residential area is likely to cause interference in which case the user at his measures may be required to
correct the interference.

IVC.:68

ORDERING INFORMATION

DESIGNATOR

DESCRIPTION

PART NO.

RIOe

Microprocessor-based remote controller with Technical
Manual (European Version)

MK78208

MDX-4221

RS-422 interface card (isolated) with Operations Manual

MK77671

MDX-422N

RS-422 interface card (non-isolated) with Operations manual

MK77676

Technical Manual for RIOe

4420165

Operations Manual for MDX-4221

4420071

Operations Manual for MDX-422N

4420053

Iseu User/Programming Manual (used with RIOe)

4420174

II

IVC-69

IVC.-70

m

UNITED

COMPUTER
PRODUCTS
DIVISION

TECHNOLOGIES
MOSTEK

MDX-DIOB1

FEATURES

MDX-DIOB1
Figure 1

o Provides parallel, memory-mapped Digital I/O Bus
o Services up to 64 8-bit liD ports
o Services up to 16 Mostek DIOPs
o Balanced differential transmission with twisted-pair
lines
o Up to 50 feet Digital 1/0 Bus length
o Address block selectable with jumpers
o One wait-state generator option
o 4 MHz capability
o Single +5 volt supply
o STD-Z80 Bus compatible

GENERAL DESCRIPTION
The Digital liD Bus Interface Module (MDX-DIOB1) is a
board that provides a simple interface between the STDZ80 Bus and Mostek's Digital liD Bus. It provides parallel,
memory-mapped liD to a maximum of 64 8-bit ports. Using
16 of Mostek's Digital 1/0 Panels (MDX-DIOP), MDXDIOB1 is capable of servicing 256 relay modules.
Figure 2 is a block diagram illustrating the flow of address,
data, and control signals on the MDX-DIOB1. The main
elements of the board are address control, control logic, and
differential bus transceivers and drivers. Input and output
are handled by one 4O-pin connector. A reset signal is
encoded on the Digital 1/0 Bus so all MDX-DIOB1 output
peripherals can be latched to their off state when a
SYSRESET occurs.
ADDRESS DECODE
The address decode circuit is used to enable the board by
comparing the upper ten address bits to preset strapping
options. REFRESH is used in the comparison circiut to
disable the board during a refresh cycle. A strapping option
to include MEMEX is also provided to allow compatibility
with MD systems using this signal.

CONTROL LOGIC
The control logic section is used to generate the control
signals on the Digital liD Bus and to enable the data bus
transceivers in the proper direction. A one wait-state
generator is provided as a strapping option to allow a 4 MHz
operation with extended Digital 110 Bus lengths. All control
logic functions are disabled by the address decode circuit
with the exception of RESET which is enabled at all times.
DIFFERENTIAL TRANSCEIVER AND DRIVER CIRCUITS
The differential transceiver and driver circuits are used to
receive data signals and to transmit address, data, and
control signals. Termination resistors are used at the data
bus receivers to minimize signal reflections on the Digital
liD Bus.
ADDRESS CONFIGURATION STRAPPING
MDX-DIOB1 is address block selectable on 64 byte
boundaries, providing for system flexibility. Address
selection is done by matching the jumper plugs on J3 to the
bit pattern for the desired address block. Inserting a jumper

IVC-71

MDX-DIOB1 BLOCK DIAGRAM
Figure 2

DATA BUS
BUFFER

DIFFERENTIAL
DATA BUS
TRANSCEIVER

8

07-00

DIR

EN

OE

IE

MOSTEK'S
DIGITAL
1/0 BUS

STD-Z80BUS
CONTROL
LOGIC
SEL
ADDRESS
DECODE

+5V

11

A15-A6
REFRESH

CRD
DIFFERENTIAL
ADDRESS
AND CONTROL
BUS DRIVER

ADDRESS AND
CONTROL BUS
BUFFER
1-----'
A5-AO

IVC-72

ONE WAIT-STATE GENERATOR

J3 HEADER PINOUT
Table 1

1- 2

A15

3- 4

A14

The one wait-state generator option is used with 4 MHz
systems when the Digital 110 Bus length is greater than 25
feet. Otherwise, this option is not necessary and can be
omitted by not installing a jumper between pins 3 and 4 on
J4. The maximum recommended Digital 1/0 Bus length for
2.5 MHz or 4 MHz operation is 50 feet.

5- 6

A13

BUSAK TO STATUS 0

7- 8

A12

9-10

A11

11 -12

A10

The BUSAK to STATUS 0 option is used to complete the
priority daisy-chain when multiple DMAs are used in the
system. Since multiple DMAs are not normally used in
Mostek's MD systems, this option can be omitted by not
installing a jumper between pins 5 and 6 on J4.

13-14

A9

SHIPPING CONFIGURATION

15-16

A8

17-18

A7

All jumper locations are shipped open. A set of jumper plugs
is su'pplied in a separate bag. A jumper option can be
strapped using one of these jumper plugs or a wire-wrap
connection.

19-20

A6

PINS

ADDRESS BIT

DIGITAL 1/0 BUS DESCRIPTION
All Digital 1/0 Bus lines are transmitted over balanced
differential. twisted-pair lines with provisions for termination resistors at each end of the bus. This method ensures
adequate noise immunity in industrial environments. A 10pin latching type connector is used to provide positive
locking to the Digital 110 Bus. A 4O-conductor twisted-pair
flat cable is used to interconnect Digital 1/0 Bus peripherals
(Mostek's DIOP) and MDX-DIOB1. Figures:3 and 4 show the
typical configurations for signals found on the Digital I/O
Bus.
.

plug causes the corresponding address bit to be set low. The
header pinout for J3 is defined in Table 1.
MEMORY EXPANSION
A memory expansion option is provided on MDX-DIOB1 to
allow compatibility with systems that use the IMEMEX
signal on the STD. Bus. When this option is used, the
address decode circuit on MDX-DIOB1 will generate its
address select signal only when IMEMEX is active low.
This option can be omitted by not installing a jumper plug
between pins 1 and 2 on J4.

Address Signals
A5-AO are used for port address selection. Each Digital 1/0
Bus peripheral compares these signals to its preset

TYPICAL ADDRESS OR CONTROL LINE
Figure 3

A4

I
I

1
.1
I
I

I
MDX-DIOB1

I
I
I
I

Ai

A4

•••

INPUT
ENABLE
DIGITAI-I/O BUS PERIPHERALS

IVC-73

1000

A4

•

TYPICAL DATA LINE'
Figure 4
7
1000

1.000

•••
07

07

INPUT
ENABLE

07

INPUT
ENABLE
MDX.DIOB1

DIGITAL I/O ,BUS PERIPHERALS

strapping options to generate its address enable and port
select signals. A5·AO are always enabled ori the Oigitall/O
Bus, which means a Oigitall/O Bus peripheral will receive
a valid address even though MOX·010B1 is disabied.This is
of no consequence, however, since the 'controi sighals
generatedbyMDX·DIOB1 will be inactive.'
.
Control Signal!5
CRO ahd CWR are coded control signals. On receipt ofa
CRO command, the port selected by A5·AO will place its
data on 07·00 ofthe Oigitall/O Bus and 110ld itthere until
CRO is released. On receipt of a CWR command, the port
selected by A5·AO will capture the data on. 07·00 of the
Digital I/O Bus at the trailing edge of CWR.lf both CRO and
CWR are 'active, a reset condition occms which clears all
Oigital 1/0 Bus output peripherals. CRO and CWR are
always enabled on the bus and are inactive unless one of
the following conditions exist:
1. MOX·010B1 is enabled
2. SYSRESET is active
3. Oigital J!OBus is open·circuited

Routing
The maximum recommended Oigital 1/0 Bus length for 2.5
MHz operation is 50 feet, with or without the one wait-state'
generator option. For 4 MHz operation, the. maxumim
recommended length is 25 feet 'without the wait-state
option, and 50 feet with the wait-state option. The 40con'ductor twisted-pair flat cable cah be tappedin·10·inch
intervals, and should he laid out ina point-to-point, 'daisy"
chain fashion. Branching from the Oig1tall/0 Bus should be
avoided. Termination resistors (100, 16 pin DIP packages)
should be located only on the 'end of the Oigitall/O Bus.
WARNING: If more than one Oigital 1/0 Bus peripheral
contains termination resistors, damage to the bus drivers
will result.

SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
Word Size

The differenti!'!1 receivers incorporate a fail·safe operation
whioh will activate their outputs whenever their inputs are
open"circuited. Note that this occurence generates a reset
condition.

8 bits
Bus Interface
STD-ZSO BUS
Inputs
Outputs

Data Signals
""

INPUT
ENABLE

07·00 constitute the bidirectional data signals to and from
all Oigitall/O Bus peripherals. These lines are arranged in a
party line configuration on thtt Oigital I/O Bus and are
.always tri-stated unlessMOX-0l081 is enabled.
IVC-74

One 74 LS load maximum
IOl = 24 mA atO.5 V maximum
IOH =-3 mA at 2,4 V minimum
IOZl =-200 pA maximum at 0.4 V
'I OlH = 20 p.A maximumaf2:7V

Connectors

DIGITAL I/O BUS
Inputs
VTH = 0.2 V maximum (differential
input sensitivity)
liN = 1.0 mA maximum
Outputs
IOL = 60 mA at 1.1 V maximum
IOH =-60 mA at 3.5 V minimum
loz = +100 JJA maximum

Functions

Configuration

Mating
Connectors

STO-Z80 BUS

56 pin dual
readout 0.125
in. centers

Printed Circuit
Viking
3VH28/1CE5

Power Supply Requirements
Wire Wrap
Viking
3VH28/1 CND5

+5 V ± 5% at 0.9 A maximum
Operating Temperature Range

Solder Lug
Viking
3VH28/1CN5

O°C to 60°C
Interrupts
DIGITAL
I/O BUS

No interrupt capability
I/O Addressing

Socket Connector 3M 6040
Ansley
40 pin dual
609-4001M
readout 0.100
in. centers

On board programmable on 64 byte boundaries
I/O Capacity
Provides parallel, memory-mapped I/O to a maximum of 64
8-bit ports, or 16 of Mostek's DIOPs
System Clock
250 KHz minimum
4.0 MHz maximum
MECHANICAL SPECIFICATIONS
Card Dimensions
4.5 in. (11.43 cm) high by 6.50 in. (16.51 cm) long
0.675 in. (1.71 cm) maximum profile thickness
0.062 in. (0.16 cm) printed circuit board thickness

IVC-75

II

J2 CONNECTOR PINOUT
Table 3
' Circuit Side

Component Side

Pin Mnem0l1ic Signal
Flow

Pin Mnemonic

Signal
Flow

1
3
5
7
9
11
13.
15

D7B
D6B
D5B
D4B
D3B
D2B
D1B
DOB

In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out

Control
Bus

17
19
21
23

CRDB
CWRB
A5B
AOB

Out
Out
Out
Out

Coded Read
18
Coded Write
20
Low Order Address Bit 22
Low Order Address Bit 24

Address
Bus

25
27
29
31

A4B
A3B
A2B
A1B

Out
Out
Out
Out

Low Order Address
Low Order Address
Low Order Address
Low Order Address

Data
Bus

NOT
USED

Description

High Order Data Bit
High Order Data Bit
High Order Data Bit
High Order Data Bit
Low Order Data Bit
Low Order Data Bit
Low Order Data Bit
Low Order Data Bit

2
4
6
8
10
12
14
16

Bit
Bit
Bit
Bit

26
28
30
32

Description

/D7B
/D6B
/D5B
/D4B
/D3B
/D2B
/D1B
/DOB

In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out
In/Out

Inverted High Order Data Bit
Inverted High Order Data Bit
Inverted High Order Data Bit
Inverted High Order Data Bit
Inverted Low Oi-der Data Bit
Inverted Low Order Data Bit
Inverted Low Order Data Bit
Inverted Low Order Data Bit

/CRDB
/CRWB
/A5B
/AOB

Out
Out
Out
Out

Inverted Coded Read
Inverted Coded Write
Inverted Low Order Address Bit
Inverted Low Order Address Bit

/A4B
/A3B
/A2B
/A1B

Out
Out
Out
Out

Inverted Low Order Address Bit
Inverted Low Order Address Bit
Inverted Low Order Address Bit
Inverted Low Order Address Bit

34
36
38
40

33
35
37
39

ORDERING INFORMATION

DESIGNATOR

DESCRIPTION

PART NO.

MDX-DIOB1

Digital I/O Bus Interface with Technical Manual

MK77672

MDX-DIOB1
Technical Manual

Technical Manual only

4420069

DIOP

Digital I/O Panel

MK79863

IVC-76

I!I

COMPUTER
PRODUCTS
DIVISION

UNITED
TECHNOLOGIES
MOSTEK

DIOP

FEATURES

DIOP

o Provides isolated computer interface to sixteen industrial
I/O channels
o Uses plug compatible solid state or reed relay modules
o Wall or rack mountable
o Digital communication via balanced differential, twistedpair lines
o Industrial barrier strip termination for field wiring
o Fuse holder provided for each relay
o LED status indicator for each relay
o Manual turn-on switch for each relay
o Quick disconnect from field wiring
o Data and data direction registers
o Single +5 volt supply
Figure 2 is a block diagram illustrating the flow of address,
data, and control signals on the DIOP. The four main
elements are the:

o Compatible with Mostek's DIGITAL liD BUS
o Up to sixteen panels allowed on one DIGITAL liD BUS

1)
2)
3)
4)

GENERAL INFORMATION
The DIGITAL I/O PANEL, DIOP, is a DIGITAL liD BUS
peripheral that provides a reliable interface between
Mostek's DIGITAL liD BUS and up to 16 industrial control
signals. Solid state or reed relays are used to isolate the
computer from the industrial signals. Each relay position is
equipped with a fuse holder and LED status indicator. The
relays can also be activated individually with momentary
contact, manual override switches.
DIOP is designed for easy maintenance and low down time.
The relay modules are socketed and can be replaced easily.
The fuse holders for the relays accommodate standard SAG
(one inch) fuses. DIOP also features quick disconnect from
the terminal strip so that the entire circuit board can be
removed from its metal frame. This feature eliminates
having to disconnect and reconnect 32 terminal screws
whenever the board is replaced.

Differential bus transceiver and receiver circuit
Address decode and control logic circuit
Data and data direction registers
Relay ports

Input and output to the board are provided via two 40-pin
connectors. Two connectors allow easy DIGITAL liD BUS
expansion (daisy-chaining). The differential transceiver and
receiver circuits are used to transmit data signals and
receive data, address, and control signals. Sockets for
termination resistors are provided at the receiver inputs so
that the DIGITAL liD BUS can be terminated at the last
DIGITAL liD BUS peripheral on the bus.
The address decode and control logic circuit performs four
functions. First, it enables the board by comparing A4-A 1 to
preset strapping options. Second, it strobes valid data into
the proper data or data direction register during a write
cycle. Third, it generates a left or right relay port select signal
during a read cycle. Fourth, it generates a signal to reset all

IVC-77

BlOC~

DIAGRAM

Figure, 2
LEFT
RELAY
PORT

RIGHT
RELt,Y
PORT

DK1
8

DK8

DK9

DK16

READ DATA
D7, DO

~

16

P;B

-'

D6E

DIFFERENTIAL
DATA BUS
TRANSCEIVER

~

LEFT OR
RIGHT DATA

tDE

~

SELECT

8

~
MOSTEK'S
DIGITAL
1/0 BUS

LEFT OR
RIGHT
SfLECT

STRAPPING
OPTIONS

~41
WRITE DATA
,','

D7

LEFT DATA AND
DATA DIRECTION
REGISTERS

8
DO

ADDRESS
DECODE
LEFT
DATA
STB
fJA4

A1

AD DR
SEL

--a-'

r
D7

RES
LEFT

DATA DIR
STB

RIGHT DATA AND
DATA DIRECTION
REGISTERS

DO
RHT
DATA
STB

RES

RHT
DATA DIR
STB

~

:

16)

A58 AGB
CRDB
CWRB

DIFFERENTIAL
CONTROL AND
ADDRESS BUS
RECEIVER

CONTROL

~
--T

LOGIC

A5,AO
eRD
CWR

the data and data direction registers whenever a SYSTEM
RESET occurs.
The data and data direction registers provide the output to
the two 8-bit relay ports. The left and right data registers
contain the actual output data for their respective relay
ports, while the data direction registers' mask the data
registers from the input relay modules on a bit-by-bit basis,
The output relay channels will be active only when the
corresponding bit in both the data and data direction
registers are in a "1" state. This hardware architecture
supports the read-modify-write and bit control modes found
in the ZOO microprocessor.
The relay ports constitute the 110 interface between the
computer interface logic and the industrial control signals.

Each relay channel has associated with it:
1) Two terminal screws integral to a quick disconnect
barrier strip.
2) A user-selectable8AG (1 inch) fuse.
3) A user-selectable relay module.
4) An LED onloff indicator.
5) A momentary-contact, manual override switch.
Each manual override switch allows the simulation of liD
for debugging and troubleshooting purposes. If a channel is
configured as an output; then a depressed switch will cause
the relay to become active and the LED to light. If the
channel is configured as an input. then a depressed switch
will appear as "1 bit" within the appropriate data register,
but the LED will not light.

IVC~78

J1, J2 CONNECTOR PINOUT
Table 1

Circuit Side

Component Side
Pin Mnemonic

Signal
Flow

Pin Mnemonic Signal
Flow

Description

1
3
5
7
9
11
13
15

D7B
D6B
D5B
D4B
D3B
D2B
D1B
DOB

InlOut
InlOut
InlOut
InlOut
InlOut
InlOut
InlOut

Control
Bus

17
19

CRDB
CWRB

In
In

Coded Read
Coded Write

Address
Bus

21
23
25
27
29
31

A5B
AOB
A4B
A3B
A2B
AlB

In
In
In
In
In
In

Low Order Address
Low Order Address
Low Order Address
Low Order Address
Low Order Address
Low Order Address

NOT
USED

33
35
37
39

Data
Bus

InlOut High Order Data Bit
High Order Data Bit
High Order Data Bit
High Order Data Bit
Low Order Data Bit
Low Order Data Bit
Low Order Data Bit
Low Order Data Bit

Bit
Bit
Bit
Bit
Bit
Bit

Description

2
4
6
8
10
12
14
16

ID7B
ID6B
ID5B
ID4B
ID3B
ID2B
ID1B
IDOB

InlOut
InlOut
InlOut
InlOut
InlOut
InlOut
InlOut
InlOut

18
20

ICRDB
ICWRB

In
In

Inverted Coded Read
Inverted Coded Write

22
24
26
28
30
32

IA5B
IAOB
IA4B
IA3B
IA2B
IA1B

In
In
In
In
In
In

Inverted Low Order Address
Inverted Low Order Address
Inverted Low Order Address
Inverted Low Order Address
Inverted Low Order Address
Inverted Low Order Address

Inverted High Order Data Bit
Inverted High Order Data Bit
Inverted High Order Data Bit
Inverted High Order Data Bit
Inverted Low Order Data Bit
Inverted Low Order Data Bit
Inverted Low Order Data Bit
Inverted Low Order Data Bit

Bit
Bit
Bit
Bit
Bit
Bit

34
36
38
40

J4 CONNECTOR PINOUT
Table 2

Pin Mnemonic

Power
Bus

1
3

+5V
+5V

Signal
Flow
In
In

Pin Mnemonic Signal
Flow

Description

Logic Power Supply
Logic Power Supply

2
4

GND
GND

In
In

Description

Logic Ground
Logic Ground

NOTE:
All signals are referenced to DIOP.

Figure 3 is the mechanical assembly drawing for DIOP. The
four main parts are the frame, side flanges, circuit board,
and cover. The frame and side flanges are constructed of
heavy-duty, black anodized aluminum. The side flanges can
be oriented two different ways to allow wall or rack
mounting of the assembly. The frame also contains the
circuit board stand-offs and quick-disconnect terminal
strips that mate to the edge connectors on the circuit board.
The circuit board is inserted and removed from the frame by
two latching ejectors. The connections to the DIGITAL 1/0
BUS and logic power supply (+5 V and GND) are made on
the circuit board. The pop-off cover is intended to protect the
high voltage lines on the circuit board from stray objects.
MOUNTING
DIOP can be mounted on a wall or a 19-inch rack,

depending on the orientation of the side flanges on the
frame. The location ofthe unit should be chosen so that the
DIGITAL I/O BUS (40-conductor, twisted-pair, flat cable)
length is minimized. When many units are to be connected
to the same DIGITAL 1/0 BUS, the units should be arranged
so that they can be connected in a point-to-point, daisychain fashion with a minimum of cable length. Branching
from the DIGITAL I/O BUS should be avoided. In any case,
the DIGITAL 1/0 BUS should not exceed 50 feet in total
length. Seethe DIOB1 Technical Manual for instructions on
4.0 MHz operation.
CONNECTIONS
The industrial field wiring is connected to terminal strips
located on the metal frame. The fused (positive) line is on the
right side of each terminal pair. The DIGITAL 1/0 BUS can

IVC-79

MECHANICAL ASSEMBLY DRAWING
Figure 3

, REF

'16

~
/

.

4REQ~/

2·REQO·'·

.

,

I

~~16REQD
~4REOD
'-

I

6REOD

be connected to either ofthe 4O-pin headers (J1 and J2).lt is
recommended that a crimp-on connector with a strain relief
be used so that all of the DIOP units can be connected
without splicing the DIGITAL 1/0 BUS. A connector should
never be placed in the twisted sections of the cable, only on
the flat sections. The flat cable should be routed between
units by looping the cable underneath the metal frame of
each unit. Two headers are provided for the DIGITAL 1/0
BUS sothe system can be expanded readily without making
a new cable assembly for the entire DIGITAL 1/0 BUS. The
+5 Vand GND power supply lines are connected to J4. Pin 1
is used for +5 Vand pin 2 is usedforGND. Pins3(+5 VIand
4 (GND) can be used for optional remote sensing.

ADDRESS CONFIGURATION STRAPPING
Header J3 is used to configure the DIOP selection number
when more than one DIOP is used on the DIGITAL VO BUS.
This is done by strapping the proper pins on J3 to match
address bits M-A1 . Table 3 shows how the address bits are
arranged on J3.
J3 HEADER PINOUT
Table 3

FUSING
DIOP provides fuse clips for user-selectable 8AG (1 inch)
fuses for each relay module. Refer to the relay module
manufacturer's specifications for the proper fuse ratings.
RELAY MODULES
DIOP is equipped to handle a variety of plug-in input and
output relays, The different types include solid-state and
reed relays. The user should be aware that certain output
relay modules use zero-cross switching, sometimes a
desirable feature, while others do not offer this feature.
Manufacturers of pin compatible modules include OPTO22, GORDOS, ELEC-TROL, MOTOROLA, and CRYDOM,
The relay modules can be arranged in any mix on DIOP.

Pins

Address Bit

1-2
3-4
5-6
7-8

A4
A3
A2
A1

Strapping respective pins together causes the corresponding address bit to be set low, Table 4 shows all the strappi ng
combinations for J3 that correspond to the 16 possible
DIOP selection numbers on the DIGITAL 1/0 BUS. A "1"
implies that the pins are open, while a "0" implies that the
pins are closed, i.e., strapped. Figure 4 provides an optional
work sheet for the strapping options on J3.
SHIPPING CONFIGURATION
All jumper locations are shipped open. Jumper plugs are
included in a separate bag for user strapping.

IVC-80

DIGITAL I/O BUS DESCRIPTION

POSSIBLE J3 HEADER CONFIGURATIONS
Table 4

Pins
1-2

Pins
3-4

Pins
5-6

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

All DIGITAL I/O BUS lines are transmitted over balanced
differential, twisted pair lines with provisions for termination resistors at each end of the bus. This method
ensures adequate noise immunity in industrial environments. A 40-pin latching type connector is used to provide
positive locking to the DIGITAL I/O BUS. A 40-conductor,
twisted-pair, flat cable is used to interconnect DIOP and
other DIGITAL I/O BUS peripherals to DIOB1. The bus
receivers are equipped with a fail-safe operation which will
reset all data and data direction registers should the bus
cable be interrupted. The data read by the CPU, however,
will be FF. Figure 5 and Figure 6 show the bus
configurations for the signals on the DIGITAL I/O BUS.

DIOP
Pins Selection
7-S Number
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1
2

3
4
5
6
7

WARNING:lf resistor termination packages are located on
more than one DIOP on the same DIGITAL I/O BUS,
damage to the bus drivers will result.

8
9
10
11
12
13
14
15
16

0= CLOSED

1

Address Signals
A4-Al selects which DIOP unit on the DIGITAL I/O BUS
communicates with DIOB1. Each DIOP compares these
four address signals to on-board strapping options to
generate its address enable signal. AO is used to select the
left (AO low) or right (AO high) relay port on the selected
DIOPduring a read or write cycle. A5 is used to select a data
(A5 low) or data direction (A5 high) register on the selected
DIOP during a write cycle. Table 5 shows the address bit
patterns (A5-AO) used to select the ports in a system
containing 16 DIOP units.

=OPEN

ADDRESS STRAPPING OPTION WORKSHEET
Figure 4

Control Signals
+5V
1 -A4

A3
ADDRESS
DECODE
CIRCUIT
A2

2

1
3

4

5

6

1
1
7

A1

J3

1

-

8

CRD and CWR are the coded control signals. On receipt of a
CRD command, the relay port selected by A4-AO will place
its data on D7-DO ofthe DIGITALI/O BUS, and hold itthere
until CRD is released. A5 is a "don't care" signal during a
read cycle. On receipt of a CWR command, the data or data
direction register selected by A5-AD will capture the data on
D7 -DO ofthe DIGITAL I/O BUS atthetrailing edge of CWR.
The coincidence of CRD and CWR both active constitutes a
reset condition which clears the data and data direction
registers on all DIGITAL I/O BUS peripherals. The data
direction registers are write only registers and should be set
by the restart or power-up routine software. The data
registers should be used to manipulate the output data
during normal program execution.
Data Signals
D7-DO serve as the bidirectional data signals to and from all
DIGITALI/O BUS peripherals. These Ii nes are arra nged in a
party-line configuration on the DIGITAL I/O BUS. Table 6
shows the relationship between the relay channel
designators (DK1-DK16) and the data Signals on the
DIGITAL I/O BUS.

IVC-S1

II

TYPICAL ADDRESS OR CONTROL LINE
Figure 6
A4
A4

10011

·1

OUTPUT
ENABLE

'.1

I

I
I

A4

•••

INPUT
ENABLE

I
I
S10 BUS
INTERFACE
BOARO

I

OIOP UNITS

I
I

TYPICAL DATA LINE
Figure 6
07
100!!

100n

07

07

OUTPUT
ENABLE

07

•••

07
INPUT
ENABLE'

STO BUS
INTERFACE
BOARD

DIOP UNITS

ADDRESS BIT PATTERNS FOR DIOP PORT SELECTION
Table 6

..
A&

A4

A3

Q

0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
1
1
1

A2

A1

AO

0

0
0
1
1
0
0
1
1
0

0

.'

0
0
0
0
0
0

O.
0
0
0

0

(j

0
0
1
1
1

1
0
0

0

.,

0

DIOP Port Selected

1
0
1
0
1
0
.1
'0
1

0

,

PANEL NO.1 LEFT DATA PORT
PANEL NO.1 RIGHT DATA PORT
PANEL NO.2 lEFT DAT~ PORT'
PANEL NO.2 RIGHT DATA PORT
PANEL NO.3 LEFT DATA PORT
PANEL NO.3 RIGHT DATA PORT
PANEL NO. 4 lEFT DATA PORT
PANEL NO.4 RIGHT DATA PORT
PANEL NO.5 lEFT DATA PORT
PANEL NO.5 RIGHT DATA PORT
PANEL NO. 6 lEFT DATA PORT

IVC-82

OUTPUT
ENA!JLE

D7
INPUT
ENABLE

ADDRESS BIT PATTERNS FOR DIOP PORT SELECTION (Cont.)
Table 5
A5

A4

A3

A2

A1

AO

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
0
0
0
0
0
0
0

0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0

1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1
1
1

0
1
1
1

1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

1
1
1
1

1
1
0
0
1
1

a
0
1
1
0
0
1
1
0
0
1
1

DIOP Port Selected
PANEL NO.6 RIGHT DATA PORT
PANEL NO.7 LEFT DATA PORT
PANEL NO.7 RIGHT DATA PORT
PANEL NO.8 LEFT DATA PORT
PANEL NO.8 RIGHT DATA PORT
PANEL NO.9 LEFT DATA PORT
PANEL NO.9 RIGHT DATA PORT
PANEL NO. 10 LEFT DATA PORT
PANEL NO. 10 RIGHT DATA PORT
PANEL NO. 11 LEFT DATA PORT
PANEL NO. 11 RIGHT DATA PORT
PANEL NO. 12 LEFT DATA PORT
PANEL NO. 12 RIGHT DATA PORT
PANEL NO. 13 LEFT DATA PORT
PANEL NO. 13 RIGHT DATA PORT
PANEL NO. 14 LEFT DATA PORT
PANEL NO. 14 RIGHT DATA PORT
PANEL NO. 15 LEFT DATA PORT
PANEL NO. 15 RIGHT DATA PORT
PANEL NO. 16 LEFT DATA PORT
PANEL NO. 16 RIGHT DATA PORT
PANEL NO.1 LEFT DATA DIRECTION PORT
PANEL NO.1 RIGHT DATA DIRECTION PORT
PANEL NO.2 LEFT DATA DIRECTION PORT
PANEL NO.2 RIGHT DATA DIRECTION PORT
PANEL NO.3 LEFT DATA DIRECTION PORT
PANEL NO.3 RIGHT DATA DIRECTION PORT
PANEL NO.4 LEFT DATA DIRECTION PORT
PANEL NO.4 RIGHT DATA DIRECTION PORT
PANEL NO.5 LEFT DATA DIRECTION PORT
PANEL NO.5 RIGHT DATA DIRECTION PORT
PANEL NO.6 LEFT DATA DIRECTION PORT
PANEL NO.6 RIGHT DATA DIRECTION PORT
PANEL NO.7 LEFT DATA DIRECTION PORT
PANEL NO.7 RIGHT DATA DIRECTION PORT
PANEL NO.8 LEFT PATA DIRECTION PORT
PANEL NO.8 RIGHT DATA DIRECTION PORT
PANEL NO.9 LEFT DATA DIRECTION PORT
PANEL NO.9 RIGHT DATA DIRECTION PORT
PANEL NO. 10 LEFT DATA DIRECTION PORT
PANEL NO. 10 RIGHT DATA DIRECTION PORT
PANEL NO. 11 LEFT DATA DIRECTION PORT
PANEL NO. 11 RIGHT DATA DIRECTION PORT
PANEL NO. 12 LEFT DATA DIRECTION PORT
PANEL NO. 12 RIGHT DATA DIRECTION PORT
PANEL NO. 13 LEFT DATA DIRECTION PORT
PANEL NO. 13 RIGHT DATA DIRECTION PORT
PANEL NO. 14 LEFT DATA DIRECTION PORT
PANEL NO. 14 RIGHT DATA DIRECTION PORT
PANEL NO. 15 LEFT DATA DIRECTION PORT
PANEL NO. 15 RIGHT DATA DIRECTION PORT
PANEL NO. 16 LEFT DATA DIRECTION PORT
PANEL NO. 16 RIGHT DATA DIRECTION PORT

IVC-83

I/O Capacity

DATA BIT CONFIGURATION
Table 6

Each OIOP provides interface between a maximum of sixteen relay modules and Mostek's OIGITAL I/O BUS.
MECHANICAL SPECIFICATIONS
D!lta
Bit

AO

Relay Channel
Designator

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

OK1
OK2
OK3
OK4
OK5
OK6
OK?
OKS
OK9
OK10
OK11
OK12
OK13
OK14
OK15
OK16

07
06
05
04
03
02
01

DO
07
06
05
04
03
02
01
00

Dimensions
19 in. (4S.26 cm) wide by 7 in. (17.7S cm) high by 2.5 in.
(6.35cm) deep (rack mount).
Connectors
Reference Mating
Designator Connector

Function Configuration
Power

Control

Load

Socket Connector
4 pin, PC mount
0.200 in. centers
2 socket connectors 40 pin dual,
straight 0,100 in.
centers
Edge connector
16 position terminal strip 0.375 in.
centers

J4

AMP
1-480-424-0

J1,2

3M 6040
Ansley
609-4001M

TB1,2

14AWGwire

ELECTRICAL SP':CIFICATIONS

Fusing

Word Size

Equipped with SAG (1 inch)fuse clips for each relay module.

S bits

Relay Sockets

DIGITAL I/O BUS Interface

Figures 7 and S show the pin configurations for relay
modules that are compatible with OIOP. A 4-40 screw is
used to hold each module in place. OIOP is not compatible
with buffered output relay modules.

Inputs

VTH

=0.2 V maximum

liN

= 1:0 mA maximum

(Differential inpllt sensitivity)

Outputs

IOL = 60 mA at 1.1 V maximum
IOH = -60 mA at 3.5 V minimum
loz = ±100 MA maximum

Power S~pply

Require~entS

PIN CONFIGURATION FOR INPUT RELAY MODULES
Figure 7

.04DIA.-

-,
e-e-e

II

+5 V ±5% at 0.9 A maximum

I

e--e--

9-1-1-

~'~

Operating Temperature Range

InterrUpts
No interrupt capability

1.6
1.7

I/O Addressing
On board selectable (four address bits)
IVC-84

there is a vacant 64-byte slot beginning at DOOOH for the
memory-mapped DIOB1. Coincidentally, Header J3 is used
for address strapping both DIOB1 and DIOP.

PIN CONFIGURATION FOR OUTPUT RELAY
MODULES
Figure 8

EXAMPLE STRAPPING
Table 7

Device

DIOB1

Port Address
J3 Address
Data Direction Strapping
Data

DOOO-D01F H

D020-D03F H

DOOOH

D020H

DOO1 H

D021 H

D002 H

D022 H

1+-------1.7 -----+1

DIOP#1
Left Relay Port
(DK1-8)
Right Relay Port
(DK9-16)

SYSTEM, EXAMPLE
This section has been included to illustrate how a basic
DIOB1 IDIOP system could be configured and applied to a
typical industrial control situation. The application chosen
for this example is a motor driven conveyor equipped with
one start push button and seven halt switches distributed
along the conveyor. Also required is a RUNNING light, a
STOPPED light, and a circuit to control the motor starter.

DIOP#2
Left Relay Port
(DK1-8)
Right Relay Port
(DK9-16)

Assuming that it is desired to have the eight inputs
connected to the right relay port of DIOP #1 and the two
outputs connected to the left relay port of DIOP #2, the
following program segments will control the process
described above.
Example Setup
Table 6 shows the required strapping configuration on
DIOB1, DIOP #1, and DIOP #2 and the corresponding HEX
addresses. System memory must be configured so that

0003 H

D023 H

5- 6
9-10
11-12
13-14
15-16
17-18
19-20
1357-

2
4
6
8

1- 2
3- 4
5- 6

Table 8 shows the correspondence between the computer
data bits and the field wiring configuration for the relay
channels used on DIOP #1 and DIOP #2. The inclusion of an
appropriate power source is necessary, of course, but has
been omitted for simplicity.

EXAMPLE FIELD WIRING
TableS

Data Bit

Address

Function

Corresponding Field Wiring

06-00

D001 H

"STOP CONVEYOR" INPUT (HALT BITS)

RELAY 10-16 DIOP #1 EACH WIRED TO MAINTAIN
CONTACT, NORMALLY CLOSED SWITCH

D7

0001 H

"START CONVEYOR" INPUT (START BIT)

RELAY 9 OF DIOP #1 WIRED TO A MOMENTARY
CONTACT, NORMALLY OPEN PUSHBUTTON

D6

0002 H

"STOPPED" INDICATOR
OUTPUT (STOP BIT)

RELAY 2 OF DIOP #2 WIRED TO A RED "STOPPED"
LIGHT

D7

DOO2H

"RUNNING"INDICATOR
OUTPUT (RUN BIT)

RELAY 1 OF DIOP #2 WIRED TO A GREEN
"RUNNING" LIGHT AND MOTOR STARTER

IVC-85

II

EXAMPLE SOFTWARE

LaC OBJ.CODE

STMT-NR

0000'DD21oooo
0Q04 DD3621 00
0008 DD3622EO

2
3

OOOC'DD7E01
OOOFCBBF
0011 DDCB027E
00152011

8
9
10
11

0017 FE7F
00192015
001 B DDCB017E
001 F 280F
0021 DD360280
0025 C33OO0'

13
14
15
16
17
18

oo28'FE7F
oo2A2804
OO2C DD360240

20
21
22

0030'00

24

1

SOURCE- STMT

MOSTEK MACRO-80 22-0CT-80 V2.3 PAGE 1
PASS 2 DIOPEX DIOPEX REL

LD
LD
LD

IX,ODOOOH
(lX+21H),0
(lX+22H),OE OH

; SET DATA DIRECTION REGISTER FOR INPUTS
; AND FOR OUTPUTS

LD
RES
BIT
JR

A,(IX+1)
7,A
7,(lX+2)
NZ,RUNNING

;
;
;
;

CP
JR
BIT
JR
LD
JP

7FH
NZ,EXIT
7,(IX+1)
Z,EXIT
(IX+2),80H
EXIT

; TEST FOR ACTIVE HALT SWITCH(ES)-I.E. LOW
; AND EXIT IF 1 OR MORE ARE
;IS START BIT ACTIVE-I.E. HIGH?
; BRANCH IF NOT
; ELSE SET RUN BIT AND CLEAR STOP BIT

RUNNG

CP
JR
LD

7FH
Z,EXIT
(IX+2),4OH

; TEST FOR ACTIVE HALT SWITCH(ES)-I.E. LOW
; AND EXIT IF ALL ARE INACTIVE
; ELSE CLEAR RUN BIT AND SET STOP BIT

EXIT

Nap

SETUP

POLL

19" RACK MOUNTING HOLE DIMENSIONS
Figure 9

7"

4"

IVC-86

READ INPUTS
CLEAR START BIT (IF ON)
IS RUN BIT ON?
BRANCH IF SO

ORDERING INFORMATION
Designator

Description

Part No.

DIOP

Digital 110 Bus Peripheral with Technical Manual

MK77673

DIOP Technical Manual

DIOP Technical Manual only

4420242

IVC-87

IVC-88

I!I

UNITED

COMPUTER
PRODUCTS
DIVISION

TECHNOLOGIES
MOSTEK

MDX-PIO

FEATURES

MDX-PIO
Figu~1.

o STD-Z80 Bus compatible
o Four 8-bit I/O ports with two handshake lines per port
o All I/O lines fully buffered
o I/O lines TIL-compatible with provisions for termination
resistor networks
o Jumper options for inverted or non-inverted handshake
and Output data buffers drive
o Two 8-bit ports capable of true Bidirectional 110

II

o Programmable In only, Out only, or Bidirectional modes
o Interrupt-driven programmability
o 2.5 MHz or 4.0 MHz options
MDX-PIO DESCRIPTION
The module has four independent 8-bit I/O ports with two
handshake (data transfer) control lines per port. Two of the
8-bit ports are capable of true Bidirectional I/O. All port lines
are brought to two 26 pin connectors, two ports per
connector.
ELECTRICAL SPECIFICATIONS

BUS OUTPUTS

IOH = -3 mA min at 2.4 Volts
IOL

= 24 mA min at 0.5 Volts

TERMINATOR
One 14-pin socket is provided per port for resistor
termination (DIP packages) for the data lines. The parallel
termination is provided for the 8-bit port data lines and the
input strobe (lSTB) handshake line. The MDX-PIO is
shipped with 1K ohm pullup terminators. In addition to the
parallel termination resistors, the ready (RDY) handshake
output line is series terminated with a 47 ohm resistor. The
series termination reduces any reflections on that line.

BUS SPECIFICATION
STD-Z80 compatible
SYSTEM INTERRUPT UNITS
2 total; one for each channel of the MDX-PIO.

I/O CAPACITY
SYSTEM CLOCK

MDX-PIO
MDX-PI0-4

MIN

MAX

500 kHz
500 kHz

2.5 MHz
4.0 MHz

The MDX-PIO uses 8 of the possible 256 port addresses,
leaving 248 port addresses available for expansion by the
user.
I/O ADDRESSING

PARALLEL BUS INTERFACE-STD BUS COMPATIBLE
INPUTS

one 74 LS load max.

Each of the ports has two addresses, one for CONTROL and
one for DATA. The port addresses are derived from the
IVC-89

BLOCK DIAGRAM OF MDX-PIO
Figure 2·

47

ROY

14)

8.

PORTA

14)

------- A7 => 1
>------- A6 => 1
>------- AS => 1
>------- A4 => 1
>------- A3 => 1
1111
1111

PORTA
1000
1001

=>F8H
=>F9H

E26 - DMA DAISY CHAIN
The E26 option is to allow multiple DMA device users to
continue the DMA daisy chain ifthe MDX-PIO was to break
the daisy chain. Mostek doesn't use this option to date.

For more information on the modes of interrupt (Mode 1, 2
and 3) provided by the MDX-PIO module refer to the
MK3881 TECHNICAL MANUAL Pub. No. 78506, and the
STD-Z80 SYSTEM DESIGN GUIDE Pub. No. MK79646.
DAISY CHAIN

P1 STD-Z80 BUS
Pin definition is as shown in Figure 4. See STD-Zao Bus
description for signal functions.
P1 PIN DEFINITION
Figure 7
~!~~~.A..!...

+5V
GND
-5V
D3
D2
D1
DO
A7
A6
A5
A4
A3

A2
A1
AO
IWR
IIORO
IIOEXP
IREFRESH
ISTATUS 1
IBUSAK
IINTAK
IWAITRO
ISYSRESET
ICLOCK
PCO
AUXGND
+12 V

DIIU

DIA.l

~I~"IAI

1
3
5
7.
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55

2
4
6
B
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38

+5V
GND
-5V
D7
D6
D5
D4
A15
A14
A13
A12
A11
A10
A9
A8

40
42

44
46
48
50
52
54
56

Daisy chain priority interrupt logic automatically supplies
the programmed vector (from the highest priority
interrupting peripheral) to the CPU during interrupt
acknowledge. Board priority is determined as an individual
peripheral chip; i.e. through the high or low state of PCI or
PCO. (Figure 7)

APPENDIX A
PARALLEL PRINTER CONFIGURATION
A standard parallel printer can be interfaced to the MDXPIO to run with Mostek provided operating systems. The 1/0
port address is DOH, D3H (1/0 #1), for operating systems
j:LP-80 DOS and M/OS-80.
Install jumpers:
(J3)

3-4
19-20

(J4)

5-6
9-10

IRD
IMEMRO
IMEMEX
IMCSYNC
ISTATUSO
IBUSRO
IINTRO
INMIRO
IPBRESET
ICNTRL
PCI
AUXGND
-12 V

;Buffer direction option header

;Address option header

InstalilC 74LS242 in socket U2 (shipped as 74LS243).
PPG 8/16 PROM PROGRAMMER CONFIGURATION
The Mostek PPG 8/16 PROM PROGRAMMER can be
interfaced to an MDX system with the use of an MDX-PIO
module. The PPG software expects the PIO to be strapped at
DOH and uses the addresses D4-D7H (1/0 #2).
Irstall jumpers:
(J3)

1-2
5-6
9-10
11-12
25-26
33-34

(J4)

5-6
9-10

THE "I" MEANS A LOw ACTIVE SIGNAL.

INTERRUPT SERVICING
If more than one peripheral chip requests interrupt
servicing at the same time, a priority status is established.
Priority is determined by the interrupt enable lines - lEI and
lEO - and the internal logic on each peripheral chip. The
interrupt priority status is defined:

;J3 option header

;Same address as printer
;Address option header

Remove IC UR3 and UR4 (1 K resistor packages).
lEI

o
o
1
1

lEO

0
1
0
1

STATUS
higher priority interrupt being requested
undefined (Not allowed)
requesting interrupt, highest priority
no interrupt
IVC-97

II

PRIORITY INT STRUCTURE
Figu.re8

COMMON
DRAIN
DEVICE
/

PIO#2

PIO#1

PORTI.P.

+5V

EDGE
CONNECTOR
P1

1
PCI 1
1
1

A.

1

B.

2
lEO

r - - .... ~
.",'

PORTI.P.

3
LOWEST
PRIORITY

I

I

I
I

1

I
I

I

I
1

.1
1

I

.1.::
PCOI

I
INTRQ*I

44>-i---

MEMORY DECODE

.
....

&

BUFFER CONTROL

......

/\

RAS
CAS

8-MK4116
16-MK4116

WRITE

4~

4

16Kx8
32Kx8

A

DOUT

DIN

j\
8

7

BUFFER

/\

..

4

ADDRESS

MUX

.

{,1

CONTROL

8

Ii
BUFFER

18\

I

DATA

.BUFFER

I

./\
16,)-

t-

5V

REGULATOR

l--.

~,

~
CONTROL
LINES

l--.

DATA
BUS

ADDRESS
BUS

I I I I

GND +5 +12 -12

JUMPER CONFIGURATIONS
Table 1
BOARD
MDX-DRAM16

-!UMPERS
Bto C

H to J
MDX-DRAM32
(U24 = MK6268)

B to C
E to F
H to J

MDX-DRAM32-4
(U24 = MK6268)

B to C
E to F
H foJ

MDX-DRAM32A
(U24 = MK6280)

Ato B
D to E
H to J

I

MDX-DRAM32A-4
(U24 = MK6280)

Ato B
D to E
H to j

} Same as above

Will notch out EOOO to EFFFH when board is addressed
at 8000H Will be contiguous memory when addressed
at OOOOH.

IVD-2

MK6280
PROM PATTERN
(MMI 6300-1J 256X4)
LOC DATA LOC DATA LOC DATA LOC DATA LOC DATA LOC DATA LOC DATA LOC DATA
20
21
22
23
24
25
26
27

F
F
F
F
F
F
3
3

40
41
42
43

05
06
07

F
F
F
F
F
F
F
F

08
09
OA
OB
OC
OD
OE
OF

3
3
3
F
C
C
C
C

28
29
2A
2B
2C
2D
2E
2F

10
11
12
13
14
15
16
17

F
F
F
F
F
F
F
3

18
19
1A
1B
1C

3
3
3
C
C
C
C
F

00

01
02
03
04

10

1E
1F

45
46
47

F
F
F
F
3
3
3
3

60
61
62
63
64
65
66
67

F
F
3
3
3
3
C
C

80
81
82
83
84
85
86
87

3
7
3
3
C
C
C
C

AO
A1
A2
A3
A4
A5
A6
A7

3
7
C
C
C
C
F
F

CO
C1
C2
C3
C4
C5
C6
C7

C
D
C
C
F
F
F
F

EO
E1
E2
E3
E4
E5
E6
E7

C
D
F
F
F
F
F
F

3
3
C
C
C
C
F
F

48
49
4A
4B
4C
4D
4E
4F

C
C
C
C
F
F
F
F

68
69
6A
6B
6C
6D
6E
6F

C
C
F
F
F
F
F
F

88
89
8A
8B
8C
8D
8E
8F

F
F
F
F
F
F
F
F

A8
A9
AB
AC
AD
AE
AF

F
F
F
F
F
F
3
3

C8
C9
CA
CB
CC
CD
CE
CF

F
F
F
F
3
3
3
3

E8
E9
EA
EB
EC
ED
EE
EF

F
F
3
3
3
3
C
C

30
31
32
33
34
35
36
37

F
F
F
F
F
3
3
3

50
51
52
53
54
55
56
57

F
F
F
3
3
3
3
C

70
71
73
74
75
76
77

F
7
3
3
3
C
C
C

90
91
92
93
94
95
96
97

3
7
3
C
C
C
C
B

BO
B1
B2
B3
B4
B5
B6
B7

3
D
C
C
C
F
F
F

DO
D1
D2
D3
D4
D5
D6
D7

C
D
C
F
F
F
F
F

FO
F1
F2
F3
F4
F5
F6
F7

C
F
F
F
F
F
F
F

38
39
3A
3B
3C
3D
3E
3F

3
C
C
C
C
F
F
F

58
59
5A
5B
5C
5D
5E
5F

C
C
C
F
F
F
F
F

78
79
7A
7B
7C
7D
7E
7F

C
F
F
F
F
F
F
F

98
99
9A
9B
9C
9D
9E
9F

7
7
7
7
F
F
F
3

B8
B9
BA
BB
BC
BD
BE
BF

F
F
F
F
F
3
3
3

D8
D9
DA
DB
DC
DD
DE
DF

F
F
F
3
3
3
3
C

F8
F9
FA
FB
FC

F
3
3
3
F
C
C
C

44

72

IVD-3

AA

FD

FE
FF

II

MK6268

PROM PATTERN
(MMI6300-1J 256X4)

LOC DATA LOC DATA LOC DATA LOC DATA LOC DATA LOC DATA LOC DATA LOC DATA

45
46
47

F
F
F
F
7
7
7
7

60
61
62
63
64
65
66
67

F
F
7
7
7
7

7
7
9
9
C
C
F
F

48
49
4A
48
4C
40
4E
4F

9
9
C
C
F
F
F
F

30
31
32
33
34
35
36
37

F
F
F
F
F
7
7
7

50
51
52
53
54
55
56
57

F
F
F
7
7
7
7
9

38
39
3A
3B
3C
30
3E
3F

7
9
9
C
C
F
F
F

58
59
5A
58
5C
50
5E
5F

9
C
C
F
F
F
F
F

05
06
07

F
F
F
F
F
F
F
F

20
21
22
23
24
25
26
27

F
F
F
F
F
F
7
7

08
09
OA
08
OC
00
OE
OF

7
7
7
7
9
9
C
C

28
29
2A
28
2C
20
2E
2F

10
11
12
13
14
15
16
17

F
F
F
F
F
F
F
7

18
19
1A
18
1C
10
1E
1F

7
7
7
9
9
C
C
F

00

01
02
03
04

40
41
42
43
44

80
81
82
83
84

7
7
7
7
9

AO
A1
A2

A3
M

A5
A6
A7

7
7
9
9
C
C
F
F

CO
C1
C2
C3
C4
C5
C6
C7

9
C
C
F
F
F
F

EO
E1
E2
E3
E4
E5
E6
E7

C
C
F
F
F
F
F
F

F
F
F
F
F
F
7
7

C8
C9
CA
C8
CC
CO
CE
CF

F
F
F
F
7
7
7
7

E8
E9
EA
E8
EC
EO
EE
EF

F
F

DO

05
06
07

9
C
C
F
F
F
F
F

FO
F1
F2
F3
F4
F5
F6
F7

C
F
F
F
F
F
F
F

08
09
OA
08
OC
00
OE
OF

F
F
F
7
7
7
7
9

F8
F9
FA
FB
FC
FO
FE
FF

F
7
7
7
7
9
9
C

9
9

85
86
87

C
C

68
69
6A
68
6C
60
6E
6F

C
C
F
F
F
F
F
F

88
89
8A
88
8C
80
8E
8F

F
F
F
F
F
F
F
F

70
71

77

F
7
7
7
7
9
9
C

90
91
92
93
94
95
96
97

7
7
7
9
9
C
C
F

85
86
B7

7
9
9
C
C
F
F
F

78
79
7A
7B
7C
70
7E
7F

C
F
F
F
F
F
F
F

98
99
9A
98
9C
90
9E
9F

F
F
F
F
F
F
F
7

88
B9
BA
B8
BC
80
BE
BF

F
F
F
F
F
7
7
7

72

73
74
75
76

IVD-4

9

A8
A9
AA

A8
AC
AO
AE
AF
BO
B1
B2
B3
B4

01
02
03
D4

9

7

7
7
7
9
9

reside on any 4K boundary, ooooH, 1OOOH, 2000H, 3000H,
and so on.

MEMORY DECODING
Table 2

STD Bus Interface
STARTING ADDRESS

0000
1000
2000
3000
4000
5000
6000
7000
8000
9000

AOOO
BOOO
COOO
DOOO
EOoo
FOOO

U28 SWITCH POSITION

1

2

3

4

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

IOH

System Clock

MDX-DRAM
MDX-DRAM-4

Min
1.25 MHz
1.25 MHz

Max
2.5 MHz
4.0 MHz

Power Supply Requirements
+5 V ± 5% at 0.6 A max.
+12 V ± 5% at 0.25 A max.
- 12 V ± 5% at 0.03 A max.
Operating Temperature

o to 60 degrees C
MECHANICAL SPECIFICATIONS

1 = Open

0= Closed

One 74LS load max.
= -3 rnA min. at 2.4 volts
IOL = 24 rnA min. at 0.5 volts

Inputs
Outputs

Card Dimensions

Word Size: 8 bits

4.5 in. (11.43 cm) high by 6.50 in. (16.51 cm) long
0.48 in. <1.22 em) maximum profile thickness
0.062 in. (0.16 em) printed-circuit-board thickness

Memory Size

Connectors

ELECTRICAL SPECIFICATIONS

MDX-DRAM16 - 16,384 bytes
MDX-DRAM32A - 32,768 bytes
Function

Configuration

STD BUS

56-pin dual
0.125-in. centers

Mating
Connector

Access Times

SYSTEM
CLOCK

MEMORY
ACCESS
TIMES

MEMORY
CYCLE
TIMES

MDX-DRAM
2.5 MHz
MDX-DRAM-4 4.0 MHz

350 ns max.
200 ns max.

465 ns min.
325 ns min.

Address Selection
Selection of 16K or 32K contiguous memory blocks to

IVD-5

Printed Circuit
Viking
3VH28/1CE5
Wire wrap
Viking
3VH28/1CND5
Solder Lug
Viking
3VH28/1CN5

ORDERING INFORMATION

DESIGNATOR

DESCRIPTION

PART NO.

MOX-ORAM16

16K Bytes (4116'5) 2.5 MHz

MK77754-0

MOX-ORAM32A

32K Bytes (4116'5) 2.5 MHz

MK77752-0

MOX-ORAM16-4

16K Bytes (4116'5) 4.0 MHz

MK77754-4

MOX-ORAM32A-4

32K Bytes (4116'5) 4.0 MHz

MK77752-4

MOX-ORAM Technical
Manual

MOX-ORAM Technical Manual Only

4420033

IVD-6

COMPUTER
PRODUCTS
DIVISION

~ TECHNOLOGIES

UNITED

MOSTEK

MDX-EPROM/UART

FEATURES

o

STD Bus compatible

o

Three 24-pin sockets for 2K x 8 ROM/EPROM device

o

Memory addressing selectable or 2K boundaries

o

Full-duplex UART

MDX-EPROM/UART
Figure 1

• Start bit verification
• Data word size variable from 5 to 8 bits
• One or two stop bits may be selected
• Odd, even, or no parity option
• One word buffering on both transmit and receive
• RS232 and 20 rnA interface
• 110 to 19,200 Baud
GENERAL DESCRIPTION
The MDX-EPROM/UART is a STD BUS-compatible
microcomputer module. Designed as a universal EPROM
add-on module for the STD BUS, the MDX-EPROM/UART
provides the system designer with sockets to contain up to
10K Bytes of EPROM memory (five 2716s) as shown in the
Block Diagram, Figure 2. The EPROM memories can be
positioned to start on any 2K boundary within a 16K block of
memory via a strapping option. Included on-board the MDXEPROM/UART is a fully buffered asynchronous 1/0 port
with a teletype reader step control. A full-duplex UART is
used to receive and transmit data at the serial port.
Operation and UART options are under software control.
Once the unit has been programmed, no further changes
are necessary unless there is a modification of the serial
data format.

ROM/EPROM - 2K blocks jumper selectable for any 2K
boundary within a given 16K boundary of the CPU
memory map
Memory Speed Required without wait states (Address
Access)
2716 (Single +5 V type required) - 515 ns
265 ns
I/O Addressing
On-board fully programmable
System Clock
MDX-EPROM/UART
MDX-EPROM/UART-4

SPECIFICATIONS
Electrical Specifications

2.5 MHz
4.0 MHz

Min.
250 kHz
250 kHz

Power Supply Requirements
+ 12 Volts ± 5% at 50 rnA max.
- 12 Volts ± 5% at 35 rnA max.
+ 5 Volts ± 5% at 1.2 A max.

STD Bus Compatible
Memory Addressing
IVD-7

Max.
2.5 MHz
4.0 MHz

MEMORY DECODING JUMPER SELECTION
Table 1
JUMPERS
E1 - E6

J2JUMPERS
DECODED
ADDRESS

EPROM
U17

EPROM
U18

J2
0000-07FF
OBOO-OFFF
1000-17FF
1800-1FFF
2000-27FF
2BOO-2FFF
3000-37FF
3BOO-3FFF
4000-47FF
4BOO-4FFF
5000-57FF
5BOO-5FFF
6000-S7FF
6BOO-SFFF
7000-77FF
7BOO-7FFF
BOOO-87FF
8BOO-8FFF
9000-97FF
9BOO-9FFF
AOOO-A7FF
ABOO-AFFF
BOOO-B7FF
BBOO-BFFF
c000-C7FF
CBOO-CFFF
DOOO-D7FF
DBOO-DFFF
EOOO-E7FF
EBOO-EFFF
F000-F7FF
FBOO-FFFF

Pin
16

to

..

..
..
..
..
..
..
..

..
..
..
..
..
..
..
..
..
..
..

..
..
..-

..
..
..
.-

..
..
..
..

J2

Pin
1
2
3
4
5
6

"7
B

.,

1
2
3
4
.5
6

7
B
1
2
3
4
5
6
7
B
1
2
3
4
5
6
7
B

Pin
15

..
..
..

..
..
...
..
..
..
..
..
..
...
..
..

..
..
..
..
..
".

..
..
..
..
.-

..
..
..

to

EPROM
U20

EPROM
U19

J2

J2

Pin
1
2
3
4

5
6
7
B
1
2
3
4
5
6
7
B
1
2
3
4
5
6
7
B
1
2
3
4
5
6
7
B

Pin
14

..
..
..

..
..
..
..
..
..
..
..

..
..
...
..

..
.-

..

..
..
..
..-

..
.-

..

..
..
..
..

to

EPROM
U21

Pin
1
2
3
4
5
6
7
B
1
2
3
4
5
6
7
B
1
2
3
4
5
6
7
B
1
2
3
4
5
6
7
B

IVD-8

Pin
13

..

..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..

to

J2

Pin
1
2
3
4
5
6
7
B
1
2
3
4
5
6
7
B
1
2
3
4
5
S
7
8
1
2
3
4
5
S
7
B

Pin
12

..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..

to

Pin
1
2
3
4
5
6
7
B
1
2
3
4
5
6
7
B
1
2
3
4
5
6
7
B
1
2
3

E1 to E6
and
E4 to E5

E1 to E6
and
E3 to E5

E2 to E6
and
E4to E5

4

E2 to E6
and
E3 to E5

5
6
7
B

j

MDX-EPROM/UART BLOCK DIAGRAM
Figure 2

ADDRESS AND CONTROL BUS

r-------.

en

-i

o

CXI

c
en

BUS
INTERFACE
LOGIC

MEMORY
SELECTION
LOGIC

EPROM/ROM
SOCKETS (5)

PORT
SELECTION
LOGIC

RS-232
AND
20MA
BUFFERS

UART

20MAINPUT
OUTPUT AND
READER STEP
RS-232
INPUT. OUTPUT
AND
MODEM
CONTROL

Serial 1/0; 26 pin dual. 0.100 in. grid
Mating Connectors
FLAT RIBBON - Ansley 609-26ooM
DISCRETE WIRES - Winchester PGB26A(housing)
Winchester loo-7oo29S
(contacts)

Operating Temperature Range

o to 60°C
Mechanical Specifications

UTILIZATION

Card Dimensions

EPROM Decoding Jumpers
4.5 in. (11.43 cm) high by 6.5 in. (16.51 cm) long
0.48 in. (1.22 cm) maximum profile thickness
0.062 in. (0.16 cm) printed circuit board thickness

Jumper Options for the EPROM decoding are shown in
Table 1.

1/0 Port Decoding Jumpers

Connectors

The port decoding for the EPROM/UART board is jumper
programmable to allow multiple EPROM/UART boards
within an MDX system. The EPROM/UART board uses
three Read/Write ports to interface to the UART. Figure 3
shows the format for strapping the I/O decoder.

STD Bus; 56 pin dual. 0.125 in. centers
Mating Connectors
PCB - Viking 3VH28/1 CE5
WIREWRAP - Viking 3VH28/1 CND5
SOLDER LUG - Viking 3VH28/1 CN5

8 BIT I/O ADDRESS DECODING
Table 2
I/O PORT ADDRESS BITS
A7 A6

OPERATION
PERFORMED

A5

A4

A3

A2

Al

AO

READ

WRITE
UART
DATA

X

X

X

X

X

X

0

0

UART
DATA

X

X

X

X

X

X

0

1

UART
UART
STATUS CONTROL

X

X

X

X

X

X

1

0

MODEM MODEM
STATUS CONTROL

X

X

X

X

X

X

1

1

NOT
USED

X = PROGRAMMABLE
IVD-9

NOT
USED

1/0 ADDRESS STRAPPING
Figura 3

14

1
----- 0

A7

2
-----0

A6

3
-----0

A6

11

4
-----0

Not Used

10

5
-----0

A2

9

6
-----0

A3

8

7
-----0

A4

13
12

'STRAP = LOGIC 0

NO STRAP = LOGIC 1

EXAMPLES:
Strap board so that serial channels occupy 1/0 ports 0,1, and 2.

J4

140-----01
130

02

120

03

11 0

04

100

05

90

06

80

07

Strap board so that serial channels occupy ports FC, FD, and FE.

J4

140

01

130

02

120

03

110

04

100

05

90

06

80

07

IVD-10

Baud Rate Selection

BAUD RATE SWITCH SELECTION
Table 3

The Baud rate for the serial interface is generated by the
Baud rate chip U7. The Baud rate is selected by DIP switch
U8. Table 3 shows DIP switch setting versus Baud rates.

U8SWITCH
POSITION
4
2
1
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

Programming the UART
A full-duplex UART is used to receive and transmit data at
the serial port. Operation and UART options are under
software control. Once the unit has been programmed, no
further changes are necessary unless there is a
modification of the serial format. Transmit and receive clock
rates (Baud clock rate) must be 16 times the desired Baud
rate. A programming model for the UART is shown in Figure

4.

1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

=OPEN

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

X16
CLOCK
.8KHz
1.2
1.76
2.152
2.4
4.8
9.6
19.2
28.8
32.8
38.4
57.6
76.8
115.2
153.6
307.2

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0= CLOSED

PROGRAMMING THE UART
Figure 4
1. UART DATA PORT DCH
Write to Port DCH
Read from UART
2. UART CONTROL PORT DDH
Write to UART
Read from UART
3. System Control Port DEH
Write to Port DEH
Read from Port DEH

DATA TO SERIAL DEVICE
DATA FROM SERIAL DEVICE

I TSB I NP I EPS I NB21 NB,
ITBMTI DAV I OR I FE I PE

l><1>2

h~Y ~:

04

06

357

JUMPERS FOR USING 27588

p~~
3

5

1

0

3

5

7

J5-J8

4

J1-J4

h~Y

OS

7

J5-J8

1

5

10----<>2

JUMPERS FOR USING 27168
OR MK34000

1

J1-J4

p~~

3

JUMPERS FOR USING MK41188

J1-J4

J5-J8

J1-J4

3

5

10--02
30--04

50

06

7

JUMPERS FOR USING MK48028

10---02
3~

50

04

Los

7

JUMPERS FOR USING 27328

IVD-18

MEMORY SIZE SELECTION JUMPERS
MEMORY DEVICE JUMPERS
Table 1

MEMORY SOCKETS

CONTROLLING JUMPERS

U4,U8

J4,J8

U3,U7

J3,J7

U2,U6

J2,J6

Ul,U5

Jl,J5

The size ofthe MDX-UMC memory can be adjusted by the
use of Jl0. Before configuring the Jl0 jumpers, be sure
that the memory device jumpers are in place. Figure 4
shows the possible combinations of Jl0 versus memory
size.

MEMORY SIZE JUMPERS
Figure 4

RELATIVE ADDRESS

8000
U5
7000
U1

III

6000
U6
5000
U5

U1

U1

U6

U6

U2

U2
4000

U1
U6
U2
U7

U5
U5
U1

3000

U5
U1
U6

U1
U6

U6

U2

U2

U1
U6
U2
U7
U3

U6
U2

2000
U7

U7

U2

~'

- 3
10 5
- 7

x
x
x
x

0
~

U7

Z

w

Q.

U7
U3

U3

0

U3

0

U3
w
....
III

U7
U8

U8

U3
U3
U8
0000- U4

..,:>

U7

U8

'~-I

~

w
Q.
:i!



x

0

0

0

x

0

0

0

x

0

x
x
x

IVD-19

0

0

0

0

0

0

0

x

x

0

0

0

0

x

0

0

x

0

0

0

x

0

x
x

0

x

0

~

w
Q.
:i!
:>
::l

cw
Vl

9U
"
"

MEMORY DEVICE AND SIZE JUMPER
EXAMPLES (Cont.)

MEMORY DEVICE AND SIZE JUMPER EXAMPLES
Figure 5

Figure 5
2

4

6

8

ld-!
3

J10

J1-J4

J5·J8

1

cr---o 2

:~

04
06

7

5

J5-J8

1~2

2
30------<> 4
50

06

70

08

4

lr~
3

8K X 8 EPROM MEMORY USING 2758.

J1-J4
8

6

1

cr---o 2

:~

J1-J4

2

4

6

8

lr~
3

1

:~

7

5

2

10

02

3cr---<>4

04
06

06
30
5

J10

cr---o 2

10----02

7

5

J5-J8
J5-J8

J10

04

50------<> 6
70------<> 8

4

J1-J4

6

04

0-------0 S

70

08

8

!-hl (~:
357

COMBINATION 8KX 8 EPROM AND 4K X 8 SRAM (SEE FIGURE 4
FOR MEMORY ALLOCATION)

16K X 8 EPROM MEMORY USING 2716. OR MK34000.

MEMORY DECODING
J5-J8
2

4

J10

J1-J4

6

8

lr~

02

10

02

04

30

04

Los

50

06

10

3~
50

357

Memory decoding for the MDX-UMC is on 4K boundaries,
i.e. OOaH, 1aaaH, 200aH, and so on. The starting address
for the MDX-UMC is selected by a four position jumper
block, J11. Table 2 shows the jumper setting for J11 versus
starting address.

7 0------<> 8

MEMORY DECODING
Table 2

32K x 8 EPROM MEMORY USING 2732.

Starting Address
J1-J4

J5-J8
2

4

6

8

h~l
3

5

1~2

~

4

6

h~l
3

5

7

a

1

a

a

a

2

a

a

a

06

os

70

08

MSB -

1

2

3

4

a

a

a

a - LSB

1

a

1

a

1

a

a

a
a

1

a

a

a

a

1

a

a

a

a

a

3

a

a

a

4

a

a

a

1

a

a

a

a

a

a

a

a

a

10---02

10

30--0 4

3cr---<>4

5
6
7
8
9

a

a

a

a

50

50----06

A

a

a

a

a

B

a

a

a

a

a

1

C

a

a

a

a

a

a

D

a

a

a

a

a

E

a

a

a

a

a

F

a

a

a

a

a

J10

J1-J4
8

a

50

8K X 8 SRAM USING MK4118.

2

a

30------<> 4

7

J5-J8

a

0'

30----04
5

J11 Jumper Position

J10

06

02

70----08

16K X 8 SRAM USING MK4802.

a = JUMPERED
IVD-20

a

1 = OPEN

a
a

WAIT STATE GENERATOR
Since most MOS EPROMs cannot meet the required 275 ns
accesstoallowthe MDX-UMCtoworkat4 MHz, a one wait
state generator has been provided. Figure 5 shows how to
enable the wait state generator for each memory socket. An
example of how to enable the wait states for every memory
socket is shown in Figure 6.

ENABLING THE WAIT STATE GENERATOR

Address Selection: Selection of 4K, 8K, or 16K
contiguous memory blocks to reside on any 4K boundary,
i.e. OOOH, 1000H, 2000H, 3000H, and so on.
PARALLEL BUS INTERFACE-STD BUS COMPATIBLE:
one 74LS load max
IOH =-15 mA min at 2.4 volts
IOL =24 mA min at 0.5 volts

Inputs
Bus Outputs

System Clock:

Figure 6

STATE FOR

4MHz

Power Supply Requirements:

MEMORY IN
SOCKET

MAX

MIN
250 KHz

MDX-UMC

ADD ONE WAIT

CONNECT JUMPER BElWEEN

U4

J9

15T01S ....

U8

J9

13 TO 14

U3

J9

11 TO 12

U7

J9

9TO 10

U2

J9

US

J9

7TO 8 (
5TO S

U1

J9

3TO 4

U5

J9

1 TO 2 )

+5 volts ±5% at 0.450A max (Does not include memories)
MECHANICAL SPECIFICATIONS

>AND E2

Card Dimension:
4.5 in (11.43 cm) high by 6.50 in. (16.51 cm) long
0.48 in. (1.22 cm) maximum profile thickness
0.062 in. (0.16 cm) printed circuit board thickness
Connectors:

EXAMPLE FOR ENABLING ONE WAIT STATE FOR
EACH MEMORY SOCKET

Function

Configuration

Mating Connector

Figure 7
J9

0
0
0
0
0
0
0
0

STD BUS

0
0
0
0
0
0
0
0
AND
E2

Operating Temperature:

Maximum Memory Device Access Time
Clock

ELECTRICAL SPECIFICATIONS

2.5 MHz
4.0 MHz

8 bits

Memory Size:
EPROM
8K x 8 using 2758
16K x 8 using 2716
32K x 8 using 2732

O°C to 60°C

REQUIRED MEMORY DEVICE ACCESS TIME

~
Word Size:

Printed Circuit
56 pin dual read out Viking 3VH28/1 CE5
Wire wrap
Viking 3VH28/1 CND5
0.125 in. centers
Solder Lug
Viking 3VH28/1 CN5

RAM
8K x 8 using MK4118
16K x 8 using MK4802

ROM
16K x 8 using MK34000
IVD-21

No Wait States

One Wait State

530 ns
275 ns

930 ns
525 ns

.ORDERING INFORMATION

Designator

Description

Part Number

MDX-UMC

MDX-UMC module with Technical Manual (less mating
connectors)

MK77759

MDXcUMC
Technical·
Manual

Technical Manual only

4420084

:<1

IVD-22

IJ

UNITED
TECHNOLOGIES
MOSTEK

COMPUTER
PRODUCTS
DIVISION

MDX-UMC2

FEATURES

MDX-UMC2
Figure 1

o STD-Z80 bus compatible BYTEWYDE memory card

o

Up til 64K bytes of RAM, ROM, and EPROM in any mix

o

Supports bank switching when multiple boards are used

o

Board may function as common memory in a bank
switched system

o

Jumper option allows bank switching through any port

o

Jumper option allows board to be selected upon system
reset in multibank systems

o

Jumper option allows memory to begin on any 4K
boundary

o

WAIT states selectable on a per socket basis

o

2.5 or 4 MHz operation

o

Eight 28-pin sockets are provided which may be strapped
to accept any combination of the industry-standard
memory devices shown in Table 1

MEMORY DEVICES THAT MAY BE USED ON
MDX-UMC2
Table 1

EPROM

STATIC RAM

ROM

2716 (2K x 8) MK4118A(1K x 8) MK34000 (2K x 8)
2732(4Kx8) MK4801 (1 K x 8)
MK37000 (4K x 8)
2764(8Kx8) MK4802 (2K x 8)
MK38000 (32K x 8)
27128 (16K x 8
27256 (32K x 8)

MD~-UMC2

DESCRIPTION

The MDX-UMC2 features eight 28-pin memory sockets
which enable the user to populate the module with any
combination of designated ROM, RAM, and EPROM.
Flexible address decoding allows the user to configure each
memory device within any 1K boundary of the memory
block on board. The memory block may start on any 4K
boundary of any (or all) of eight64K banks. A PROM decoder

is supplied which will allow the user to choose one of eight
preselected memory configurations or, by programming a
decoder PROM, the user can assign any of the eight sockets
to memory addresses as required by his application needs.
To ensure sufficient memory access time at 4 MHz
operation, a jumper option enables automatic insertion of
one WAIT state for those memory devices identified as
"slow" in the decoder PROM. The standard decoder PROM
supplied with MDX-UMC2 identifies RAMs as "fast" parts
(no WAIT states) and ROMs and EPROMs as "slow" parts
(one WAIT state).
Also provided on the MDX-UMC2 is the circuitry to enable
the board to be used in a multibank system. The board may
occupy one entire 64K bank or as little as 1K of a 64K bank.
The MDX-UMC2 can be used to provide the common
memory in a multibank system. Bank selection is
accomplished through writing to a user defined port. Each
bit in the port activates a single bank, for example, bit 0 set
enables bank 0, bit 1 set enables bank 1, etc. The user may
strap the board to reside in anyof the eight ban'ksc For use as
the common memory in a multibank system, the MDXUMC2 must be jumpered so that it is active when any bank
is selected. A header is provided for this purpose. The user
may strap the board so that it wiff be active or inactive upon
system reset.

IVD-23

MDX-UMC2 BLOCK DIAGRAM
Figure 2
~



t
DATA
BUFFERS

BANK SWITCH
PORT DECODE
AND
LOGIC

;L--

~1
CHIP ENABLE
LOGIC

t--

'""--

\.

~

"-.7--=lZ "",2

11

t\.

\

BUFFERED DATA

./

MEMORY
SOCKET
BLOCK

~

-.;:

\

MEMORY
OPTION
HEADER

-I

!::oo

MECHANICAL SPECIFICATIONS

System Interrupt Units:

Card Dimensions:

This board does not generate any interrupts.

4.50 in. (11.43 cm) wide
6.50 in. (16.51 cm) long
0.675 in. (1.71 cm) maximum profile thickness
0.062 in. (0.16 cm) printed .circuit board thickness

Operating Temperature:

o to 60 degrees C.

STD Bus Edge Conne~or: .
56-pin dual readout; 0.125 in. centers
Mating Connectors:
PCB - Viking 3VH28/1 CE5
WIRI;WRAP - Viking 3VH28/1 CND5
SOLDER LUG - Viking- 3VH28/1 CN5

Power Supply Requirements:
5 V ± 5% @ 1 .1 A (excluding memory power requirements)

CONNECTORS AND OPTION HEADERS
ELECTRICAL SPECIFICATIONS
STD-Z80 Bus Compatible

For the location of all.~onnectors and option headers, see
Figure 3 •.

IVD-24

BOARD OUTLINE AND HEADER LOCATION

J1 PIN DEFINITION

Figure 3

Figure 4

SIGNAL
+5V
GNO
-5V
03
02
01
00
A7
A6
A5

J8
1
J20
J4

J3
1

I

2

'0

9

71

3

J9

5

I I

62

6

J6
2 J5
10

U

15

J10

16

J13

J14

J15
J7

10
J1

The

Active/lnactive on Reset

This header determines whether the MOX-UMC2 becomes
active or inactive upon system reset. The memory bank
selected to act as system boot memory in a bank switched
system should become active upon reset, while all other
banks should be inactive. For the board to be active upon
reset, place jumper from pin 1 to pin 2. For the board to be
inactive, place jumperfrom pin 2 to pin 3.lfthe board is to be
used in a non bank switched system, a jumper should be
placed between pins 1 and 2 as shown in the example.
Shipping configuration is with no jumpers installed.

SIGNAL

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36 *
38 *
40*
42 *
44 *
46 *
48 *
50 *
52
54 *
56 *

+5V
GNO
-5V
07
06
05
04
A15
A14
A13
A12
A11
A10
A9
A8
IRO
IMEMRO
IMEMEX
IMCSYNC
ISTATUS 0
IBUSRO
IINTRO
INMIRO
IPBRESET
ICNTRL
PCI
AUXGNO
-12

"*"

indicates signals not used on MDX-UMC2

within a given bank, so the starting address takes on the
form XOOO hex. See Table 2 for starting addresss jumper
configurations.
MEMORY STARTING ADDRESS
Table 2
STARTING 1 * * * * 7 STARTING 1 * * * * 7
ADDRESS
ADDRESS
(HEX)
(HEX)
2 * * * * 8
2 * * * * 8

EXAMPLE:

0000
1000
2000
3000

4000
5000
6000
7000

The board will be active upon reset.
J3

PIN

STD-Z80 BUS

Pin definition is as shown in Figure 4. See STO-Z80 Bus
description for signal functions.
J2

*

A4
A3
A2
A1
AO
IWR
IIORO
IIOEXP
IREFRESH
ISTATUS 1
IBUSAK
IINTAK
IWAITRO
ISYSRESET
ICLOCK
PCO
AUXGNO
+12 V

J11

J12

J1

PIN

Memory Starting Address

This header determines the starting address for the on
board memory. The memory may begin at any 4K boundary
IVD-25

0000
1000
o 100
I lob

00 I 0
1010
01 10
I I 10

I = JUMPER IN PLACE

8000
9000
AOOO
BOOO
COOO
0000
EOOO
FOOD

000
100
010
I 10
001
101
01 I

I
I
I
I
I
I
I
I I I I

o = PINS LEFT OPEN

III

as common memory. Pins 1-,6 determine the bank in which
the on-board memory will reside as defined in Figure 5. If
the board is to act as common memory in a bank switched
system, insert a jumper between pins 9 and 10, otherwise
insert a jumper between pins 7 and S. If the board is not to
be used in a bank switched system, all pins on this header
may be left open (shipping configuration).

* * * * 7

EXAMPLE:

J3

2****S
The starting address is 0000 hex (shipping configuration).
J4

Memory Map Option Select

This header selects one of eight possible memory maps for
the memory on the MDX-UMC2. The hexadecimal
equivalent of the jumper sequence on J4 corresponds tothe
memory map selected. Ajumper in place asserts a logic "0",
while no jumper in place indicates a logic "1".

J5 JUMPER OPTIONS
Figure 5
1 •

8
I

* * * 5

EXAMPLE:

888
I, I I
T T T

B
I

J5

* 10

PLACE JUMPER HERE IF BOARD IS
TO BE COMMON MEMORY
PLACE JUMPER HERE IF BOARD
IS NOT TO BE COMMON MEMORY

1 * * * * * 9
BANK 2

1 2

The binary number represented by the jumper sequence
above is 111 or 7 hexadecimal so map 7 is selected
(shipping configuration). For map definitions, see Table 3.
J5

B
I

210

2 * * * 6

L:

*

T T T

J4

o

• 9

2 •

* * * * * 10 BANK 2 * * * * * 10
I I I
I 10
I 01
I 00

0
1
2
3

Bank Select and Common Area Decode Header

This header selects the 64K bank in which the MDX-UMC2
resides and determines whether or not the board shall act

1 * * * * * 9

4
5
6
7

I = JUMPER IN PLACE

01 I
010
001
000

o = PIN5 LEFT OPEN

MEMORY MAP DEFINITION
Table 3

MAP OPTION

0

SOCKET
SIZE
U14
U 15
U 16
U 17
U 18
U 19
U20
U 21

ADDR

1K
1K
1K
1K
1K
1K
1K
lK

2

1

0000

0400
0800
OCOO
1000
1400
1800
1COO

SIZE
2K
2K
2K
2K
2K
2K
2K
2K

S
5
5
S
S
5
S
S

ADDR

SIZE

0000
OSOO
1000
lS00
2000
2S00
3000
3S00

4K
4K
4K
4K
4K
4K
4K
4K

5
S
S
S
S
S
S
S

3
ADDR

SIZE

0000
1000
2000
3000

8K
SK
8K
SK
2K
2K
2K
2K

4000
5000
6000
7000

ADDR
S
S
S
S

0000
2000

4000
6000

8000
8S00
9000
9S00

MAP OPTION
4

SOCKET
SIZE
U14
U 15
U16
U 17
U18
U19
U 20
U 21

16K
16K
2K
2K
2K
2K
2K
2K

S
5

ADDR

SIZE

0000

32K
2K
2K
2K
2K
2K
2K
2K

4000
8000
8800
9000
9S00
AOOO
ASOO

S

7

6

5
ADDR

SIZE

0000
SOOO
SSOO
9000
9800
AOOO
ASOO
8000

32K
2K
2K
2K
2K
2K
2K
2K

S
S
S
S

ADDR

SIZE

0000
SOOO
SSOO
9000
9S00
AOOO
ASOO
FSOO

SK
8K
8K
2K
2K
2K
2K
2K

ADDR
S
5
S
S
S

THE "5" INDICATES THAT THE DECODER PROM IDENTIFIES THESE PARTS AS "5LOW".

IVD-26

0000
2000

4000
8000
SSOO
9000
9S00
F800

EXAMPLE:

EXAMPLE:

2

*

*

*

*

*

*

I *I *I

*

9

*

10

1*

J5

The board will reside in bank 4 for use in a bank switched
system. Common memory will reside on some other
memory card in the system. For the board to become active,
bit 4 of the byte written to the bank switch port must be set
to a logic "1" while all other bits contain a logic "0".
J6

Bank Select Port Address

This set of jumpers selects the address of the port through
which bank switching is accomplished. The port address
will be the hexadecimal equivalent ofthe jumper sequence.
Insert a jumper to assert a logic "0"; leave jumper off to
indicate a logic "1 ".
EXAMPLE:
*

*

*15
J6

*

*

B B

I I
T T
7 6

--- -

*

*16

B

B

I
T
1

I
T
0

The hexadecimal equivalent of the jumper sequence is FF,
so the port is located at address FF hex (shipping
configuration).
J7

J7

WAIT states are disabled (shipping configuration).
JB-J15

Socket Configuration Headers

These headers allow the user to configure each memory
socket (U14-U21 respectively) so that it will accept one of
the standard memory parts listed under the heading
'FEATURES'. The required jumpers for each of these parts
are shown in Table 4.
For information on configuring the memory sockets for
other types of memory components, see the heading
"MEMORY SOCKET CONSIDERATIONS".
MEMORY SOCKET CONSIDERATIONS

1*
2*

*2

WAIT State Enable

This header enables WAIT states for memory parts
identified as "slow" in the decoder PROM. A jumper
between pins 1 and 2 of J7 will enable WAIT states.

The UMC2 card will accept many memory components
other than those listed under the heading 'FEATURES'. The
following information is provided to aid the user in
configuring the memory sockets for components other than
those listed. Each of the eight memory sockets have the pin
configuration as shown in Figure 6. The numbers inside the
parentheses are pin numbers for 24-pin memory
components. When 24-pin packages are used, the memory
should occupy the bottom part of the socket leaving pins 1,
2, 27, and 28 open.
The pins indicated by the "*" are "option pins". These pins
may be defined by the user so that the socket will accept a
particular memory type. This is accomplished by inserting
jumpers into the socket configuration header (J8-J15)
adjacent to the memory socket. The function of each pin of
the header is shown in Figure 7.

STANDARD MEMORY SOCKET CONFIGURATIONS
Table 4
MEMORY

JUMPERS REQUIRED

JUMPERS REQUIRED

MEMORY

4118A

1
2

*-* * *-* * * 13
* * * * * * * 14

27128

1 *I
2 *

4801

1
2

*-* * *-* * * 13
* * * * * * * 14

27256

1
2

*I * *I * * *-* 13
* * * * 1 * * 14

4802

1
2

*-* * *-* * * 13
* * * * * * * 14

34000

1
2

*-* * * * * * 13
* * * * * * * 14

2716

1
2

*-* * * *-* * 13
* * * * * * * 14

37000

1
2

* * * * *I * * 13
* * * * * * * 14

2732

1
2

*-* * * * * * 13
* * * * 1 * * 14

38000

1
2

!*

2764

1
2

* *-* * * *-* 13
* * * * ! * * 14
IVD-27

*-* * * *-* 13
* * * 1 * * 14

* * * 1 * i 13
* * * * * * 14

III

MEMORY ACCESS TIMES

MEMORY SOCKET PIN CONFIGURATIONS
Figure 6

The table below indicates the required access times for
memory components for operation at 2.5 MHz and 4 MHz. If
the component's access time is greater than that shown in
Table 5, one WAIT state will be required. One WAIT state
will add 250 ns to the required memory access time at 4
MHz. One WAIT state will add 400 ns to the required
memory access time at 2.5 MHz.

A12
A7
A6

A8

A5

A9

A4
A3

IOE

REQUIRED MEMORY ACCESS TIME

A2

A10

Table 5

A1

ICE

AO

07

DO

06

01

05

02

04

GNO

03

ACCESS TIMES REQUIRED

PIN FUNCTION OF J8-J15
Figure 7

SYSTEM
CLOCK

ICE TO DATA

IOE TO DATA

2.5 MHz

<438 ns

<425 ns

4.0 MHz

< 188 ns

< 175 ns

2

1

MEMORY SOCKET PIN 26 -

*

* -

V CC -

*

* -NOTUSED

MEMORY SOCKET PIN 27 -

*

* --A14 BUFFERED FROM BUS

WRITE ENABLE (/WE) -

*

* -NOTUSED

MEMORY SOCKET PIN 23 -

*

* - - A 11 BUFFERED FROM BUS

V CC -

*

* -NOTUSED

MEMORY SOCKET PIN 1 -

*

* --A14 BUFFERED FROM BUS

13

A 13 BUFFERED FROM BUS

14

ORDERING INFORMATION

DESIGNATOR

DESCRIPTION

PART NO.

MDX-UMC2

Universal Memory Card (less memory and mating connectors)

MK-77763

MDX-UMC2
Technical
Manual

Technical Manual only

4420319

IVD-28

I!

COMPUTER
PRODUCTS
DIVISION

UNITED

TECHNOLOGIES
MOSTEK

MDX-BRAM

FEATURES

MDX-BRAM
Figure 1

D 2K or 4K bytes of memory

D 4K boundary selection
D Same board used with 2.5 MHz or 4.0 MHz systems

D Rechargeable batteries
D 4K of memory sustained for at least five days with fully

charged batteries
D Wait state circuit allows sufficient access time for RAMs

GENERAL DESCRIPTION
The MDX-BRAM is one of Mostek's complete line of STD
Bus-compatible laO microcomputer modules. The MDXBRAM is desig ned to save up to 4K bytes of memory duri ng
a power fa i lure. Power degradation is detected by either the
resident 5 volt monitoring circuitry or an external powerfail
detect module (MDX-PFD). When a power failure is
detected, the on-board battery power is enabled to retain
memory data.
The MDX-BRAM provides 4K bytes of random access
memory (RAM). The addressing of the board is jumper
selectable on 4K boundaries within a 64K address space.
The MDX-BRAM2 provides 2K bytes of RAM.
The board has a DC power monitor circuit to detect when
the 5 volt supply line is lower than a specified value. It also
contains the interface circuitry to monitor an external signal
(lSYSRESET) indicating a power failure has been detected
by the MDX-PFD module. When a power failure is detected
by either method, battery power is enabled and all access to
the board is blocked until primary power is restored.

directly from the buffer to the array, and the other six
(A 1a-A 15) go through a compare circuit for the board
address and a decode circuit to form the four chip select
signals.
Control and II F Circuit
The block generates the IWE, SYSPF, and data direction
signals from the IRD, IWR, IWREQ, and ISYSRESET
signals.
Data Buffer

Battery power is supplied by three NiCad cells which can
provide enough energy to retain memory data for up to five
days. An on-board battery charging circuit is provided to
ensure the batteries are kept fully charged while the board
is in use. Duration of data retention may be considerably
less when the batteries are not fully charged. An MDXBRAM Block Diagram is shown in Figure 2.

The data into the board is buffered by a 74LS245. The bus is
normally turned into the board, and is turned out for a read
operation. The bus is normally enabled but is disabled
during the system reset or power fail. This is doneto prevent
an invalid write to memory during power down and power
up.

Address Decoder and Buffer

Memory Array

All the address lines are buffered. The first ten (AO-A9) go

The memory array consists of CMOS RAMs. These RAMs

IVD-29

M[}X;SRAIIIf"BLOCK DIAGRAM
,Flglire' 2" .. ','. \'

F
)

A1~\'
I .
AOI

.4-CHIP SEL
& 10ADDRESS
BITS

ADDRESS
DECODE &
BUFFER

MEMRQ

.t..

)

RD,WR, \
MREQ.
SYS RESEY
+5. +12

WE. SYS, P.F .•

CONTROL
. & I/FCIRCUIT

+5. +12

BATIERY
CIRCUIT
&
P.F. DETECT

V'

BUS RD
-

M

W
L
)

DATA
BUFFER.' .

-WAIT

WRITE
ENABLE &
V BAlB

~/
MEMORY
ARRAY
4K x B

WAIT
STATE
GEN

~~

I

BUS EN

4-CHIP
SEL

~'.

I
\

8 BITS OF DATA

are 1K x 4 bits in an eighteen pin pac«,age; they have a 300
nsec access tiine' and a standby current drain of 50
microamps. The array is organized into logical pairs for each
of the four chip selects. The total array when fully populated
is4K x 8 bits.

at ambient) and remains below 4.85 volts (maximum) for
more than four microseconds. When this occurs, the board
will block all access to the memory array. When the 5 volt
supply rises above 4.85 volts, this circuit will again allow
access to the memory.

Battery Circuit and Power Fail Detect

WARNING: This circuit contains a potentiometer which
should not gimerally be set in the field. It is set at the factory
and requires equipment which may not be available to the
user. Changing the setting of this circuit will void the
warranty. If it is changed inadvertently, the following
procedure may be used to reset it.

The battery'charg'er circuitcian be viewed as three circuits
which are overlaid to form one circuit. The first circuit (the
major source of charge) is from the +12 V supply and
provides a nearly consta nt input of approximately 9 mA. The
second circuit comes from the +5 V line which will provide a
rioininal9 mA and is' cut off toa' very small trickle as the
batteries become Hilly charged. The third circuit is the
discharge circuit which provides a low resistance path (120
ohms) or at most a diode drop when the VBAT current drain
is large. The zener protects the CMOS circuitry if +5 V drops
out and +12 Vis still present. In addition, note that the VBAT
is provided anytime +5 V is present This provision protects
the CMOS circuits by providing power to the CMOS
whenever an input is possibly present.
- Three AAAsize NiCads supply power to the memory for five
days when fully charged. It will take at least twenty-four
hours of operation to charge the batteries to full capacity.
The power fail detect circuit will detect when the 5 volt
. supply-to the board falls below 4.7 volts (the factory setting

1. Adjust the 5 volt power supply to 4.70 volts.
2_ Connect an oscilloscope or a voltmeter to the output
(pin 4) of the·ICLB211 (m 2).
3. Adjust R2 until the voltage on pin 4 goes toan active
level (>2.4 V).
4. Slowly' adjustthe pot in the opposite direction until the
voltage goes low (>.7 V).
5. Readjust the 5 volt supply to 5 volts.
This circuit is also 'for the detection of /SYSRESET signal
(pin 47 on the STD-Z80 Bus); when this signal is active, all
access is blocked. This allows the board to interface to the
power fail detect board (Mostek Part Number MK77760).
The power fail detect board will detect A.C. power failures
and "brown-outs" and give an early warning signal to the
CPU to allow an orderly shut-down of the system.

IVD-30

The circuit also does memory access blocking. If a power
failure is detected, either on this board or on the MDX-PFD,
this circuit will prevent any bus access to the board. This
turns off all interface of address, data, and read and write
control signals and access is blocked as long as the
ISYSRESET is asserted or the 5 volt supply is below 4.85
volts.
Wait State Generator
The wait state generator will insert one WAIT state during
an access ofthe board to allow for the 300 nsec access time
of the CMOS RAM.

(enabled when IMEMEX is high), then J7-3 to 4 is
jumpered.
WAIT STATE
The Wait State Jumper (located at J6-1 to 2) will normally
be installed; however, if faster CMOS RAMs (sub 200 nsec
for 4 MHz, and sub 350 nsec for 2.5 MHz) are used, this
jumper may be removed to eliminate the wait state added to
each memory access. (Note that the jumper may be
removed for 2.5 MHz systems using the RAMs provided
with the board.)
MEMORY SIZE

BOARD ADDRESS
Starting memory addressing for the MDX-BRAM is
selectable on 4K boundaries, i.e., OOOOH, 1OOOH, 2000H,
and so on. The starting address is selected using four
jumper positions located at J5. Table 1 shows the jumpers
to be used for various starting addresses.
ADDRESS JUMPERS

These four jumpers will select only those 1 K increments of
memory the user needs.

Table 1

Address

1-2

3-4

5-6

7-8

0
1
2
3
4
5
6
7
8

Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N

Y
Y
Y
Y
N
N
N
N
Y
Y
Y
Y
N
N
N
N

Y
Y
N
N
Y
Y
N
N
Y
Y
N
N
Y
Y
N
N

Y
N
Y
N
N
N
Y
N
Y
N
Y
N
Y
N
Y
N

9

5 VOLT ONLY

Jumpers installed at J5

Most Significant Hex

A
B
C
D
E
F

Four jumpers may be installed, depending on the memory
size. When 1 K of memory is installed (U4 and U8 only),
jumper J4-1 to 2 is in place. With 2K of memory(U3, U4, U7,
and U8), install jumpersJ4-1 to 2 andJ4-3 t04, andJ4-5 to
6. When all 4K of memories are installed (U1 through U8),
place all four jumpers as follows: J4-1 to 2, J4-3 to 4, J4-5
to 6, and J4-7 to 8.

AjumperatJ2-1 t02 is installed ifand only if the system is
operated with a 5 volt only supply, that is, if a 12 volt supply
is unavailable. It should be noted, however, that this mode
increases the charge time to 36 hours for full charge at
25°C.
BATTERY DISCONNECT
To remove the batteries from the circuit (for removal or
addition of CMOS IC socketed on the board orfor prolonged
storage of 2 to 3 months), the jumper J3-1 to 2 will need to
be removed. (Note: this jumper is not factory-installed and
should be inserted before use.)
ELECTRICAL SPECIFICATIONS
System Clock

MIN

MAX

250 kHz

4.0 MHz

Add jumper for 'V' and remove jumper for 'N'
IMDX-BRAM

MEMORY EXPANSION

Bus Interface-STD-Z80 Compatible

IMEMEX (pin 36 on the STD-Z80 Bus) is not used by the
Mostek MDX-CPU1 and MDX-CPU2 and is held low by the
backplane. The jumper at J7 allows use of this board in
systems that do incorporate this feature. For the MDXBRAM to provide primary memory (lMEMEX is low),
jumper J7-1 to 2 is used; if it is not primary memory

Inputs:
Outputs:

IVD-31

One 74LS load max
IOH = -3 mA min at 2.4 volts
IOL = +24 mA min at 0.5 volts

III

Power Supply Requirements

MECHANICAL SPECIFICATIONS

+12 Volts ±5% at.2 A max
+5 Volts ±5% at 1.0 A max
-9 mA max on standby battery

Card Dimensions

Battery Type Used

4.5 in. (114.3 mm) wide by 6.5 in. (165.1 mm) long
0.675 in. (17.1 mm) maximum profile thickness
0.062 in. (1.6 mm) printed circuit board thickness

3 AAA NiCads supplies with card

Connectors

Battery Life

Three years or 200 full charge/discharge cycles (whichever
is less)

Connector
Function

STD BUS

Word Size

Configuration

Connectors

56 Pin dual read out
0.125 in. centers

Printed Circuit
Viking 3VH28/1 CE5

Data: 8 bits
I/O Addressing: 16 bits, jumper selection on 4K boundary
Access Time

Wire Wrap
Viking
3VH28/1 CND5
Solder Lug
Viking 3VH28/1 CN5

Less than 400 nsec
Operating Temperature Range

o to 60°C
Power Failure Detection Level

A power failure is registered when:
1. The 5 volt supply level drops below 4.7 volts and is
then held less than 4.85 volts maximum for more than
4 microseconds, or
2. When the /SYSRESET signal is active.

ORDERING INFORMATION

Designator

Description

Part Number

MDX-BRAM4

MDX-BRAM4 module with Technical Manual (4K memory)

MK77760

MDX-BRAM2

MDX-BRAM2 module with Technical Manual (2K memory)

MK77762

MDX-BRAM
Technical Manual

Technical Manual only

4420066

IVO-32

IJ

. COMPUTER
PRODUCTS
DIVISION

UNITED

TECHNOLOGIES
MOSTEK

MDX-RAM 64/128

FEATURES

o

MK77765
Figure 1

STO-ZSO Bus compatible

o 64K (MDX-RAM64) or 12SK (MDX-RAM12S) bytes of
dynamic RAM
o +5 V only operation
o Automatic refresh accomplished through use of STOIREFRESH signal

zao

o 2.5 MHz or 4.0 MHz operation with no wait states
o Bank switching accomplished via a user designated I/O
port
o Bank switching is hardware compatible with MDXUMC2, MDX-CPU3, and MDX-CPU4
o Common memory area for bank switched systems may
reside at any 256 byte boundary within the 64K memory
map
o Common area size is user defined in 256 byte
increments
o Common area can be made resident on any board
o Option allows the board to become active upon system
reset for use as the system boot memory
o MEMEX and 10EXP are supported, polarity for each is
user defined

MDX-RAM DESCRIPTION
The MDX-RAM card features a capacity of 64K or 12SK
bytes of dynamic memory, and wi" support selection of
multiple 64K banks under software control. Provision is
made for an area of memory which will be common to a"
64K banks, useable for operating system or applications
software which is needed by a" banks. The bank select
structure is the same as that used on MDX-CPU3, MDXCPU4, and MDX-UMC2 and is compatible with commercially
available software packages. The board will function in 2.5
MHz and 4.0 MHz STD-ZSO systems with no WAIT states.
MDX-RAM has features designed to simplify implementation of multi-user operating systems such as MP/MTM* or
TM*

Digital Research
Infosoft

MULTI/OSTM**. One of S banks of 64K bytes each is
selected by writing a "1" to one of S bits at the bank switch
port location. Setting bitOwi" select bankO, setting bit 1 wi"
select bank 1,and so on. Only one bank may be selected at a
time. The actual bank switch port address may be jumper
selected to reside at one of 256 locations. In addition,
IMEMEX is decoded as a board enable (polarity jumper
selectable) to double the number of banks that may be
selected at each port location. IIOEXP is decoded as a port
enable (polarity jumper selectable) to double the number of
bank select port locations. A special option allows the user
to select the board as the default system boot memory on
reset without prior software intervention, enabling the
board to be used as a standard 64K board without special
software.
To facilitate switching from one bank to another, a special
common memory area has been provided. This area of
memory remains enabled regardless of which memory
bank has been selected. The user may place a software
monitor in this common memory area for commul'1icating
data between banks. This guarantees that the monitor wi"
still be available when a new bank is selected. The common
area may begin on any 256 byte boundary within the 64K
memory map and is size selectable in 256 byte increments.

TM**

IVD-33

BLOCK DlAGRAM MDX-RAM
Figure 2

a

DATA
BUF

a

0
A
T
A

a

RAS/CAS/WR ADDRESS

a
BANK
SWITCH
LOGIC

S
T
D

MEMORY ARRAY

RAS
MUX
CAS

J
a

z

a

o

~a

COMMON
AREA
DECODE

-

B
U

S
16

fa

ADDR
BUF

16

ADDR
MUX

MISC
LOGIC

CNTRL
BUF

In addition. an option has been incorporated to allow the
common area to reside on any board in the system. One
board in the system must be selected to contain the
common area.

System Interrupt Units
No interrupts are generated by this board.
Operating Temperature

Memory refresh circuitry has been provided on board. and
makes use of the STO-Zao IREFRESH signal. Memory will
be refreshed even if it does not reside in the curre,ntly
selected bank.

o to 60 degrees C
Power Supply Requirements

In addition. PCI is connected to PCO for preserving the,Zao
interrupt priority chain.

MDX-RAM64 +5 V ± 5% @ 2.0 A MAX
MDX-RAM 128 +5 V ± 5% @ 2.6 A MAX

MECHANICAL SPECIFICATIONS

CONNECTORS AND HEADERS

Card Dimensions

For the location of all connectors and option headers. see
Figure 3.

4.50 in. (.11.43 cm.) wide by 6.50 in. (16.51 cm.) long
0.675 in. (1.71 cm.) maximum profile thickness
0.062 in. (0.16 cm.) printed circuit board thickness
STD BUS Edge Connector
56 pin dual readout; 0.125 in. (0.32 cm.) centers
Mating Connectors:
PCB -Viking 3VH28/1CE5
WIREWRAP - Viking 3VH28/1 CND5
SOLDER LUG - Viking 3VH28/1 CN5
ELECTRICAL SPECIFICATIONS
STD-Z80 Bus Compatible

J1

STD-Z80 Bus 56 Pin

For J1 pin definition. see Figure 4. (See STD-ZaO, Bus
description for Signal functions).
J2

Bank Select Header

This header determines which banks of memory will reside
on board. The odd numbered pins correspond to the eight
bits in the bankswitch port. Twoofthe even numbered pins
correspond to the enables of the tvyo 64K rows of memory
that may reside on. board. Two of the even numbered pins
are reserved for future expansion. The function of each pin
IVD-34

J1 PIN FUNCTION
Figure 4

HEADER AND CONNECTOR LAYOUT
Figure 3

1 2

1 2

J5D J6D
J1

SIGNAL

PIN

+5V
GNO
-5V
07
06
05
04
A15
A14
A13
A12
A11
A10
A9
A8
IRO
IMEMRO
MEMEX
IMCSYNC
ISTATUS 0
IBUSRO
IINTRO
INMIRO
IPBRESET
ICNTRL
PCI
AUXGNO
-12 V

2
4
" 6
8
10
12
14
16
18
20
22
24
26
28
30
32
34

36
• 38
• 40
• 42
• 44

" 46
• 48
• 50
52
• 54
• 56

PIN
1

3
5"
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39 •
41 "
43 •
45 "
47
49 *
51
53 *
55 *

SIGNAL
+5V
GNO
-5V
03
02
01
DO
A7
A6
A5
A4
A3
A2
A1
AO
IWR
IIORO
IOEXP
IREFRESH
ISTATUS 1
IBUSAK
IINTAK
IWAITRO
ISYSRESET
ICLOCK
PCO
AUXGNO
+12

The ..... indicates signals not used
on MOX-RAM.

is shown below. To select the banks that will reside on
board, place a jumper between the designated row enable
and the bank select port bit that it should respond to.
EXAMPLE:
J2

If U1-U8 are populated with 4564 RAM's (MDX-RAM64),
only row may be used. To make this row respond to bank
2, place a jumper between pins 5 and 6.

a

2

BANKO--- *
BANK 1 --- *
BANK 2--- *
BANK3---*
BANK 4--- *
BANK 5--- *
BANK 6--- *
BANK 7--- *
15

• --- NO CONNECTION
• --- NO CONNECTION
" --- ROW 0 (64K RAMI
" --- ROW 1 (64K RAMI
" --- RESERVED
• --- RESERVED
• --- NO CONNECTION
• --- NO CONNECTION
16

J3 IOEXP, MEMEX, Reset Status, Common
Memory Location

Row a may be used only if U1-U8 are populated with 4564
RAM's (MDX-RAM64 or MDX-RAM128).
Row 1 may be used only if U9-U16 are populated with 4564
RAM's (MDX-RAM 128).
EXAMPLE:
If U1-U16 are populated with 4564 RAM's (MDXRAM 128), both rows of memory may be used, rows aa nd 1 .
To make these rows respond to banks 3 and 4 respectively,
place a jumper between pins 6 and 7 and ajumper between
pins 8 and 9.

This header selects the polarities of IOEXP and MEMEX that
the board will respond to, whether or not the board will
become active upon system reset, and whether or not the
common memory area will reside on board or on some
other board in the system. Place jumper between pins 1 and
2 to cause the board to respond to a logic a on IOEXP, or
between pins 3 and 4 to cause the board to respond to a
logic f. If the host system does not support IOEXP, leave
pins 1 through 4 open. A jumper between pins 5 and 6
indicates that the common memory area will reside on
board.lfthisjumper is in place and the address bus contains
an address within the range defined by J5 (common
memory ending address) and J6 (common memory starting
address), the memory in U1-U8 will become active. If this
jumper is not in place and the address bus contains an
address within range defined by J5 and J6, no memory on
the MDX-RAM will become active. Place ajumper between
pins 7 and 8 to cause the board to respond to a logic a on

IVD-35

MEMEX, or between pins 9 and 10 to cause the board to
respond to a logic 1. If the host system does not support
MEMEX, leave pins 7 through 10 open. A jumper between
pins 11 and 12 will cause the board to become active upon
system reset. If this jumper is in place and a system reset
has occurred, the memory in U1-U8will become active and
will remain active until the bank select port is written to. If
the address is within the common memory boundaries, the
memory in U1-U8 will become inactive so that the memory
designated to be the common memory may be accessed.

J5

Common Area Ending Address

This header determines the ending address for the common
memory area. The upper boundary of the common area
takes on the form XXFF hex, so the common memory may
end at the top of any 256 byte page. A jumper in place
asserts a logic "0", while no jumper in place indicates a
logic'''''.
EXAMPLE:

EXAMPLE:

J5

2
J3

"---BITO

2
* -- > BOARD ACTIVE WHEN IOEXP = 0
* -- > BOARD ACTIVE WHEN IOEXP = 1
• -- * -- > JUMPER IN FOR COMMON ON BOARD
* -- > BOARD ACTIVE WHEN MEMEX = 0
* -- > BOARD ACTIVE WHEN MEMEX = 1

"--- BIT 1

*--- BIT 2
* --- BIT3
" --- " --- BIT 4
"--- BITS
BIT6
"

• -- • -- > JUMPER IN FOR ACTIVE ON RESET
11

12

15

As shown above, the board will become active when an
address within the common memory area is accessed or
when a system reset occurs. Since pins 1-4 and 7-10 are
left open, the logic levels of IOEXP and MEMEX are ignored.

BIT7

16

The binary number represented by the jumpers is
11101111, or EF hex, so the common area will end at EFFF
hex.
J6

J4

__0

"000

Common Area Starting Address

Bank Select Port Address
This header determines the starting address for the
common memory area. The common area lower boundary
takes the form of XXOO hex, so common memory may begin
with any 256 byte page. A jumper in place asserts a logic
"0", while no jumper in place indicates a logic "1".

This header selects the address of the port through which
bank switching is accomplished. The port address will be
the hexadecimal equivalent of the jumper sequence. A
jumper in place will assert a logic "0", while no jumper in
place indicates a logic "1".

EXAMPLE:
EXAMPLE:
J6
J4

2
2
"---BITO

000

"

000

"

000

"

000

*

" --- " --- BIT 1
" --- * --- BIT 2

" --- * --- BIT 3

*--- BIT 4

000

"

000

"

000

*
*
"

000

000

000

"000

*--- BIT6

"000

"--- BIT6

"000

*--- BIT 7
16

"

16

BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT5
BIT6
BIT7

16

16

The binary number represented by the jumpers is
11100000, or EO hex, so the common area will begin at
EOOO hex.

The binary equivalent of the jumper sequence is 11110001
binary of F1 hex, so the port address is F1 hex.

IVD 36
o

ORDERING INFORMATION

DESIGNATOR

DESCRIPTION

PART NO.

MDX-RAM64

64K byte dynamic memory card with bank switch capability
with Technical Manual

MK77764

MDX-RAM128

128K byte dynamic memory card with bank switch capability
with Technical Manual

MK77765

MDX-RAM
Technical Manual

Technical Manual only

4420291

IVD-37

IVD-38

1983 COMPUTER PRODUCTS DATA BOOK

.

: ;<

MD Series Special Functions

~,

,

.. ,',

.

'.

:"~'

"

;

,',

'-;

~ TECHNOLOGIES

UNITED

COMPUTER
PRODUCTS
DIVISION

MOSTEK

MDX-DEBUG
M K77950-0, M K77950-4

HARDWARE FEATURES

o
o
o
o

MDX-DEBUG BOARD PHOTO
Figure 1

STD-Z80 BUS compatible
4 MHz version available
Serial I/O Channel
10K bytes of ROM contain the following firmware:
DDT-80, ASMB-80

DEBUGGER FEATURES

o Z80 Operating System with debug capability
o Channelized I/O for versatility
o I/O peripheral drivers supplied
o ROM-based
TEXT EDITOR FEATURES

o Input and modification of ASCII Text
o Line and character editing

o Alternate command buffers for pseudo- macro command
capability

o ROM-based
ASSEMBLER FEATURES

o Assembles all Z80 mnemonics
o Object output in industry-standard hexadecimal format
extended for Relocatable and Linkable Programs

o Over fifteen pseudo-ops
o Two-pass assembly
o ROM-based
LINKING LOADER FEATURES

interface and is available in both 2.5 MHz and 4.0 MHz
version. Included on-board is a fully buffered asynchronous
I/O port capable of 110-19200 Baud rates. Serial data
interfaces are available for 20 mA current loop(with readerstep control) and RS-232. The on-board Baud Rate
Generator is selectable to all common Baud rates from 110
to 19,200 Baud. The address of the serial port is selectable
via 6 on-board jumpers.

o Loads into memory both relocatable and non-relocatable
object output of the assembler

DEBUGGER DESCRIPTION

o Loads Relocatable modules anywhere in memory
o Automatically provides linkage of global symbols
between object modules as they are loaded
o Prints system load map
o ROM-based
HARDWARE DESCRIPTION
The MDX-DEBUG module has sockets for 10K bytes of
masked ROM that are filled with a Z80 firmware package
(DDT-80/ASMB-80). This module has a STD-Z80 BUS

DDT-80 is the Operating System for the MDX-DEBUG
Module, residing in a 2K ROM (MK34000 Series) on the
module itself. It provides the necessary tools and
techniques to operate the system, i.e., to efficiently and
conveniently perform the tasks necessary to develop
microcomputer software. DDT-80 is designed to support
the user from initial design through production testing. It
allows the user to display and update memory, registers,
and ports, load and dump object files, set breakpoints, copy
blocks of memory, and execute programs.

IVE-1

•

MDX-DEBUG BLOCK DIAGRAM
Figure 2

ADDRESS AND CONTROL BUS

20 mA INPUT
OUTPUT AND
READER STEP
BUS
INTERFACE
LOGIC

MEMORY
SELECTION
LOGIC

ROM FIRMWARE
DDT·80 AND ASM8·80
RS·232
INPUT, OUTPUT
AND
MODEM CONTROL

DATA BUS

DDT-SO COMMAND SUMMARY
M s
M s, f
Ps
D s, f

L
Es
H
C s, f, d

Bs

Rx

MEMORY, PORT AND REGISTER COMMANDS
(M,P,R)

- Display and/or update the contents of
memory location s.
Tabulate the contents to memory locations s
through f.
Display and/or update the content of I/O
ports.
- Dump the contents of memory locations s
through f in a format suitableto be read by the
Lcommand.
- Load, into memory, data which is in the
appropriate format.
- Transfer control from DDT-80 to a user's
program starting at location s.
- Perform 16-bit hexadecimal addition and/or
subtraction.
Copy the contents of memory locations s
through f to another location in memory
starting at location d.
Insert a breakpoint in a user's program (must
be in RAM) at location s which transfers
control back to DDT-80. This allows the user
to intercept his program at a specific point
(location s) and examine memory and CPU
registers to determine if this program is
working correctly.
- Display the contents of the user registers.

The s, f, and d represent start, finish, and destination
operands required for each command.

The M, P, and R commands provide the means for
displaying the contents of specified memory locations, port
addresses, or CPU registers. The M and P commands
sequentially access memory locations or ports and display
their contents. The user has the option of updating the
content of the memory location or port, (Note some ports are
output only and their contents cannot be displayed). The M
command also gives the user access tothe CPU registers
through an area in RAM called the Register Map (discussed
in the Execute and Breakpoint section below).
The M and R commands are used to tabulate blocks of
memory locations (M) or the CPU registers (R). The M
command will accept two operands, the starting and ending
address of the block to be tabulated. The R command will
accept either no operand or one.,lf no operand is specified,
the CPU registers will be displayed without a heading. If an
operand is specified, then a heading which labels the
registers' contents will be displayed as well.
EXECUTE AND BREAKPOINT IE, B)
The E command is used to execute all programs, including
aids such as the Assembler. The B command is used to set a
breakpoint to exit from a program at some predetermined
location for debugging purposes, At the instant of a
breakpoint exit, the contents of all CPU registers are saved
in a designated area of RAM called the Register Map. In the

IVE-2

Register Map, the register contents may be examined or
mapped using the M command and a predefined mnemonic
(or absolute address) ofthe storage location for that register
(example :PC, :A, ... , :SP). The Register Map is also used to
initialize the CPU registers whenever execution is initiated
or resumed. Thus the E and B commands can be used
together to initialize, execute, and examine the results of
individual program segments.
The B command gives the userthe option of having all CPU
registers displayed when the breakpoint is encountered.
This is done by entering a second operand to the B
command. Otherwise, DDT-aD defaults to displaying the PC
and AF registers. When all CPU registers are displayed, the
format is the same as for the R command previously
discussed.
LOAD, DUMP, AND COpy (L, 0, C)
The Land 0 commands load and dump object files through
the object 1/0 channel in standard Hex format. Checksums
are used for error detection, and the addresses of
questionable blocks are typed automatically while loading.

The C command will copy the contents ofthe memory block
specified to another block of memory. There are no
restrictions on the direction of the copy or on whether the
blocks overlap.
HEXADECIMAL ARITHMETIC (H)
The H command is a dummy command used to allow
hexadecimal addition and subtraction for expression
evaluation without performing any other operation.
DDT-SO 1/0 CAPASILITIES
DDT-aD specifies 1/0 channels. designated 'Console',
'Object', and 'Source', towhicl) any suitable devices may be
assigned. The Channel AssignmentTable is located in RAM
where it may be examined or modified using the M
command. The table addresses correspond to the 1/0
channels and the table contents correspond to the
addresses of the peripheral driver routines. A channel
which has a device assignment may have that device
assignment changed using the M command. This is
accomplished by merely modifying the table contentsofthat
channel's table address to correspond to the new peripheral
driver routine. A set of peripheral driver routines is supplied
and listed below. This scheme also allows the user to write
a driver routine for his own peripheral, load it into memory,
and easily configure that peripheral into the system.
DDT-SO 1/0 PERIPHERAL DRIVERS
1. A serial input driver (usually a keyboard).
2. A serial output driver (usually a CRT or teletype
type head).

3. A serial input driver which sends out a reader-step signal
(usually a teletype reader).
4. A serial output driver which forces a delay after a
carriage return (usually a Silent 700 typehead).
5. A parallel input driver (usually for high-speed paper tape
input).
6. A parallel output driver (usually for high-speed paper
tape output).
7. A parallel output driver (usually for a line printer).
TEXT EDITOR DESCRIPTION
The Text Editor permits random-access editing of ASCII
character strings. It can be used as a line or characteroriented editor. Individual characters may be located by
position or context. The Editor works on blocks of characters
which are typically read into memory from magnetic tape or
paper tape. Each edited block can be output to magnetic
tape or paper tape after editing is completed. While the
primary application for the Text Editor is. in editing assembly
language source statements, it may be applied to any ASCII
text delimited by '"carriage returns'".
The Editor has a macro command processing option. Up to
two sets of commands may be stored and processed at any
time during the editing process.
AIIVO is done via the DDT-aD channels. The Editor can be
used with the ASMB-aO Assembler and Loader to edit,
assemble, and load programs in memory without the need
for external media for intermediate storage.
The following commands are recognized by the Text Editor:
An Bn Cn dS1dS2dOn E1Ln Mn NPn RSn dS1d-

Advance record pointer n records
Backup record pointer n records
Change string S1 to string S2 for n
occurrences
Delete next n records
Exchange current record with records to
be inserted
I nsert records
Go to line number n
Enter command buffers (pseudo-macro)
Print top, bottom, and current line number
Punch n records from buffer
Read source records into buffer
Search for nth occurrence of string S1

ASSEMBLER DESCRIPTION
The Assembler reads zao source mnemonics and psuedoops and outputs an assembly listing and object code. The
assembly listing shows address, machine code, statement
number, and source statement. The object code is in
industry-standard hexadecimal format modified for relocatable, linkable assemblies.

IVE-3

•

The' Assembler supports conditional assemblies, global
symbols, relocatable programs, and a printed symbol table.
It can assemble any length program limited only by a symbol
table size which is user-selectable. Expressions involving
addition and subtraction are allowed. A global symbol is
categorized as "internal" if it appears as a label in the
program; otherwise it is an "external" symbol. The printed
symbol table shows which symbols are internal and which
are external. The Assembler allows the' user to select
relocatable or non-relocatable assembly via the "PSECT"
pseudo-op. Relocation records are placed in' the object
output for relocatable assemblies (the Mostek object format
is defined below). The Assembler can be run as a single-pass
assembler or as a learning tool, (In this mode, global
symbols and forward references are not allowed.)
The follbwi ng pseudo-ops are recognized by the Assembler:
ORG program origin
EQU equate label
DEFL define label
DEFM define message
DEFB define byte
DEFW define word
DEFS define storage
END end statement
NAME program name definition
PSECT program section definition
GLOBAL global symbol definition
Supports the following assembler
pseudo-ops
EJECT eject a page of listing
TITLE place heading at top of each page
turn listing on
LIST turn listing off
NLiST -

RELOCATING UNKINGLOADER DESCRIPTION
The Relocating Linking Loader provides state-of-the-art
capability for loading programs into memory by allowing
loading and linking of any number of relocatable and nonrelocatable object modules. Non-relocatable modules are
always loaded at their starting address as defined by the
ORG pseudo-op during assembly. Relocatable object
modules can be positioned anywhere in memory at an
offset address.
The loader automatically links any relocator global symbols
which are used to provide communication or linkage
between program modules. As object programs are loaded,

a table containing global symbol references and definitions
is built up. At the end of each module, the loader resolves all
references to global symbols which are defined by either the
current ora previously loaded module. It also prints on the
console device the number of defined global symbols that
have been referenced. The symbol table can be printed to
list all global symbols and their load addresses. The number
of object modules which can be loaded by the Loader is
limited only by the amount of RAM available for the
modules and the symbol table. Space forthe symbol table is
allocated dynamically downward in memory from either the
top of memory or from a specified address entered as an
operand of the load command.
All 1/0 is done via the DDT -80 channels. Assembl ies can be
done from source statements stored in memory (by the
Editor). The object output can be directed to a memory buffer
rather than to an external device. Thus, assembly and
loading can be done without external storage media.
The Loader prints the beginning and ending address of each
module as it is loaded. The transfer address as defined by
the END psuedo-ops is printed for the first module loaded.
The Loader execute command (E) can be used to
automatically start execution at the transfer address.
The Loader Commands are the following:
L offset load object module at address "off-set"
plus program origin address
Eexecute loaded program at transfer
address of first module
Tprint global symbol table

MOSTEK OBJECT OUTPUT DEFINITION
Each record of an object module begins with a delimiter
(colon or dollar sign) and ends with carriage return and line
feed. A colon (:) is used for data records and the end-of-file
record. A dollar sign ($) is used for records containing
relocation information and linking information. All information is in ASCII. Each record is identified by "type". The type
is determined by the 8th and 9th bytes of the record which
can take the following values:
00
01
02
03
04
05

IVE-4

- data'
- end-of-file
- internal symbol
- external symbol
- relocation information
- module definition

f

OBJECT MODULE TYPES
Figure 3

1

•
•
•

•

D

RECOROTYPE

"'.'''"

2

~

3

CD

#OF
BINARY
DATA BYTES

4

5

7

6

I

8

START AODRESS
OF DATA

110

9

0

0
I

0

TRANSFER ADDRESS
OF MODULE

0

CHECK
SUM

DATA

0

1

CHEC~ CD

SUM

I

I

$

INTERNAL
SYMBOL NAME

0

2

$

EXTERNAL SYMBOL NAME

0

3

$

#OF
BINARY
BYTES

CD

$

0

0

0

MODULE NAME
I

CD1

CHECK
SUM

ADDRESS

LINK
ADDRESS

I
0

CD1

0

4

0

5

CHECK
SUM

CD

CD

CD1

CHECK
SUM

ADDRESSES WHICH
... REQUIRE RELOCATION ...

FLAGS

CD

I

J

-LCD

NOTES:
1. Check Sum is negative of the binary sum of all bytes except delimiter and carriage return/line feed.
.
.
.
2. Link Address points to last address in the data which uses the external symbol. This starts a backward link list through the data records for that external symbol. The list
terminates at OFFFFH.
3. The flags are one binary byte. Bit 0 is defined as:

o - absolute module
4.

1 - relocatable module
Maximum of 64 ASCII bytes.

WORD SIZE

SERIAL COMMUNICATIONS INTERFACE

8 bits for PROM
5 to 8 bits for serial 1/0
SIGNAL
MEMORY SIZE
10K bytes of firmware
MEMORY ADDRESSING

Transmitted data
Received data
Data Terminal Ready (DTR)
Request to Send (RTS)
Carrier Detect (CDET)
Clear to Send (CTS)
Data Set Ready (DSR)
Reader Step relay (RS)

2K blocks jumper-selectable for any 2K boundary within a
given 16K block oftheZ80 memory map. MDX-DEBUG has
ROMS strapped every 2K beginning at COOOOH.
I/O ADDRESSING
On board Serial 1/0 Port
Control Port: XXXXXX01
Data Port: XXXXXXOO
Module and Reader Step Control Port: XXXXXX10
XXXXXX represents 6 strap-selectable address bits.

Output
Input

Output
(40mA)

SYSTEM CLOCK
MDX-DEBUG
MDX-DEBUG-4

1/0 TRANSFER RATE
110, 300, 600, 1200, 2400, 4800, 9600, 19200 BAUD

BUFFERED FOR
20mA
Current
Loop

2.5 MHz ± .05%
4.0 MHz ± .05%

SYSTEM INTERRUPT UNITS ISIU) = 0
IVE-5

RS-232
Output
Input
Input
Input
Output
Output
Output

STD BUS INTERFACE
Inputs:
Outputs:

CONNECTORS

One 74LS load max.
10H = -3 mA min. at 2.4 Volts
10L = 24 mA min. at 0.5 Volts

Function

OPERATING TEMPERATURE

Configuration

STD-Z80 BUS 56-pin

PRINTED CIRCUIT
Viking 3VH281
1CE5

O°C to +60°C
POWER SUPPLY REQUIREMENT

0.125 in. centers

+12 Volts ± 5% at 50 mA max.
-12 Volts ± 5% at 35 mA max.
+5 Volts ± 5% at 1.2 A max.

Mating
Connector

WIRE WRAP
Viking 3VH281
1CND5
SOLDER LUG
Viking 3VH281
.1CN5

CARD DIMENSIONS
Serial 110
4.5 in. (114.3 mm) wide by 6.5 in. (165.1 mm) long
0.48 in. (12.2 mm) maximum profile thickness
0.063 in. (1.6 mm) printed-circuit-board thickness

26-pin
0.1 in. grid

FLAT RIBBON
Ansley 609-26ooM
DISCRETE WIRES
Winchester
PGB26A
(housing)
Winchester
1oo-7oo20S
(contacts)

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NO.

MDX-DEBUG

Module with 10K bytes of firmware and Operations
Manual. No mating connectors. 2.5 MHz version.

MK77950-0

MDX-DEBUG-4

Module with 10K bytes of firmware and Operations
Manual. No mating connectors. 4.0 MHz version

MK77950-4

MDX-DEBUG Operations Manual only.

MK79611

Program Source Listing of 10K byte firmware package
(DDT I ASMB-80) including comments and flow charts.
(Available free with purchase of either MDX-DEBUG
Module.)

MK78536
and
MK78534

* The DDT-80 and ASMB-80 listings are available directly from Mostek by filling out a copy of the Software Licensing
Agreement and returning it with the appropriate payment of Customer Purchase Order to:
Mostek Corporation
Microcomputer Systems Div.
1215 West Crosby Road
Carrollton. Texas 75006

IVE-6

!J

COMPUTER
PRODUCTS
DIVISION

UNITED
TECHNOLOGIES
MOSTEK

MDX-INT

FEATURES

MDX-INT
Figure 1

o STD-Z80 Bus compatible

o

User-programmable CTC provides:
• Four external vectored interrupts
or
• Four cascadable counter/timer channels
or
• any combination of the above

o Z80 Daisy Chain Interrupt Expansion
• Allows up to 40 interrupt devices
• User selectable expansion of System Interrupt Units
(SIU)
• Required for systems over five SIUs
o Nonmaskable Interrupt Input
o All input/output signals buffered
o 2.5 and 4 MHz compatible

II

o +5 volt operation

DESCRIPTION
The Interrupt-Timer Expansion Module, MDX-INT
(MK77967), is designed to be a versatile multi mode unit. It
provides external interrupt expansion of up to four lines, a
nonmaskable interrupt input, up to four cascadable timer
channels, and internal interrupt expansion capability of up
to 40 System Interrupt Units. All interrupts are Z80
compatible with full Mode 2 interrupt capability.
The MDX-INT permits up to four external interrupt inputs.
This is possible by programming the MK3882 Counter
Ti mer to fu nction as ani nterrupt controller. When progra mming the CTC, the selected input channel is programmed to
be in the counter mode with count set to one. The active
edge as well as the interrupt vector locations are also
specified by the user's program. When an active input
occurs, a Mode 2 interrupt is generated by the CTC and the
MDX-CPU can vector directly to a service routine. After the
interrupt, the CTC down counter is reloaded automatically
with a count of one and the CTC begins looking for another
active edge. Therefore, once initialized, a channel will
provide external interrupt capability automatically.

Up to four channels can be used to provide external
interrupts. Input is provided through theTRGOto TRG31ines
for channels zero through three. When multiple channels
are used, priorities are resolved within the CTC if more than
one interrupt request is made simultaneously. Each
channel has a unique vector address and each channel can
be masked independently by disabling that channel's local
interrupt.
The nonmaskable interrupt is also provided as an input
through this board. This line is tested by the MDX-CPU at
the end of each instruction. It has priority over the normal
interrupt and cannot be disabled under software control. Its
usual function is to provide response to signals requiring
immediate response, such as an impending power failure.
Each of the four CTC channels has an 8-bit Prescaler and
8-bit Down Counter that allows the circuit to be used as a
counter of a timer rather than an interrupt generator. In the
counter mode, a Zero Count output is provided that allows
cascading of successive counters. In the counter mode,
external inputs can be counted automatically by the CTC
and interrupt the processor after a predefined number of

IVE-7

counts. In the timer mode, the CTC can generate timing
intervais that are integer multiples of the system clock
period. The Zero Count output can generate a uniform pulse
train of the precise period. Therefore, precise time
measurements can be made that are a function of a crystal
clock's accuracy and stability.
The MDX-INT also provides internal interrupt expansion
through a concept of System Interrupt Units (SIU). The
interrupt system ofthe STD-ZSO compatible CPUs will allow
up to five System Interrupt Units without need of expansion.
The MDX-INT has circuitry to allow expansion of board with
up to 40 SIUs. It must be the last card (the lowest priority) in
the interrupt daisy chain. An SIU is defined as an interval of
time equivalent to the worst-case propagation delay of the
priority daisy chain through an MD board. A board with one
interrupting peripheral component, such as an MDX-SIO,
has one SIU. A board with two interrupting peripheral
components, such as an MDX-PIO, has two SIUs. A board
with no interrupt capability has zerO SIUs.
The SIU expansion circuitry on the MDX-INT card monitors
the data bus and PCllines. Walt states are added during the
RETI opcode to allow the PCI and PCO lines to stabilize. The
Wait state generator on the MDX-INT is enabled when an
interrupt is pending or lmder service and will insert a
predetermined number of wait states for 15, 25, or 40 SIUs.
SYSTEM INTERRUPT UNITS
Table 1

Card
MDX-AlD12
MDX-A/DS
MDX-AIO
MDX-CPU1/1A
MDX-CPU2I2A
MDX-CPU3
MDX-CPU4
MDX-D/AS
MDX-D/A12
MDX-DEBUG
MDX-DRAMS/16/32/64/12S
MDX-EPROM
MDX-EPROM/UART
MDX-FLP/FLP2
MDX-INT
MDX-ISIO
MDX-MATH
MDX-MODEM
MDX-PIO
MDX-SASI112
MDX-SC/D
MDX-$10/SI02
MOX-SRAM4/S/16
MDX-SST
MDX-UMC/UMC2

SIU's
1
1

0
1
1
1
1

The number of SIUs that the system can handle is hardware
selectable on-board. A Block Diagram ofthe MDX-INT board
'.
.'
is shown in Figure 3.

WORST-CASE PRIORITY CHAIN INTERFACE PROPAGATION DELAY
Figure 2

PCI

PCO

2.5 MHz 20 nsec

220nsec

20 nsec

4.0 MHz 20 nsec

160 nsec

20 nsec

4.0 MHz SIU = 200 nsec = 20 + 160 + 20
2.5 MHz SIU = 260 "sec = 20 + 220 + 20

CTC Address Decode
This address logic compares the six most significant I/O
address bits (A7-A2) with the J4address location jumper. If
these are equal, and an I/O request has been made to the
board, then the CTC will be enabled. AO and A 1 are decoded
directly by the CTC and used to select the specific CTC
channel, as shown in Table 2.
MDX-INT BOARD PORT ASSIGNMENTS
Table 2

0
0
0
0
0
0
1
1
1
1
1
2
1
1
1

0
0
0

lEO

A1

AO

CTCChannel

0
0

0

0

1

1
1

0

1
2
3

1

Bus and Buffer Control
All signals are buffered going to or coming from the board.
Data Buffering

a

SN74LS245 octal
Data signals are buffered by
transceiver. The turnaround of the bus is handled either by
the decode of an I/O Read or by a Read of the interrupt
vector.

IVE-8

MDX-INT BLOCK DIAGRAM
Figure 3

3 CONTROL

3 CONTROL

LA0- A7 )

2 CONTROL

ADDRESS
DECODE

4 CONTROL

5 CONTROL

CTC

D~~
5 CONTROL
2 CONTROL

BUFFER

1 CONTROL

I--

I

1 CONTROL
2 CONTROL

~
WAIT

ED PREF

00-07>

DATA
BUFFER

~-DB7

D~

OP CODE
PREFIX
DECODE

WAIT
STATE
SEau.
RETI

Op-Code Prefix Decode

ADDRESS DECODE

The Op-Code Prefix Decoder searches the data bus for two
things: an ED two-byte instruction, and an RETI instruction.
When an ED two-byte instruction is decoded, a WAIT state
is inserted. Next the data is inspected for a 4D, the second
part of the RETI. If a 4D is present, additional WAIT states
are added corresponding to the number of SIUs selected. If
not, no additional wait states are added.

Table 3 shows the assignment of address decoder select. A
pullup resistor is on the board which selects a logical 1 in
the address bit field. Each address bit that is to be
programmed to a zero must have a jumper installed.
JUMPER ADDRESS PIN ASSIGNMENTS
Table 3

WAIT State Sequencer
This micro-programmed sequencer is a state controller
designed to add wait states in conjunction with the op-code
prefix decoder. It allows the decode of a RETI (ED-4D)
instruction and the propagation of a correct PCI to all boards
in the system. If WAIT states are not required, the interrupt
expansion capability can be disabled by removing jumper
E2. This prohibits WAIT states from being introduced on the
bus.
CTC

Address Bit

J4 Jumper Pin

A7
A6
A5

1- 2
3- 4
5- 6
7- 8
9-10
11-12

A4

A3
A2
SIU Selection

zao

The MK3882 is a flexible
peripheral that allows
operation as either a counter or timer on to 4 channels. The
outputs of the CTC are buffered and wired to connector J2.
The outputs are the ZCITO from channels 0 through 2.
Clock and Trigger inputs are buffered and provided for all
four channels.

The pins 1 to 2 and 3 t04 of J3 select the maximum SIUs in
a system. Table 4 shows the options of system, speed
selection, and jumpers required.
One More WAIT State
If there is an extra Wa it state in the CPU for memory cycles,
the jumper for one more (at J3 5-6) must be removed.

IVE-9

II

MECHANICAL

SIU JUMPER ASSIGNMENTS
Table 4
MaxSIU's
2.5 MHz

Card Dimensions
J3 Jumper Pins

4.5 in. (11.43 cm) wide by 6.5 in. (16.51 cm) long
0.48 in (1.22 cm) maximum profile thickness
0.062 in. (O.16 cm) printed circuit board thickness

4MHz

15

14

3-4 and 1'2

25

24

3-4

40

34

NONE

Connectors
Function

Configuration

Mating Connectors

STD Bus

56 Pin dual
0.125 in. centers

Printed Circuit
Viking 3VH28/1 CE5
.WireWrap:
Viking 3VH28/1 CND5

SPECIFICATIONS
ELECTRICAL

Solder Lug:
Viking 3VH28/1 CN5

System Clock
Part Number
MK77967
MK77967-4

Board
MDX-INT
MDX-INT-4

Min.
250 KHz
250 KHz

Max.
Parallel
I/O

2.5 MHz
4.0 MHz

26 pin dual
0.100 in. grid

Bus Interface. STD-Z80 Compatible
Inputs:
Outputs:

One 74LS load Max.
IOH = -15 mA.Min. at 2.4 Volts
IOL = +24 mA Min. at 0.5 Volts

Flat Ribbon:
Ansley 609-2600M
Discrete Wires:
Winchester: PGB26A
(housing)
Winchester:
100-70020S
(contacts)

CTC I/O PIN ASSIGNMENTS
Power Supply Requirements
+ 5 Volts ± 5% at 1.2 A max
Word Size
DATA: 8 bits
I/O ADDRESS: 8 bits using 4 ports with 6 bits jumper option
Operating Temperature Range
0° to 60° Centigrade
MODE OF OPERATION

1
2
3
4
5
6
7
8
9
10
11
12
13

Interrupts are handled to provide prioritized interrupts
compatible with the STD-Z80 Bus requirements, and be
capable of polled operation when interrupts are disabled for
the CTC. The interrupt expander is code-transparent to
software when the CTC is not used.
.
SIU's

IVE-10

CLK/TRGO
ZCT/TOO
CLK/TRG1

ZCTIT01
CLK/TRG2

ZCTlT02
CLK/TRG3
N.C.
/NMI
N.C.
N.C.
N.C.
N.C.

14
15
16
17
18
19
20
21
22
23
24
25
26

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND·.
GND

ORDERING INFORMATION
Designator

Description

Part Number

MDX-INT

MDX-INT Interrupt Expander Module with Technical Manual
(2.5 MHz)

MK77967

MDX-INT

MDX-INT Interrupt Expander Module with Technical Manual
(4.0 MHz)

MK77967-4

MDX-INT
Technical Manual

Technical Manual only

4420069

•

IVE-11

""'.,,,'

"

IVE~'2'

;

m

UNITED

COMPUTER
PRODUCTS
DIVISION

TECHNOLOGIES

MOSTEK

MDX-SC/D

MK77963-0, MK77963-4
FEATURES

MDX-SC/D BOARD PHOTO
Figure 1

o STD-Z80 BUS compatible
o Provides an operator interface; switches and lamps
o 10K x 8 EPROM (2716's not included)
o Dual-purpose card, memory and/or diagnostic interface
o Interrupt-driven programmability
o Strap-selectable address
o 4 MHz Option
o Fully-buffered for MD Series expandability
o Diagnostic software package
DESCRIPTION
Designed as a system controller/diagnostics board, it
provides the user with Reset/Interrupt lines to the CPU, as
well as the capability to run tests placed in EPROM on
board, to verify the operation of other MD boards on the bus.
The board is equipped with sockets to contain upto 10Kx8
of EPROM memory (5-2716's) as shown in the Block
Diagram. The EPROM's can contain the diagnostic
programs necessary for testing the modules or can contain
user application programs.
The EPROM memories can be positioned to start on any 2K
boundary within a 16K block of memory via a strapping
option provided on the board.
For the 4MHZ version, circuitry is provided to force one wa it
state each time on-board EPROM's are accessed.
A three-position switch is provided at the top of the board.

The switch is spring loaded to the OFF position. The RESET
position initializes the hardware and software diagnostics
elements. The START position begins the diagnostic test
which had been preset by the thumbwheel switches, also
on the top of the board. At the conclusion of the test, the
results are displayed by the LED Readouts. Data transfers
from the switches to the bus and from the bus to the
readouts are accomplished by the MK3881 PIO.
The PIO also permits total interrupt control so that full usage
of the CPU interrupt capabilities can be utilizEld during data
transfers. The PIO provides vectored interrupts and
maintains the daisy-chain, priority interrupt logic
compatible with the STD-Zao BUS.

IVE-13

•

MDX-SC/D BLOCK DIAGRAM
Figure 2
ADDRESS AND CONTROL
BUS

DATA BUS

The address decoding, interface and bus management for
the board are performed by the address decode and data
bus circuit. The PIO ports have two addresses each; these
are summarized below.
PORl' A

xxxxxooo

XXXX X010

CONTROL

XXXX XOO1

XXXXX011

EPROM - 2K blocks jumper-selectable for any 2K boundary
within a given 16K boundary of Z80 memory map.
MEMORY SPEED REQUIRED

PORTB

DATA

MEMORY ADDRESSING

Memory
Access Time
* 2716
450 ns
* Single 5-Volt type required

Cycle Time
450ns

INPUT/OUTPUT

The XX symbols stand for the upper five bits of the I/O
channel address. These bits are jumper-selectable on the
board in order to provide address-selectable, fully decoded
ports.

Controlled by spring-loaded RESET/START switch with
center off.
Test selected by two thumbwheel switches.
Test results indicated by two 7-segment LEDs.
INTERRUPTS

MEDEX-80
Vectored interrupts generated. Interrupt vector programmable upon initialization. Daisy-chained interrupt
priority. Selected bit channels can be masked out under
program control.

MEDEX-80 is a diagnostic software package designed to
operate with the MDX-SC/D card's thumbwheels, switch
and display. The package consists of a control monitor,
MDX-SC/D card interface handler, and numerous
diagnostic tests for the MDX series cards. The package can
operate as a stand-alone program or can be integrated with
a user program. MEDEX-80 is designed to allow userdeveloped diagnostics to be adapted as extensions to the
package.

SYSTEM CLOCK

WORD SIZE

STD BUS INTERFACE

8 bits

Inputs: One 74LS Load max.
Outputs: 10H = -3mA min. at 2.4 Volts
10L = 24mA min. at 0.5 Volts

MEMORY SIZE

MDX-SC/D
MDX-SC/D-4

10K bytes of 2716 memory (2716's not included)

IVE-14

2.5 MHz ± .05%
4.0 MHz ± .05%

OPERATING TEMPERATURE RANGE

POWER SUPPLY REQUIREMENTS
+5 Volts

± 5% at 1.2 A

max.

CARD DIMENSIONS
4.5 in. (114.3 mm) high by 6.50 in. (165.1 mm) long
0.48 in. (12.2 mm) maximum profile thickness
0.062 in. (1.6 mm) printed-circuit-board thickness
CONNECTORS
Function

Configuration

STD-Z80 BUS 56-pin
0.125 in. centers

Mating Connector
PRINTED CIRCUIT
Viking 3VH28/1 CE5
WIRE WRAP
Viking
3VH28/1 CND5
SOLDER LUG
Viking
3VH28/1CN5

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NO.

MDX-SC/D

Module with Operation Manual, 2.5 MHZ version

MK77963-0

MDX-SC/D-4

Module with Operation Manual, 4.0 MHZ version

MK77963-4

MDX-SC/D Operation Manual Only

MK79678

Diagnostic software for various MDX Series cards,
distributed on diskette in Z80 Assembly source form

MK77968

MEDEX-80

IVE-15

II

IVE-16

!t
.

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COMPUTER
PRODUCTS
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TECHNOLOGIES
MOSTEK

MDX-PFD

FEATURES

MDX-PFD
Figure 1

o Detects. loss of AC power after one half cycle
o Detects brownout condition (AC below 95 V)
o Contains logic to sequence pushbutton res.et and nonmaskable interrupt
o Battery backup for up to five days via rechargeable Ni
Cads
o STD-ZaO Bus compatible

DESCRIPTION
The MDX-PFD board (MK77979) and voltage transformer
module provide for power-up/power-down sequencing for
use in conjunction with the battery backed MDX-BCLK and
MDX-BRAM boards. A block diagram is shown in Figure 2.
Figure 3 shows the MDX-PFD timing.
The Voltage Transformer Module is mounted separately
from the card cage containing the MDX-PFD board. Its
purpose is to provide a low voltage AC signal which is
derived from the 115/230 volt line supplying the main
system power.ltcontainsaterminal strip for 115/230VAC
power, a fuse, and a transformer. A cable and connector are
provided for connection to the MDX-PFD board.
Rectified AC voltage from the voltage transformer module is
divided through a resistive network and used as an input to
a comparator (U2) with an internal reference. The
comparator "peak detects" the adjustable AC input which is
factory set to approximately 95 VAC as a brown-out
detection level. The comparator outputtriggers a retriggerable
CMOS one shot (V2 of U3) with a period of 13 mSec. This
output generates the NMIRQ signal, and it also triggers a
second one shot (Y2 of U3) which inhibits the first one shot
for a period of 5 mSec. This second delay is necessary to
allow a software power-down subroutine to complete
before SYSRESET is generated.

POWER DOWN SEQUENCE
Detection of power failure immediately sets the NMIRQ
flip-flop (Y2 of US) causing non-maskable interrupt (NMIRQ)
to go low, which in turn vectors the processor to location 66
H, the entry point of a user supplied power-down
subroutine. Table 1 shows an example of a power-down
subroutine.

ADDRESS DECODE AND CONTROL
When the interrupt port OF7H (PFD board address) is read by
the power-down subroutine, a 0 in data bit 7 (D7) indicates
power fail condition which a 1 indicates no power failure.
The last instruction of the power-down subroutine should
be a write to port address OF7H. This will set the SYSRESET
flip-flop (Y2 of US) and cause SYSRESET to go low. The
above conditions will be maintained by battery backed up
CMOS logic until power is restored.

POWER UP SEQUENCE
When the power is detected by the MDX-PFD voltage
comparator circuit, a reset signal is released from a counter
(U6), allowing itto count. The counter then releases NMIRQ,
nonmaskable interrupt request, causing it to go high after
approximately 130 mSec. Next the counter releases
SYSRESET, causing it to go high after approximately 260
mSec after AC power is detected, thus allowing normal
system operation to begin the power up subroutine starting
at address DOH or EOOOH. These delays are necessary in
order to allow DC power to stabilize after AC power has
been restored. Loss of power at any.time before system
reset goes high will cause the counter to be reset and the
130/260 mSec timer sequence to be repeated after AC
power is again restored.

IVE-17

MDX-PFD BLoCK DIAGRAM
Figure 2

.

-;..

'"

AC
VOLTAGE
TRANSFORMER
MODULE

"

5VAC
SIGNAL

-

POWER
DETECT
LOGIC

j

"

I
PWR

---...

1

"t

07

-

STD AO-A7& "\
ZBO CONT~Pk
BUS SIGNA -y

II1\
V

A

SYSRESET

-.

.,

BATT,fFlIES
CHARGING
CIRCUIT

I

NMIRQ

BUS
INTERFACE
LOGIC

l.-.

7-

SYSRESET

NON-MASKABLE
INTERRUPT
AND
SYSTEM
RESET
LOGIC

'f

I

-...

NMIRQ

,.

TIMING DIAGRAM
Figure 3

~-----------'J ~

ACPOWER PWR

6Ms -

r-----~.Pt-i----'-----

' - -_ _---J

H

COUNTER RESET 07-_ _ _ _.:..."
SYSRESET _
I

Ur-------~Ut----r-------

SET PULSE

U

$$...._ _---L_ _ _ _ __
I

I

.COUNTER(Q181 - n J l - ' " . - - - . . ! - - - - - - - - - - ' $

r-:-l
. I
COUNTER(Q191 -=----.J.

j

~
f

I

-+I

I

26~ ms

NMIRQSYSRESET

-=--__---====f-------JHI--------11
IVE-18

F1

EXAMPLE OF POWER-DOWN SUBROUTINE
Table 1
ORG

0066H

;POWER FAIL TRAP

•
•
•
IN
AND
JP

A, (OF7H)
080H
NZ, NOFAIL

;TEST FOR POWER-DOWN CONDITION FROM MDX-PFD
;IS BIT 7 SET?
;JUMP IF SO

•
•
USER POWER FAIL ROUTINE

(EG:SAVE REGISTERS VARIABLES ETC.)

•
OUT
NOFAIL •

(OF7H), A

;INSTRUCT MDX-PFD TO ASSERT SYSRESET LOW
;OTHER NMI INTERRUPT SERVICE ROUTINES

•

•

•
JUMPER CONFIGURATIONS

BATTERY BACKUP

Figure 4

Three AAA size nickel-cadmium rechargeable cells are
provided to supply standby power during primary AC power
outages. These batteries will supply power for the logic for a
minimum of five days when operated at 25 C. The batteries
are charged from both +12 V DC(J1 pin 55)via CR5 and R6
and +5 V DC (J1 pin 1 and 2) via CR4 and R4. Zener diode
CR1 serves to keep VBATTfrom going above 5.6 V DC when
J3 pins 1 and 2 are not connected. If +12 V DC is not
available, the batteries may be trickle charged from +5V DC
alone by installing the jumper between J4 pin 1 and pin 2.
Note, however, because of the reduced charging potential
in this configuration, battery supply may not last the full five
days.

J3
• 1

• 2

J4
• 1

• 2

Depending on the initial condition ofthe batteries, the initial
charging current is 18 mA to 32 mA, the trickle charging
current is 9 mA to 13 mA. When batteries are being charged
with 5 volts only, the charge rate is approximately 4 mA.

•

J5

1·
3.

• 2
• 4

STRAPPING OPTIONS
The CPU jumpers are used to activate the power up and
pushbutton reset logic provided on the MDX-PFD board if
CPU1 board is used as the microprocessor. Figure 4 shows
the jumper configuration for use with CPU 1 and CPU 2
processors. The board is shipped with a jumper between J5
pins 1 and 2.

J6

2
JUMPER CONFIGURATION
FOR CPU-1
J5

1.
3

BATTERY CIRCUIT JUMPERS
The MDX-PFD board is shipped with the batteries
disconnected from the logic and charging circuit. In order to
connect the batteries, place a jumper between J3 pins 1 and

• 2

____ 4

JUMPER CONFIGURATION
FOR CPU-2
J5

•1

3 •

Input Power Connections
Voltage Transformer Module

2.
The board is also shipped with no jumper between J4 pins 1
and 2. If +12 volts are not available for battery charging, a
jumper should be placed between J4 pins 1 and 2.
IVE-19

...--- 2

1L2t115VA:J

230VAC~

• 4

SPECIFICATIONS

Operating Temperature

ELECTRICAL SPECIFICATIONS

0° to 60°C
0° to 25°C for 5 day battery operation

STD BUS Compatible
MECHANICAL SPECIFICATIONS
AO-A7

Inputs
Card Dimensions (MDX Card)

IlL = -.2 mA max at .4 V
IIH = 20 pA. max at 2.7 V
Inputs

(11.43 cm) high by 6.50 in. (16.51 cm) long
4 ..5 in.
0.675 in. (1.71 cm) maximum profile thickness
0.062 in. (0.16cm)printed circuit board thickness
Card Dimensions (Voltage Transformer Module)

IlL = -.2 rnA max at .4 V
IIH = 20 pA. max at 2.7 V
NMIRQ. SYSRESET Open Collector Output

3.00 in. (7 ..62 cm) wide by 3.00 in. (7.62 cm) long
0.062 (0.16 cm) printed circuit board thickness
Connectors

IOL 24 rnA min at .5 V
D7

Function
STD Bus

Tristate Output

IOL 24 rnA at .5 V

Configuration
56 pin dual read
out 0.125 in.
centers

Mating Connector
Printed Circuit
Viking 2VH28/1 CE5

Wire Wrap
Viking
3VH28/1 CND5

AC (Input to MDX-PFD)
5VAC RMS
Power Supply Requirement
5 V ± 5% at 130 rnA max.
12 V ± 5% at 45 rnA max.

MDX-PFD
Card
AMP87551-2
. 2 pin rt. angle
to Voltage
Transformer header strip on
Module
MDX-PFD Board

AMP87499-3 cable
connector on
Transformer Module

ORDERING INFORMATION
Designator
. MDX-PFD

MDX-PFD
Technical
Manual

Description

Part Number

MDX-PFD Power Fail
Detect Module XFMRS
Cable with Technical
Manual

MK77979

MDX-PFD Technical
Manual only

4420046

;

IVE-20

COMPUTER
PRODUCTS
DIVISION

~ TECHNOLOGIES

UNITED

MOSTEK

MDX-8CLK

FEATURES

MDX-BCLK
Figure 1

o STD Bus Compatible

o

24 hour clock

o

Provides seconds, minutes, hours, day, and month in
BCD format

o

Contains Leap and non-Leap year Julian calendars

o

Retains clock/calendar functional capability without
system power for five days on fully-charged batteries

o

Provides Interrupts at 62.5 ms (16 Hz), one sec, one min,
and one hour intervals to CTC on MDX-CPU2 via usersupplied cable

o

Accuracy of ten seconds per month at 25°C

o

Power backup is provided via rechargeable batteries

o

2.5 MHz and 4.0 MHz operation

o

2 Port addresses

DESCRIPTION
The MDX-BCLK module provides seconds, minutes, hours,
days, and month data in BCD format (24 hour). Real-time
interrupt capability is provided via the CTC on the MDXCPU2 or MDX-INT module. The module is accurate to 10
seconds per month at 25°C. The battery-backup feature
retains clock/calendar functional capability without system
power for five days on fUlly charged batteries.
The board consists of nine main elements: address buffers,
address/bus control decode logic, bi-directional data
buffers, power detect circuitry, backup batteries, clock
control register, clock data latches, CMOS clock circuit. and
clock set logic. The address/bus control decode logic
controls the direction of the bi-directional data buffers and
the enabling of the clock control register, data clock latches,
and the clock set logic. The power detect circuitry detects
system power failure and prevents the TTL from interacting
with the battery-backed-up CMOS. The clock control
register selects the desired operation of the CMOS clock
circuit (i.e., read seconds, set seconds, read minutes, and so
on). The clock data latches, in conjunction with the clock
control register, enable and select the desired clock data

(seconds, minutes, hours, day of the month, and month).
The CMOS clock circuit is a battery-backed-up clock which
retains data for five days on fully charged batteries. The
clock set logic allows clock setting through the STD BUS
interface.
STRAPPING OPTIONS
Port Address Configuration Strapping
The MDX-BCLK module port address block permits port
selection and system flexibility. Address selection is
accomplished by installing the proper straps on Header J5.
Installing a strap is equivalent to selecting the particular
address bit to zero. In addition, the board can only be port
addressed on even bit increments (i.e., DOH, 02H, 04H ... ).
Figure 3 is an example of a port addressed at 80 H.
External Clock Input
Header J3 is provided to input a clock frequency other than
the on-board 1 Hz frequency and is primarily intended for
testing purposes. Header J3 must be strapped for module
functional capability, and is strapped before shipment.

IVE-21

II

MDX-BCLK FUNCTIONAL BLOCK DIAGRAM
Figure 2

ADDRESS BUS

ADDRESS/
ADDRESS
BUFFERS

1------1,

I-______________________________

BUS
CONTROL
DECODE
LOGIC

~~

CLOCK
CONTROL
REG.

r---~~CLR

CONTROL SIGNALS

BLOCK
DATA

REAL TIME
INPUTS

IVE-22

J5 PORT ADDRESS SELECTION

MDX-CPU2 CTC HEADER PINOUT

Table 1

Table 3

PINS

ADDRESS BITS

13-14

A1

11-12

A2

9-10

A3

7- 8

A4

5- 6

A5

3- 4

A6

1- 2

A7

FUNCTION

ADDRESS STRAPPING EXAMPLE FOR PORT
ADDRESS SOH
+5V

Figure 3

I

PIN

PIN

FUNCTION

CIT 0

1

2

ZCO

CIT 1

3

4

ZC 1

CIT 2

5

6

ZC2

CIT 3

7

8

NC

NMI

9

10

NC

NC

11

12

NC

NC

13

14

GND

GND

15

16

GND

GND

17

18

GND

GND

19

20

GND

GND

21

22

GND

GND

23

24

GND

GND

25

26

GND

J5
13,...
A1

A2
A3
A4
A5

14

Battery Disconnect

"\.J.--.-IJ'

-

11 ......

......

9....

12

The MDX-BCLK module has on-board rechargeable
batteries. Pins 3-4 on header J4 allow disconnection of
these batteries when the system is to be powered down and
the clock function is not needed. Removing the jumper
disconnects the batteries, thus preventing discharge.

10

"IJ.-.-,.:V
",,8
7....
~

-

5,..."
~

-

.....

A6

3,..."

A7

1

6
4
2

-"-

Connector J2 Pinout for External Clock Frequencies
External clock frequencies are provided to enable the CTC
on the MDX-CPU2 or MDX-INT to provide accurate realtime interrupts at 62.5 msec, one sec, one min, and one
hour time intervals. The desired time interval or intervals
are selected by connecting the appropriate pins ofthe 26 pin
header on the MDX-CPU2 to the S pin header on the MDXBCLK module. A twisted pair connection should be used
where one conductor is ground (See Table 2 and Table 3).
J2 PINOUT
Table 2

FUNCTION

PIN

PIN

FUNCTION

GND

1

2

GND

3

4

62.5 msec (16 Hz)
1 sec

GND

5

6

1 min

GND

7

8

1 hour

The MDX-BCLK module can function with a 5 volt supply
because the 12 volt supply is only used to decrease battery
charge time. In order to select 5 volt only operation, pins 1
and 2 must be strapped on Header J4. Note: this mode
increases the charge time to 36 hours for a full charge at
25°C.
Power Fail Ciruitry
The power fail detection circuit senses when the 5 volt
supply to the BCLK falls below 4.7 volts. If the 5 volt line
remains below this threshold for more than 9 microseconds,
access to the board will be disabled. The 9 microsecond
delay is a result of the RC time constant used in the SPF,
system powerfail circuitry. This circuitry is composed ofthe
ICL 8211, U1 (voltage reference); an MC14538B, U2 (dual
multi-vibrator); and an MC14013B, U7 (D-type flip flop). The
battery-backed CMOS clock circuitry remains active during
SPU; access only to read or write is inhibited. The system
power up, (SPU), signal is used to re-enable board access
and may be active from 4.7 volts typical to 4.85 volts
maximum. The SPU one shot U2, has a time-out of 5 ms to
allow for stable power supply voltage before enabling board
access. Because of the level at which the BCLK module
becomes re-enabled, the user must set the power supply
voltage at the board bus interface, connector J1, to a
minimum of 4.9 volts (5 volts recommended).

IVE-23

Adjustment of R2 establishes the voltage level at which tlie
MDX-BCLK module recognizes power fail. This' level is
factory set at 4.7 volts and should not be changed. If R2
requires adjustment, the following procedure should be
used:
'
a) Adjust a power supply such that 4.7 volts is present on
the 5 volt input (Pins 1 and 2 on J1).
b) Connect an oscilloscope or a voltmeter to the output of
the ICL8211 (Pin 4 of U1).
c) Adjust R2 until the voltage on Pin 4 of the ICL8211 goes
to a high level (greater than 2.4 V).
d) Slowly adjust R2 in the opposite direction until the
voltage goes to a low level (less than .7 V).
e) The ICL8211, U 1 provides 50 mV hysteresis typically
between system power up signals which may be altered
by varying the value of R4.

DO-Clock ReSet and Disable
When the DO bit of the control register makes a transition
from low to high (positive edge), the clock resets to zero
(00:00:00). As long as the bit remains in the high condition,
the 1 Hz input to the clock counter chain is disabled.
The disable function is level triggeredcFor instance, if DO is a
high level and a reset function is desired, the bit must be
"dropped" to a Iqw level and then "raised" to a high level.
D1-Calendar Reset
When the 01-bit of the control register makes a transition
from low to high (positive edge), the calendar resets to
January 1 (01,01).
D2-Second Read/Second Set

WARNING: Mostek does not assume any responsibility
for module failure if this adjustment is made.
FUNCTIONAL SOFTWARE DESCRIPTION
The MOX-BCLK interface consists of two ports. When a
write (OUT) is performed to the low order port (XXXXXXX 0)
the control register is accessed. When a read (IN) ,is
performed from the low order port, the desired clock data is
accessed. Two successive writes (OUT) to the high order
port (XXXXXXX 1) increment a particula'r counter dependingon the state of the control register, Reading the high
order port has no function and irrelevant data will be
obtained.
Control Data Register
The control register on the MOX-BCLK module consists of
eight bits whose functions are described in Table 4. In order
to read and,set clock data, the appropriate bits in the control
register must be set. Writing FFH would set all bits and
writing ooH would clear all bits of the control register.

When the 02 bit of the control register is a high level, the
second read/second set function is enabled, With the 02 bit
set, and a read performed on the low order port, "second"
data appears in BCD format. The bit also serves as the
second set. When two successive writes (OUn are
performed on the high order port, the "seconds" counter
advances by one second.
D3-Minute Read/Minute Set
When the 03 bit of the control register is a high level, the
minute read/minute set function is enabled. When 03 bit is
set and a read performed on the low order· port, "minutes"
appears in BCO format. The bit also serves as the minute
set. When two successive writes (OUT) are performed on
the high order port, the "minute" counter advances by one
minute. After the "minute" counter reaches fifty-nine and is
incremented one more time, the "hour" counter advances
one hour. Note: The hour counter must be set through the
minute counter.

CONTROL REGISTER FUNCTIONS
Table 4
07

06

05

04

03

02

01

DO

,I"'I~~.:
.

-

CLOCKRESET&DISABLE
CALENDAR RESET

' - - - - - - - - - - -.... SECOND READ/SECOND SET
1..-_ _ _ _ _ _- - - - - , . ,

MINUTE READ/MINUTE SET

~~--------------------------~: HOUR READ
I..----------~~----.. DAY-MONTH READ/DAY SET

I..---_---,------------I~ DAY/MoNTH SELECT
LEAP/l\ION-LEAP YEAR SELECT

CONTROL DATA REGISTER FUNCTIONS
Figure 4
WRITE

READ

OUT (XXXX XXX1)

(XXXXXXXO)

(XXXXXXXO)

OUT (XXXX XXX1 )

07
X

X

05
X

X

X

X

03
X

X

X

X

X

X

01

DO

X

•

COMMENTS

Rising Edge Resets
Clock to 00:00:00
High Level Disables

X

1 Hz Clock Pulse
X

X

X

X

X

X

X

X

X

X

X

•

X

X

X

Rising Edge Resets
Calendar To 01-01
High Level Selects
Leap Year Calendar

0

X

X

X

X

X

X

Low Level Selects

X

Non-Leap Year Calendar
X

X

0

0

0

X

X

INCREMENT SECONDS

SECOND DATA

Ripple Not Disabled
To Minute Counter

X

X

X

X

X

0

0

0

X

X

MINUTE DATA

INCREMENT MINUTES

Ripple Not Disabled

& HOUR WITH RIPPLE

To Hour Counter

o

0

X

X

HOUR DATA

o

0

0

X

X

MONTH DATA

INCREMENT DAY OF YEAR

o

0

0

X

X

DAY DATA

INCREMENT DAY OF YEAR

0

X

0

D4-Hour Read
When the D4 bit of the control register is a high level, the
hour read function is enabled. When the D4 bit is set and a
read performed on the low order port, "hour" data appears
in BCD format.
D5-Day-Month Read/Day Set
When the D5 bit of the control register is a high level. the
day-month read/day set function is enabled. With the D5
bit set, and a read is performed on the low order port, either
"day" or "month" data appears in BCD format depending on
the condition of the day/month select bit of the control
register (D6). The D5 bit also serves as the day set. When
two successive writes (OUT) are performed on the high
order port, the day or month counter advances by one "day"
or "month" depending on the condition of the day/month
select bit.

operations can be performed on "month" data. When the
D6 bit is a high level, the "day" portion of the calendar is
addressed and read and set operations on "day" data can be
performed.
D7-Leap/Non-Leap Year Select
The MDX-BCLK module contains leap and non-leap year
calendars. With the D7 bit in a low state, the calendar is a
365 day non-leap calendar. With the D7 bit in a high state,
the calendar is a 366 day leap year calendar. During a leap
year, the D7 bit only has to be set when reading or setting
operations are performed on the clock. It is not necessary to
keep the bit set all the time during a leap year.
Power Up Condition
All bits of the control register power up in a low level state.
Clock Read/Set Software

D6-Day/Month Select
When the D6 bit of the control register is a low level, the
"month" portion of the calendar is addressed and read

The section provides a general flow chart for reading the
clock and software examples in zao Assembly Language.
The zao programs are sample implementations while the

IVE-25

II

flow charts provide detailed program outlines. Figure 5 is a
general program for reading the clock calendar with leap
year provisions. Figure 6 is a complete clock calendar with
leap year provisions. Figure 7 and 8 are flow charts of the
same information:

for up to 127 days past the end of the year (i.e" 82, 83, 84,
85, 86, 87, 88, 89, 8A, ·8B, ... ) allowing the calendar
correction.

Explanation of Clock Read Flow Chart

This section provides a general flow chart for reading the
clock and a software example in Z80 Assembly Language.
Figure 6 is a general program for setting the time.

The clock calendar read flow chart is shown in Figure 7 and
consists of the following four parts:

Clock Set Advance

Explanation of Clock/Calendar Set Flow Chart
1.
2.
3.
4.

Leap/Non-Leap Year Determination
Clock Read
Clock Check
End of Year

Clock Read and Check
In order to interpret the clock calendar correctly, one must
determine if the year is a leap or non-leap year. Because the
leap year is cleared when system power is lost, it should be
set, if necessary, prior to each read. The clock calendar
should be read next by setting the leap year bit accordingly
and reading the clock in the following order:
1.
2.
3.
4.
5.
6.

Second Data
Month Data
Day Data
Hour Data
Minute Data
Second Data

After the above data has been obtained, the two second
readings must be compared. This is necessarY due to the
possibility of reading the clock during a counter chain ripple.
For example, if the time is (23:59:59) and the clock changes,
one might obtain (23:00:00). By reading the seconds twice,
the beginning and end one would always know the validity
of the read. If the two second readings are different, one
needs to re-read the entire clock.
End-Of-Year Function
Software is responsible for resetting the day/month
counter. A status bit (07) will be set on the 366th or 367th
day depending on which calendar is used (leap or non-leap)
to inform that the end of the year has arrived. The end-qfyear data contained in the month portion Qf the calendar
starts at 81 H !lo.that the user can test the high order Qit to
determine the end of the year. From then it counts in binary

The clock/calendar set flow chart is illustrated in Figure 8,
and consists of the following three parts:
1. Leap/Non-Leap Year Determination
2. Clock Set
3. Calendar Set
Clock Set
To setthetime on the MDX-BCLK module, set in sequence,
the hours first, minutes next, and then seconds. Use the
control register to select the desired counter for setting;
write to the high order port to incrementthe counter. Setthe
second and minute counters individually; the hour counter
is incremented automatically by the minute counter (i.e.,
after 60 increments ofthe minute counter, the hour counter
advances.). Two algorithims can be used to set the clock.
First, increment and then check each counter until the data
matches that ofthe flowchart and sample programs. To set
the clock, either increment each counter unti I it matches the
flow chart and sample programs or reset the counters and
increment from zero (i.e., 30 second desired set time
requires 60 OUTs). The clock reset disable bit (DO) of the
control register should be set and left set during the entire
clock/calendar set time.
Calendar Set
Tosetthe calendar on the MDX-BCLK module, the calendar
reset should be raised and then lowered at the beginning of
the calendar set program. The Leap Year/Non-Leap Year
bit, 07, must be set accordingly before month alld day data
is set.
Mandatory setting order of the calendar is month and then
day. Select the desired date to be set (day or month) with the
control register and then write to the high order port to
increment the counter.

CLOCK CALENDAR READ SOFTWARE
Figure 5
MOSTEK MACRO-80 ASSEMBLER V2.2
LOC

OBJ.CODE

STMT-NR

PASS2

SOURCE-STMT

OPSRD

OPSRD

OPSRD

PAGE 1
REL

COMPLETE CLOCK AND CALENDAR READ
PASS

HL

RETURN

DATA IN BCD FORMAT

: POINTER TO DATE/TIME BUFFER

HL

:UNCHANGED

(HL)

:YEAR

(HL + 1)

:MONTH

(HL+ 2)

:DAY

(HL + 3)

:HOUR

(HL+ 4)

:MINUTE

(HL + 5)

:SECOND

DATE CORRECTED FOR END OF YEAR
USES

AF

BC

DE

HL

PRESERVES

AF

BC

DE

HL

CONTROL REGISTER AND MDX-BCLK DEFINITIONS

=0070

28 BCLK

EQU

70H

BCLK BASE PORT ADDRESS

=0070

29 DATA

EQU

BCLK

BCLK DATA PORT

=0071

30 PULS

EQU

BCLK+1

BCLK PULSE PORT

=0080

33 LEP

EQU

80H

LEAP YEAR BIT

=0060

34 DAY

EQU

60H

DAY BIT

=0020

35 MON

EQU

20H

MONTH BIT

=0010

36 HRS

EQU

10H

HOUR BIT

=0008

37 MIN

EQU

08H

MINUTE BIT

=0004

38 SEC

EQU

04H

SECOND BIT

=0002

39 CALR

EQU

02H

CALENDAR RESET BIT

=0001

40 CLKD

EQU

01H

CLOCK RESET AND DISABLE

=0007

43 LFLAG

EQU

7

LEAP YEAR TEST FLAG

=0007

44 EYEAR

EQU

7

END OF YEAR TEST FLAG

47

GLOBAL READBACK

=0000'

50 READCK:

IVE-27

III

CLOCK CALENDAR READ SOFlWARE (CONT.)
Figure 5

LOC

OBJ.CODE

0000
0001

F5
C5
D5

0002

=0003'
0003
0004

...

,~' :,

MOSTEK MACRO-80 ASSEMBLER V2.2
OP8RD
OPSRD
OPSRD

. SOURCE-STMT

PASS2

51

PUSH

AF

52

PUSH

53

PUSH

BC
CE

PAGE 2
REL

56 LEPCK:

7E

57

LC

A.(HL)

23

58

INC
DR

HL

GET CURRENT YEAR OUT OF BUFFER
POINT TO MONTH DATA

A
Z,NLEAP-$

NON-LEAP FOR YEAR 2000

13H
Z,ISLEAP-$

LEAP FOR EVEN DECADES

0005
0006

B7

59

280C

JR

0008
OooA

ES13
2804

60
61
62

OOOC
OooE

FE12

JR
CP

2004
=0010'

0010

CBF9

0012

1802

0014

=0014'
CB89
=0016'

,

STMT-NR

63
64
65ISLEAP:

AND

JR

12H
NZ,NLEAP-$

66
67
68 NLEAP:

SET

LFLAG,C

JR

SETFLG-$

SET LEAP YEAR FLAG

69
70 SETFLG:

RES

LFLAG,C

CLEAR LEAP FLAG

0016

3E04

71

LD

D370
DB70
47

72

OUT

A,SEC
(DATA),A

SET CONTROL REG. FOR SEC READ

0018
001A
001C

73
74

IN
LD

A,(DATA)
B,A

GET SECOND DATA

0010

C5

75

SAVE ON STACK

E5

001F
0020

E8
216400'

76
77

PUSH
PUSH

BC

001E

0023
0025
0027

CB79
2003
215FOO'
=002A'

002A

060A

002C

OE70

002E

=002E'
EDA3

EX

HL
DE,HL

78

LD

HL,LTABLE

LEAP YEAR TABLE IN HL

79

BIT
JR

LFLAG,C
NZ,OVER-$

CHECK FOR LEAP YEAR

LD

HL,TABLE

NON-LEAP TABLE IN HL

LD
LD

B,5*2
C,DATA

5 BYTES TO WRITE, 5 TO READ

80
81
82 OVER:
83
84

BUFFER ADDRESS IN DE

85 LOOP:
86

CUTI

OUTPUT CONTROL BYTE,
INCREMENT TABLE ADDRESS (HL)

0030

OB70

89

IN

A,(DATA)

DECREMENT COUNTER (B)
INPUT DATA

0032

12

90

STORE IN BUFFER

13
10F8

91
92

LD
INC

(DE),A

0033
0034

DE
LOOP-$

INCREMENT BUFFER POINTER

0036
0037

18

95
96

DE
A,(DE)

POINT TO SECONDS IN BUI;FER

1A

0038
0039

E1
C1

97
98

003A

BB

100

DJNZ

DEC
LC
POP
POP

HL
BC

CP

8

DECREMENT COUNTER (B)

GET FIRST SECOND READING
OFF STACK

IVE-28

CHECK FOR CLOCK ROLL OVER

CLOCK CALENDAR READ SOFTWARE (CONT.)
Figure 5
MOSTEK MACRO-SO ASSEMBLER V2.2
OPSRD
OPSRD
OPSRD

PAGE 3
REL

LOC

OBJ.CODE

003B

20C6

101

JR

NZ.LEPCK-S

003D
003F

CB7E
2008
=0041'

BIT
JR

EYEAR.(HL)
NZ.ENDYR-$

CHECK FOR END OF YEAR
GO FIX IT

0041
0042
0044
0045
0046
0047
0048

AF
0370
23
D1
D1
F1

XOR
CUT
DEC
pop

A
(DATA).A
HL
DE

CLEAR CONTROL REGISTER
RESTOREHL

POP
POP
RET

BC
AF

RESTORE REGISTERS

0049

46

104
106
106 DONE:
107
108
109
110
111
112
113
114 ENDYR:
116

LD

B,(HL)

004A
004C
004E

CBB8
3E62
D370
1804
=0052'
D371
D371
=0056'
10FA

121
122 ADVN:
123
124

RES
LD
OUT
JR

EYEAR.B
A.DAY+CALR
(DATA),A
UPDATE-$

GET MONTH DATA
IT'S REALLY COUNT OF DAYS PAST
END OF YEAR
MASKFl,AG
SETUP FOR DAY BUMP AND CAL RESET

OUT
OUT

(PULS).A
(PULS),A

125 UPDATE:
126

DJNZ

ADVN-$

129
130
131
132
133
134

DEC
LD
INC
DAA
LD
JR

HL
A.(HL)
A

INCREMENT YEAR (IN BCD)

(HL),A
LEPCK-$

RE-READ CLOCK

C9
=0049'

0050
0052
0054
0056

0058
0059
005A
005B
005.C
0060

28
7E
3C
27
77
18A4

=006F'
005F
0060
0061
0062
0063

20
60
10
08
04

0064
0066
0066
0067
0068

AO
EO
10
08
04

=0064'

STMT-NR

SOURCE-STMT

118
119
120

137 TABLE:
138
139
140
141
142

PEFB
DEFB
DEFB

145 LTABLE:
146
147
148
149
150

DEFB
DEFB
DEFB
DEFB
DEFB

DEFB
DEFB

PASS2

MON
DAY
HRS
MIN
SEC

MON + LEP
DAY + LEP
HRS
MIN
SEC

IVE-29

;

RE-READ CLOCK IF ROLL OVER OCCUR ED

INCREMENT DAYS

POINT TO YEAR DATA

II

CLOCK CALENDAR READ SOFTWARE
Figure 6

LOC

OBJ.CODE

. MOSTEK MACRO-BO ASSEMBLER V2.2
OPSWR
OPSWR
·OPSWR
PASS2

SOURCE-STMT

STMT-NR

PAGE 1
REL

CPMPLETE CLOCK AND CALENDAR SET
DATA IN
HL
(HL)
(HL + 1)
(HL + 2)
(HL + 3)
(HL + 4)
(!-iL + 5)

PASS

BCD FORMAT
:POINTER TO CLOCK SET BUFFER
:DESIRED YEAR SET
:DESIRED MONTH SET
:DESIRED DAY SET
:DESIRED HOUR SET
:DESIRED MINUTE SET
:DESIRED SECOND SET

DATE CORRECTED FOR END OF YEAR
USES

AF

BC DE

HL

PRESERVES

AF

BC DE

HL

CONTROL REGISTER AND MDX-BCLK DEFINITI.ONS

;0070
;0070
;0071

;OOBO
;0060
;0020
;0010
;OOOB
;0004
;0002
;0001

;0007
;0007
;0004

;0000'
0000
0001

F6
C5

24 BCLK
25 DATA
26 PULS

EQU
EQU
EQU

70H
BCLK
BCLK+1

BCLK BASE PORT ADDRESS
BCLK DATA PORT
BCLK PULSE PORT

29 LEP

EQU

30
31
32
33
34
35
36

EQU
EQU
EQU
EQU
EQU
EQU
EQU

BOH
60H
20H
10H
OBH
04H
02H
01H

LEAP YEAR BIT
DAY BIT
MONTH BIT
DAY BIT
MINUTE BIT
SECOND BIT
CALENDAR RESET BIT
CLOCK RESET AND DISABLE

39 LFLAG
40 EYEAR
41 EOT

EQU
EQU
EQU

7
7
04H

LEAP YEAR TEST FLAG
END OF YEAR TEST FLAG
FLAG FOR END OF TABLE

44

GLOBAL SCLO---....~MONTH READ/SET
CLOCK RESET
CALENDAR RESET

INCREMENT
LEAP
MONTH

INCREMENT
NON·LEAP
MONTH

CONTROL REG.
BITS SET: (E1 H)
DAY READ/SET
DAY SelECT
CLOCK DISABLE
LEAP YEAR SELECT

CONTROL REG.
BITS SET: (61H)
DAY READ/SET
DAY SELECT
CLOCK DISABLE

YES

IVE-38

CLOCK CALENDAR SET FLOW CHART (Cont'd.)
Figure 8

INCREMENT
LEAP DAY

CONTROL REG.
BITS SET: (11 H)
HOUR READ
CLOCK DISABLE

INCREMENT
NON-·LEAP
DAY

YES

NO

CONTROL REG.
BITS SET: (09H)
MINUTE SET
CLOCK DISABLE

INCREMENT
MINUTE
TO SET HOUR

CONTROL REG.
BITS SET: (09H)
MINUTE READ/SET
CLOCK DISABLE

IVE-39

•

CLOCK CALENDAR SET FLOW CHART (Cont'd.)
Figure 8

YES

INCREMENT
MINUTES

CONTROL REG.
BITS SET: (05H)
ECOND READ/SE
CLOCK DISABLE

YES

INCREMENT
SECONDS

CLEAR
CONTROL
REGISTER

RETURN

IVE·40

CONNECTORS
Function

Description

Mating Connector

STD BUS

56-pin, dual

Viking 3VH28/1 CE5 (Printed circuit
Viking 3VH28/1 CND5 (Wire-wrap)
Viking 3VH28/1 CN5 (Solder Lug)

CTC Interface

2-position Housing
Contact

AMP 87499-3
AMP 87046-1

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NO.

MDX-BCLK

Battery Clock Module with Technical Manual

MK77976

MDX-BCLK
Technical Manual

MDX-BCLK Technical Manual only

4420065

•

IVE-41

IVE-42

1983 COMPUTER PRODUCTS DATA BOOK
,"

~,,'~:. ,.~

..

~. "',\.;<~.'~:

,.~~.

'::l','.

"','.

MD Series Accessories
:.,;.) .
-:. .

'~",'

IJ

COMPUTER
PRODUCTS
DIVISION

UNITED

TECHNOLOGIES
MOSTEK

ACCESSORIES
(MO-ACC)
INTRODUCTION
The following accessories are available to aid in the design,
development, and production of products designed around
the Mostek MO Series Z80* microcomputer modules:
MOX-WW1
MOX-WW2
MO-EXT

Wire-wrap card with bussed power
and ground
Wire-wrap card without bussed power
and ground
Extender card

MO-2320CE-C
MO-2320TE-C
MO-TIY-C
MO-PPG-C

25-pin "0" female MO OCE cable
25-pin "0" male MO OTE cable
15-pin Molex-TIY cable
25-pin "0" female PROM Programmer
(PPG-8/16) interface cable

MO-CC6
MO-CC6WM
MO-CC10
MO-CC12A
MO-C16

6-slot card cage
6-slot wall mount card cage
10-slot card cage
12-slot card cage
16-slot card cage

The MOX-WW2 (MK77952) is a wire-wrap card with all
plated-through holes on a 0.1 DO-inch grid. This allows
mounting of both DIP sockets and discrete components for
circuit fabrication. The plated-through holes accept 0.025inch square posts. A photo of the WW2 board is shown in
Figure 2.

MDX-WW2 (MK77952) PHOTO
Figure 2

WIRE WRAP CARDS
The MOX-WW1 (MK77959) is a wire-wrap card with
bussed power and ground lines on the board to facilitate
fabrication of circuits using wire-wrap sockets. A series of
plated-through holes are available on the top ofthe card for
mounting connectors. A photo of the board is shown in
Figure 1.

MDX-WW1 (MK77959) PHOTO
Figure 1

·zao is a registered Trademark of ZILOG

EXTENDER CARD
The MO-EXT (MK77953) is an extender card that allows the
cards in the card cage to be extended outside the cage for
easy access. A photo of the extender card is shown in Figure

3.
MD-EXT (MK17953) PHOTO
Figure 3

IVF-1

CABLES

CARD CAGES

The MO-2320CE-C (MK77955) is a cable designed to
interface with either the MOX-SIO or MOX-EPROM/UART
card. One end has a 26-pin socket to connect to the board.
The other end has a 25-pin female "0" type connector. This
cable allows the MD board to provide a Oata Communication Equipment interface. A drawing of the cable and
interface is shown in Figure 4.

There are five versions o~'~ard cages'avai,lable fr~~ Mostek,
they are:
MO-CC6 (MK77973)
MO-CC6-WM (MK77978)
MO-CC10 (MK77989)
MO-CC12A (MK77970)
MO-CC16 (MK77977)

MD-232DCE-C (MK77955)
Figure 4

All models have connectors on 0.75-inch centers. MO-CC6
and MO-CC12A have the cards inserted horizontally while
the MO-CC6-WM, MO-CC10, and MO-CC16 have the
cards inserted vertically.

MOX·SIO
MOX·OEBUG
MOX·EPROMI
UART

The MO-2320TE-C (MK77970) is a cable designed to
interface with either the MOX-SIO or MOX-EPROM/UART
card. One end has a 26-pin socket to connect to the board.
The other end has a 25-pin male "0" type ·connector. This
cable allows the MO board to provide a Oata Terminal
Equipment interface. A drawing of the cable and interface is
shown in Figure 5.

The MO-CC6 is a six-slot card cage fabricated out of
aluminum. Its basic purpose isto be mounted to a baseplate,
allowing the cards to be inserted horizontally. The card edge
extending from the top ofthe cage is not intended tobe used
as a bus extension mechanism. The thickness of the
motherboard prohibits standard connectors to fit on it.
Figure 8 iIIust~ates the six-slot card cage dimensions.

MD-CC6 DRAWING WITH DIMENSIONS

MD-232DTE-C (MK77970)

Figure 8

Figure 5
MOX·SIO
MOX·EPROMI
UART
MOX·OEBUG

The MO-TIY-C (MK77956) is a cable designed to interface
with either the MOX-SIQ or MOX-EPROM/UART card. One
end has a 26-pin socket to connect to the board. The other
end has a Molex connector that allows connection to the
terminal block in a teletype. A drawing of the, cable and
interface is shown in Figure 6.

>-

MD-TTY-C (MK77956)
Figure 6
MOX·SIO
MOX·EPROMI
UART
MOX-OEBUG

The MO-PPG-C (MK79957) is a cable designed to interface
the MOX-PIO with the PPG-8/16 PROM Programmer. A
drawing of the cable and interface is shown in Figure 7.

MD-PPG-C (MK77957)

The MO-CC6-WM is a card cage fabricated from steel as
opposed to aluminum. Its basic purpose is for wall
mounting; for example in a NEMA enclosure for industrial
applications. Figure 9 illustrates the six-slot wall-mount
card dimensions.

Figure 7

EJ
IVF-2

MD-CC6-WM DRAWING WITH DIMENSIONS

MD-CC6 AND MD-CC6 WM MOTHERBOARD
WITH DIMENSIONS

Figure 9

Figure 10

5.140 -----t

Ilr:;::=:~4.~630-==~1---r

-.-.

.

-.--------

~
The six-slot motherboard (for both CC6 and CC6-WM) has
eight plated-through holes in which to insert 16-guage wire
(maximum) for power and ground connections. The holes
are denoted from left to right on the fab side of the
motherboard (see Figure 10 for a drawi ng of the
motherboard). In addition, there are five pins located on the
lower right edge ofthe board for connecting a remote +12 V
lamp. The /PBRESET line is also connected to these pins if
the user desires a remote reset switch. The hole and pin
assignments are shown in Table 1 and Table 2.

0

UNUSABLE AREA

:~-~.~-~~--=:~J'~~;r

r.m--=-:=--........,...-

••

THIS AREA FOR POWER INPUT

The MD-CCl O(MK77989) is a ten-slot card cage fabricated
from steel. Figure 11 slows the dimensions of the MD-CCl 0
card cage. Power connections to the MD-CCl Oare provided
by a 2-pin and 4-pin AMP Universal MATE-N-LOK
connector. There is also a 3-pin Universal MATE-N-LOK
connector for connecting a remote power lamp and reset
button. The pins assignments for these connectors are
shown in Table 3.

MD-CC10 DRAWING WITH DIMENSIONS
Figure 11

INTERCONNECTION OF POWER PLANE
TO STD BUS-CC6, CC6-WM
Table 1

CONNECTION
PINS (Left to Right)

DESIGNATOR

STD BUS
PINNO.

1,2
3
4, 5
6
7
8

GND
-12V
+5V
+12 V
-5 V
AUX. GND

3,4
56
1,2
55
5, 6
53,54

5.2

,
I

)
. ' / i ir20
/'
A '

7.89 (DEPTH)

/
/ ' /'

/

I

(EDGE
TO HOLE)

7.490 (HOLE
TO HOLE)

CONNECTION FOR REMOTE LAMP AND RESET
SWITCH - CC6. and CC6-WM
Table 2

CONNECTION

DESIGNATOR

5
4
3
2
1

+12V
GND
/PBRESET
GND
KEY

The MD-CCl Ocard cage motherboard is terminated at both
ends of the bus with a special RC network designed to
reduce signal ringing. The CCl 0 motherboard is shown in
Figure 12.

IVF-3

II

MD-CC10 MOTHERBOARD WITH DIMENSIONS

MD-CC12A DRAWING WITH DIMENSIONS

Figure 12

Figure 13

r

6.80

I

~.
7.25

COMPONENT SIDE

The MD~CC12A (MK77970) is a twelve-slot card cage
faricated.from aluminum. Figure 13 shows the dimensions
of the MD-CC12A card cage. Power connections to the
MD-CC12A are accomplished via a 4-pin and 2-pin AMP
Universal MATE-N-LOK connector. In addition, there is a
3-pin Universal MATE-N-LOK connector for connecting a
remote power lamp and a. remote reset button. The pin
assignments for these connectors are shown in Table 3,
with holes denoted from the component side left to right.

The MD-CC12A card cage motherboard is terminated at
both ends of the bus with a special RC network designed to
reduce signal ringing. The CC12A motherboard is shown in
Figure 14.
MD-CC12A MOTHERBOARD
Figure 14

.1I1MlDfA.

8 HOll!.

INTERCONNECTION OF POWER PLANE TO
STD BUS - CC10, CC12A

.000DIIIo.
872 HOLES

Table 3

STD BUS
PIN
CONNECTION
PINS (Left to Right) DESIGNATOR DESIGNATOR
4-Pin
+5V
GND
.-12 V
+12 V

1,2
3,4
56
55

2

AUXGND
+5V

53,54
5,6

1
2
3

GND
+12 V
/PBRESET

3,4
55
48

1
2
3
4
2-Pin
-1

3-Pin

The MD-CC16 is a 16-slot card cage which can be wall
mounted or rack mounted. It is constructed from steel giving
it greater strength for industrial environments. (See Figure
15 for a drawing of the 16-slot card cage dimensions). There
are two AMP MATE-N-LOK connectors (a 9cpin and 6-piri)
which connect power to the card cage. Note that the
connectors can be placed in one to two orientations, either
on the left side or the top of the card cage (see Figure 15).ln
addition, the··right side of the cage has a rectangular hole
through which cables can be passed for connection to the
MD cards. Table 4 9ivlls the two connector pinouts for
CC16.

IVF-4

INTERCONNECTOR OF POWER PLANE TO
STD BUS - MD-CC16
Table 4

CONNECTION
PINS

MD-CC16 MOTHERBOARD WITH DIMENSIONS
Figure 16

,

CQfolN

STD BUS
PIN
DESIGNATOR DESIGNATOR

•a

9-Pin
1,2,
3
4,5, 7,8
6
9

+5V
+5 V SENSE
GND
GND SENSE
No connect

1,2
3,4

/PBRESET
AUXGND
GND
+12 V
-12V

48
53,54
3,4
55
56

9

0

0

•

0

002

3

7

0

00'
4

6-Pin
1
2
3,4
5
6

'[TI'
6

0

0

2

4

0

0

1

I/O Expand/Memory Expansion

The mating connectors for the above pins are listed in the
CONNECTORS section.
MD-CC16 DRAWING WITH DIMENSIONS
Figure 15

Each card cage motherboard has two stake pins (lOEXP and
MEMEX) which are connected to bus pins 35 (IOEXP) and
36 (MEMEX). If the IOEXP (I/O Expand) pin is not used to
must be strapped to the logic ground stake pin opposite pin
IOEXP.lf the MEMEX (Memory Expansion) pin is not used it
must be strapped to the logic ground stake pin opposite pin
MEMEX.
Card Priority
If a card slot is not used, the user can maintain the priority
interrupt chai n by strappi ng across the unused connector to
terminal points provided on the assembly side of the
motherboard of each card cage (opposite pins 51 and 52).
The interrupt priority for the MD-CC6 is highest at the
bottom of the cage. The priority for the MO-CC6-WM,
MD-CC10, and MD-CC16, is from right to left as viewed
from the front, with the highest priority board at the right
side.
The interrupt priority for the MD-CC12A card cage is from
bottom to top on the right, then from bottom to top on the left
side when viewed from the front with components facing
upward. Therefore, the bottom-most board on the right side
is the highest priority board, and the top-most board on the
left side is the lowest priority board.

The MD-CC16 card cage motherboard is terminated at both
ends of the bus with a special RC network designed to
reduce signal ringing. The CC16 motherboard is shown in
Figure 16.

IVF-5

III

CONNECTORS

FUNCTION
STD BUS

MATING
CONNECTOR

CONFIGURATION
56-Pin

PRINTED CIRCUIT
Viking 3VH28/1CE5
WIRE WRAP
Viking 3V38/1CND5

0.125 in. centers

SOLDER LUG
Viking 3VH28/1CN5
Card Cage
Mating
Connectors

CC10

2-Pin SIP

PLUG HOUSING
AMP 350777-1
PLUG HOUSING
AMP 350766-1
PLUG HOUSING
350779-1
Socket AMP
350551-1

3-Pin SIP
4-Pin SIP
Contacts

CC12

2-Pin SIP

PLUG HOUSING
AMP 350777-1
PLUG HOUSING
AMP 350766-1
PLUG HOUSING
AMP 350779-1
Socket AMP
350551-1

3-Pin SIP
4-Pin SIP
Contacts

CC16

6-Pin

PLUG HOUSING
AMP 350715-1
PLUG HOUSING
AMP 350720-1
Pin AMP 350552-1

9-Pin
'1.'"

Contacts

IVF-6

ORDERING INFORMATION

DESIGNATOR

DESCRIPTION

PART NO,

MDX-WW1

Wire-wrap card with bussed power and ground,

MK77959

MDX-WW2

Wire-wrap card without bussed power and ground,

MK77952

MD-EXT

Extender Card

MK77953

MD-232DCE-C

25-pin "0" female MD cable

MK77955

MD-232DTE-C

25-pin "0" male MD cable

MK77970

MK-TIY-C

15-pin Molex-TIY cable

MK77956

MD-PPG-C

25-pin "0" female PROM Programmer (PPG-8/16) interface
cable

MK77957

MD-CC6

6-slot card cage with STD BUS motherboard

MK77973

MD-CC6-WM

6-slot wall mount card cage with STD BUS motherboard

MK77978

MD-CC10

1O-slot card cage with STD BUS motherboard

MK77989

MD-CC12A

12-slot card cage with STD BUS motherboard

MK77990

MD-CC16

16-slot card cage with STD BUS motherboard

MK77977

•
IVF-7

IVF-8

fj

UNITED
TECHNOLOGIES
MOSTEK

COMPUTER
PRODUCTS
DIVISION

MATRIX-80/0EM TO (MO-PTR2-C)
CENTRONICS PRINTER CABLE (MK79099)

MATRIX-OEM

25-PIN
FEMALE
"O"TYPE

~---8~--~~~~~1
36-PIN
FLAT
RIBBON

MD-PTR2-C DESCRIPTION
The MO-PTR2-C (MK79099) is an 8-foot long cable
designed to interface the MATRIX-SO/OEM enclosure to a
parallel Centronics printer. One end of the cable has a

OELTA
RIBBON

CENTRONICS
PRINTER

25-pin male "0" type connector to connect the MATRIX80/0EM (I/O panel J1.) The other end has a 36-pin delta
ribbon plug connector that will mate with the standard
Centronics parallel interface connector on the printer.

IVF-9

ORDERING INFORMATION
Designator

Description

MD-PTR2-C

MATRIX-80/0EM to Centronics

Part Number

Pri nter Cable
Data Sheet Only

IVF-10

MK79099

!t

COMPUTER
PRODUCTS
DIVISION

UNITED

TECHNOLOGIES
MOSTEK

MOX-CPU3/4 TO CENTRONICS (MO-PTR1-C)
PRINTER CABLE MK79098

8FT _ _
MDX-CPU3
MDX-CPU4

26-PIN
FEMALE
FLAT
RIBBON

MD-PTR1-C DESCRIPTION
The MO-PTR1-C (MK79098) is an 8-foot long cable
designed to interface the MOX-CPU3 or MOX-CPU4 STO
modules to a parallel Centronics printer. One end of the

36-PIN
DELTA
RIBBON

CENTRONICS
PRINTER

cable has a 26-pin socket to connect to the STO Printer bus
board. The other end has a 36-pin delta ribbon plug
connector that will mate with the standard Centronics
parallel interface connector.

..

IVF-11

ORDEf'I,NG;INFORMATION
,"

Designator i,

MD-PTR1-C

MDX-CPU3/4 to Centronics
:

Printer Cable

,

"

Part ~l.Irnber

Description

,

Data Sheet Only

IVF-12

MK79098

I!I

UNITED

COMPUTER
PRODUCTS
DIVISION

TECHNOLOGIES
MOSTEK

MO-PWRI

MK77964

FEATURES
o Triple output supply: +5 volts and

MD-PWR1 PHOTO
Fi!:!ure 1

± 12 volts

o 1151230 vac ± 10%, 47-440 Hz
o Remote sensing on 5V output
o Overvoltage protection on 5V output
o ± 0.05% regulation
o Foldback current limit
o I.C. regulated design
o UL recognized
o CSA certified
o STD or STD-ZBO BUS compatible
DESCRIPTION
The MD-PWR 1 is an open-frame power supply. Designed to
furnish power for the MDX-PROTO kit, the MD-PWR1
operates from 115/230 vac ± 10% at a frequency range of

47 to 440 Hz: This input power is then transformed and
regulated into the three output voltages, +5 VDC and ± 12
VDC. The open-frame design allows for adequate cooling.

IVF-13

MD·PWR1 .BLOCK DIAGRAM
Figure 2
"

\

'.,:

+5V

+5VDC

REGULATOR

117/230VAC

-r=--

XFMR

GND

+12VDC
±12V

i-'---i

ACINPUT
1151230 vac, 47·440 Hz

REGULATORS

-12VDC

REMOTE SENSING
Provided on 5V output, open-sense-Iead protection built-in

DC OUTPUT
+5V@6.0A
±12V@1.7A
(Derate output current 10% for 50 Hz operation)

STABILITY
± 0.3% for 24 hours after warm up

LINE REGULATION
±.05% for a 10% line change

TEMPERATURE RATING
O°C to 50°C full rated
(derate linearly to 400,1, at 70°C)

LOAD REGULATION
± .05% for a 50% load change

TEMPERATURE COEFFICIENT
± .03%;oC max.

OUTPUT RIPPLE
3.0 mV Pk-Pk max.

EFFICIENCY
5V output: 45%, ± 1 2V output: 55%

TRANSIENT RESPONSE
30 microseconds for 50% load change

VIBRATION AND SHOCK
Per MIL-STD-810B

SHORT CiRCUIT AND OVERVOLTAGE PROTECTION
Automatic current limitlfoldback
REVERSE VOLTAGE PROTECTION
Provided on output and pass element

SIZE
4.75 in (120.7 mm) wide x 11.0 in (279.4 mm) long x
2.75 in (69.9 mm) high

OVERVOLTAGE PROTECTION
Optional on ± 12V outputs

WEIGHT
8 Ibs (3.6 kg)

ORDERING INFORMATION

DESIGNATOR

DESCRIPTION

PART NO.

MD-PWR1

Power Supply Module with prestripped and tinned wires

MK77964

IVF-14

I!I

UNITED
TECHNOLOGIES
MOSTEK

COMPUTER
PRODUCTS
DIVISION
MO-RMC12

FEATURES

MD-RMC12
Figure 1

o Standard 19-inch rack-mountable chassis
o Removable structural-foam front panel for internal
access
o Front panel RESET switch and POWER indicator
o 12-slot card cage
o Cards mounted horizontally for ease of cooling and cable
routing
o Self-contained power supply and 115 CFM fan
o 100/115/230 Volt 50/60 Hz operation
GENERAL DESCRIPTION
The Mostek MD Series Rack Mounted System (MDRMC12) provides rack mounting for the MD series
Microcomputer modules. The system features a selfcontained power supply designed to work on voltages and
frequencies available worldwide. A structural foam front
panel is provided with a system RESET switch and POWER
indicator. The front panel is designed with quick-release ball
studs so that it can be removed quickly for access to internal
components. The card cage and power supply may be
removed individually from the front or top for improved
access. The cards are mounted in a horizontal plane with
provisions for cabling over the card cage to the rear 110
panel. The back panel has an I/O panel prepunched for
fifteen 25-pin D type connectors, one 50-pin D connector,
and one BNC connector. AC components on the back panel
include: On/Off switch, voltage selection switch, fuse
holder (3 AG or 5 x 20 mm), and AC input receptacle/line
filter.

attachment is by the 3 pin connector J15. The front panel
RESET switch is connected to pin 48 (/PBRESET) or the
system bus, which initializes the system upon depression.
The pinout for connector J15 is shown in Table 2.
One other connector is provided to the signals /MEMEX
(pin 36) and /IOEXP (pin 35) to ground. These signals are
not used by the Mostek STD-Z80 BUS, but may be tied low
for compatibility with other boards by inserting minijumpers or wire. Wrap wires on J16 are shown in Figure 2.

J16 WIRE WRAPS
MOTHERBOARD CONNECTORS

Figure 2

The twelve connectors (J1-J12) mounted on the motherboard are dual readout, 56 pin .125" centers, card edge
style. Power is connected to the motherboard by three
connectors, J13, J14, and J15. The pinout for J13 and J14
is shown in Table 1.
The motherboard is also the attachment pointforthe RESET
button and POWER indicator on the front panel. This
IVF-15

IMEMEX

GND

IIOEXP

GND

J16

II

.J13 ANO J14 PINOUT
Table 1
J13

Pin

Wire Color

Connector

+5
GNO
-12
+12

1
2
3
4

Red
Black
White
Blue

AMP Universal Mate-n-Iok
PCB Pin Housing #350792-1 (supplied)
Plug Housing #350779-1 (Using four Socket Contacts)

J14

Pin

Wire Color

Connector

AUXGNO

1
2

Not supplied
Not supplied

J15

Pin

Wire Color

Connector

GNO
+12
IPBRESET

1
2
3

Black
Orange
Yellow

AMP Universal Mate-n-Iok
PCB Pin Housing #350789-1 (supplied)
Plug Housing #350-766-1
(Using 3 Socket Contacts)

-5

I

AMP Universal Mate-n-Iok
PCB Pin Housing #350786-1
Plug Housing #305777-1 (Using two Socket Contacts)

J15 PINOUT
Table 2

MOTHERBOARD INTERRUPT PRIORITY CHAIN
The motherboard of the MO-RMC12 CPU subsystem is
designed to allow a daisy chain of interrupt logic between
boards. Thiswiring is accomplished by connecting PCO (pin
51) to PCI (pin 52) of the next lower priority board from slot
6R to slot 1R, to 6L to 1L. The twelve-slot daisy chain priority
of the motherboard is shown in Figure 3. Provision has been
made for jumper wires in case the user wishes to leave a
slot open while still preserving the daisy chain. This is
provided by wires E1-E11, with proper connection shown in
Table 3.

JUMPER WIRE CONNECTIONS WITH DAISY CHAIN
PRIORITY
Table 3

If no card is in:

TWELVE-SLOT PRIORITY CHAIN
Figure 3

lOWEST
PRIORITY
1l I

11R

Connect

To

J1

6R

J2

5R

E1

J3

4R

E2

E3

J4

3R

E3

E4

J5

2R

E4

E5

J6

1R

E5

E6A

J7

6L

E6B

E7

J8

5L

E7

E8

J9

4L

E8

E9

E2

J10

3L

E9

E10

J11

2L

E10

E11

J12

1L

211

12R

311

13R

I/O CONNECTORS

411

14R

Sll

ISR

Sll

HIGHEST
ISR PRIORITY

The rear panel is shipped with no internal liD cabling
connectors installed. This prepunched panel has provisions
for 15 25-pin "0" subminiature connectors, one 50-pin "0"
type connector, and one BNC bulkhead connector. The
typical connectors used are shown in Table 4. Should the
user desire to fabricate his own liD panel, the panel is
simply held in place by four screws.

IVF-16

United States systems (60 Hz) are shipped with a 3 AG (3
Amp) fuse in a grey fuse insert. European systems (50 Hz)
are shipped with a 5 x 20 mm (3 Amp) fuse in a black fuse
insert.

I/O CONNECTORS
Table 4
25-Pin "0"

ANSLEY

609-25S
(Insulation Displacement)

WINCHESTER

49-1125S
(Insulation Displacement)
17-10250
(Discrete Wire)

AMPHENOL

SO-Pin "0"

ANSLEY

SPECIFICATIONS

Electrical Specifications
Input Power: 110/115/230 volts ac
DC Power Available:

609-50F

SWITCH AND INDICATOR FUNCTIONS
Load Regulation:
The MO-RMC12 SUBSYSTEM has three switches and one
indicator light as follows:
Power ON/OFF switch
Power selection switch
POWER ON indicator light
RESET push button

± 10% 50/60 Hz

+5 Vdc at 12 A max.
+12 Vdcat 1.7 A max.
- 12 Vdc at 1.7 A max.

± .05% for a 50% load change

Ouput Ripple: 3.0 mV PK-PK-max
Transient Response: 30 microseconds for a 50% load
change

Right Rear Panel (S1)
Right Rear Panel (S2)
Left Hand Indicator on
Front Panel
Right Hand Button on
Front Panel

Short Circuit and Overload Protection: Automatic current
limit/foldback
Overvoltage Protection: +5 volt output, set to 6.2 ± 0.4 volts

The RESET button connects the /PBRESET signal of the
STO BUS to LOGIC GROUND when pressed. This generates
a RESET signal to the CPU.

Stability: ±o.3% for 24 hours after warm-up

POWER SELECTION

Thermal Protection: Bi-metal thermostat in primary ac line
set to open at 180°F (82°C); close at
130°F (55°C)

The system has a power selection switch (S2) on the upper
right-hand rear panel to select between 115 V ± 10%
operation or 230 V ± 10% operation. Set the switch so the
primary voltage available shows through the hole in the rear
panel. The MO-RMC12 will operate at either 50 or 60 Hz.

Card Cage: 12-slot for MO series module 11.4 cm x 16.5
cm (4.5 x 6.5 in.). Connectors are the 56-pin
edge card specified for the STO BUS
Fusing:

100 V AC OPERATION
The MO-RMC12 CPU subsystem can be operated at 100 V
± 10",{,; however, the following internal wiring changes
must be made.
1. Remove the top from the subsystem.
2. Unsolder the blue/white wire from pin 1 on the power
transformer.
3. Solder the solid blue wire on pin 2 of the power
transformer.
4. Place the power selection switch (S2) in the 115 volt
position.
5. Replace the top lid. System is now configured for 100 volt
± 10% operation.

Line
Voltage

MK77966
(MO-RMC12)

MK77975
(MO-RMC12-50)

100/115 V
230 V

3 Amp 3 AG*
1.5 Amp 3 AG

3Amp5x20 mm
1.5 Amp 5 x 20 mm*

*Configuration as shipped
Line Cord Supplied:
MK77966

MK77975

Similar to Beldon 17250B Similar to Fell Model 1100

FUSE SELECTION

Front Panel Controls: RESET Switch
POWER-ON Indicator

If the voltage selector switch is changed from the factory
setting indicated on the rear panel label, the fuse size may
need to be changed. Refer to the following table for the
correct fuse size for a given voltage selector setting.

Rear Panel Controls: ac
ac
ac
ac

IVF-17

Power ON/OFF
Fuse Holder
Line Receptacle/Filter
Line Voltage Selector

II

Dimensions:

Mechanical Specifications

Height - 7.0 in. (17.8 cm) panel space
7.3 in. (18.5 cm) overall, includes feet

Weight: 25 Ibs (11.3 kg)
Chassis: (a) 19" rack mountable. Using the two rails
supplied
(b) Slide mounting available with optional slide
mounting kit. Requires two inches of panel
space below the unit.

Width - 19.0 in. (48.3 cm) at front panel
17.5 in. (44.5 cm) behind front panel
Depth - 21.6 in. (54.9 cm) with all protrusions
20.0 in. (50.8 cm) without foam front

Order Mostek part number MK78193 SLD Kit.
Operating Temperature Range: O°C to 60°C
ORDERING INFORMATION

DESIGNATOR

DESCRIPTION

PART NO.

MD-RMC12

Rack-mounted CPU subsystem with MD series 12-slot card
cage with U.S. line cord and fuse. 100/1151230 Volts
50/60 Hz AC operation, front panel, support bracket for rack
mounting, and Technical Manual included.

MK77966

MD-RMC12-50

Same as above except with 5 x 20 mm fuse and European
line cord.

MK77975

MD-RMC12
Technical Manual

MD-RMC12 Technical Manual Only

4420086

lVF-18

l!I

UNITED

COMPUTER
PRODUCTS
DIVISION

.TECHNOLOGIES
MOSTEK

RACK-MOUNTABLE
DUAL-FLOPPY-DISK ENCLOSURE
RMDFSS, RMDFSS-50
FEATURES

RMDFSS-FRONT VIEW
1

o Standard 19-inch rack-mountable chassis; 7 -inch panel
height

o

Removable structural-foam front disk bezel for internal
access

o

Front panel power-on indicator

o

Mounts two standard 8-inch floppy disk drives

o

Disk Drives mounted horizontally for low profile

o

Self-contained power supply and 115 CFM fan

o

100/115/230 volt, 50/60 Hz operation

RMDFSS-REAR VIEW

DESCRIPTION

Figure 2

The RMDFSS is a rack-mountable enclosure for two
standard 8-inch floppy-disk drives. The enclosure is fully
self-contained with disk drives, power supply, and fan. The
RMDFSS is compatible with Mostek's zao based
microcomputer systems, but can be used with any system
which has a suitable disk interface.
The power supply works on voltages and frequencies
available world wide, and provides cooling with a 115 CFM
fan. The two single-sided floppy-disk drives are mounted in
a horizontal plane for a low-profile appearance and to
conserve panel height in the rack. The enclosure has an
attractive structural-foam front bezel where the power-on
indicator light is located. Both the front bezel and metal top
have quick release ball studs for easy access to the drives
and power supply for maintenance. The back panel has an
I/O panel pre-punched for one 50-pin "0" type connector
for interface to the disk controller. AC components on the
back panel include: ON/OFF switch, voltage selection
switch (S2), fuse holder, and AC input receptacle/line filter.
The RMDFSS has a standard 19-inch wide chassis and
requires a 7-inch panel clearance. Included are two stainless
steel angle brackets which mount in the user supplied
enclosure to provide support along the sides of the disk unit.
An optional slide kit is available from Mostek by ordering
MK781.93 SLD KIT.

III
UNPACKING AND INSPECTION
Remove the RMDFSS from the shipping container carefully.
Remove the soft foam inserts located in the diskette
openings.
Inspect the subsystem for shipping damage. Check for loose
connectors or wires which may have been unseated during
shipment. In case of damage, place a claim against the
shipping agent.

IVF-19

INSTALLATION

FUSE SELECTION

POVYER SELECTION

If the voltage s~leCtor switch is changed trom the factory
setting (as indicated on the rear panel jabel), the fuse size
may need to be changed. The following table lists the
correct fuse size for a given voltage selection:

The RMOFSs has a power selection switch (S2)(see Figure
2) to ~elect either 115 V ±1 Q% or 230 V ±1 0% operation.
·Set the switch so the pri~ai"yvoitage available shows
through the' 1:10le in the rear panel. The disk module is,
filctory configuredfor either 50 Hz or 60 Hz (verify correct
frequency for your installation on the rear panel label).
The RMOFss can be operated at 100 V ± 10% by making
the following internal wires changes:
1. Remove the top from the subsystem.
2. Unsolder all wires from Pin 1 on the power transformer
except the blue-with-white stripe wire. Connect the
unsoldered wires'to Pin 2 of the power transformer.

100 Volt
3 Amp

115 Volt
3 Amp

230 Volt
1.5Amp

Systems shipped in the United States (60 Hz) have a 3 AG
(3-Amp) fuse in a grey fuse insert. European systems (50
Hz) are shipped with a 5 x 20mm (3-Amp) fuse in a black
fuse insert.
SWITCH AND INDICATOR FUNCTIONS
The RMOFSs has two switches and one indicator with the
following functions:

3. Place the power selection s~itch (52) in thE! 115 V
position.

Power-on Switch (51) - power-on subsystem

4. Replace top lid.

Power Selection Switch (S2) - selects AC line voltage

The subsystem is now wired for 100 V operation (Figure 3).

Power-on Indicator - illuminates when power is on

POWER TRANSFORMER WIRING
Figure 3

.:~.

DISK CONFIGURATION AND INTERFACE CONNECTOR
The floppy-disk drives shipped in the RMOFss are the,
following (or equivalent):
Shugart 800-2 single-sided 50 Hz, PN 853104
, Shugart 800-2 single-sided 60 Hz, PN 850104
The drives are standard mOdels and include write protect.
Jumpers inStalled oli the disk drives are as follows:
Logical Unit (OK 1)
, (left drive viewed
from front)

Logical Unit (OKO)
(right drive viewed
from front)

A
B

A

C

B
C

HL

T2
HL

T1
T2
T3
T4
TS
T6
.OS2

800
051

y
800

Y

All other junipers are open.
The interface connector suPPli6d with the RMOFss subsystem
is a 50-pin, ribbon-contact type,Ansley 609-SOF (6fequivillent).
The mating connector, which is user supplied, is either an
IVF-20

Ansley 609-50M insulation displacement type or the
Amphenol157 series for discrete wire cables. The Shugart
equivalent pinout for the interface connector is shown in
Table 1.
INTERFACE CONNECTOR PINOUT
Table 1

-

HOST SYSTEM'

DISK DRIVE

SUBSYSTEM

1/0 CONNECTOR

~

31

IN USE
HEAD LOAD
INDEX
READY
DRIVE SELECT 1
DRIVE SElECT 2
DRIVE SELECT 3
DRIVE SELECT 4

WRITE DATA
WRITE GATE
TRACK 00
WRITE PROTECT
READ DATA
SEP DATA
SEP CLOCK
GROUND

34

18

35

20

36

22

38

26

39

28

40

30

41

32

42

34

43

36

44

38

45

40

46

42

47

44

48

46

49

48

50

50

L..--

**CAUTION**
High AC voltages are present within the
RMDFSS even with AC switch OFF. Remove
line cord from the wall outlet before servicing.

12

16

1- 25
i---

-

33

DIRECTION SElECT
STEP

The disk drive units must be removed from the subsystem in
order to inspect them or do preventive maintenance. The
following procedure describes disk drive removal:
1. Disconnect all power from the RMDFSS.

RMDFSS

DISK CHANGE

DISK DRIVE REMOVAL

2. Remove lid (top) of RMDFSS by pulling upward to release
fasteners.
3. Remove P1 (signal), P4 (AC), and PS (DC) connectors
from back of each drive. The P5 connectors are removed
by depressing the tabs extending from the sides of the
connectors.
4. Carefully remove the front bezel surrounding the disk
drives. A pull from the front will remove the bezel from
the chassis.
5. Remove the front and rear screws (3) that hold the
bracket below the drive. This connects the baseplate to
the disk drive. Note that two screws are visible from the
front. and the third screw is visible from the top ofthe unit
between disk drive and power supply.
6. Remove the disk drive unit(s) out the front of the
enclosure.

"
i---

J1

7. Lay the drive upside down (on its top) and remove the
four screws that hold the mounting bracket to the drive
frame.

'USER DEFINED CONNECTOR
"ALL ODD NUMBERED PINS ARE GROUNDED

RMDFSS THERMAL PROTECTION

8. Replace the drivels) in reverse order of the above steps.

The RMDFSS contains an integral thermal breaker which
will remove AC power should the interior temperature
reach 82° C(180° F). AC power will be restored automatically
when temperature lowers to approximately 55° C (130° F).
Should this occur, check to see that the fan is operating and
the enclosure venting is not obstructed.

ELECTRICAL SPECIFICATIONS
Input power:

100/1151230 Volts AC

± 10%

50/60 Hz

DC POWER AVAILABLE: (for disk drives)
+5 VDC at 3.0 A maximum
-S VDC at O.S A maximum
+24 VDC at 3.4 A maximum

DISK DRIVE MAINTENANCE
The disk drives require preventive maintenance every 12
months under normal usage. See Table 2 for preventive
maintenance procedures. Cleanliness is very important to
successful operation of the RMDFSS. The fan should be
kept clean and free from dirt and lint. Do not lubricate the
disk drive units; oil will allow dust and dirt to accumulate.
The read/write heads on the disk drive units should be
cleaned only when signs of oxide build-up are present.
Oxide build-up will cause premature failure of diskette
material. Occasional inspection of read/write heads and
diskettes will monitor this condition.

LOAD REGULATION:

± .05% for a 50% load change

OUTPUT RIPPLE: 3.0 mV PK-PK maximum
TRANSIENT RESPONSE:
30 microseconds for a SO% load change
SHORT CIRCUIT AND OVERLOAD PROTECTION:

IVF-21

Automatic current limitlfoldback

II

DISK DRIVE PREVENTIVE MAINTENANCE PROCEDURES
Table 2

FREQ
MONTHS

UNIT
ReadIWrite
head

12

OBSERVE

ACTION

Oxide Build-up

Clean ReadIWrite
Head ONLY IF
NECESSARY

Check for
proper alignment

Align

Read/Write
Head Button

12

Excessive
wear

Replace

Stepper Motor
and Lead Screw

12

Inspect for
nicks and burrs

Clean off oil,
dust, and dirt

Belt

12

Frayed or
weakened areas

Replace

Base

12

Inspect for
loose screws, connectors,
and switches

Tighten screws,
connectors, and
switches

ELECTRICAL SPECIFICATIONS (Cont'd)

MECtiANICAL SPECIFICATIONS

OVERVOLTAGE PROTECTION:

WEIGHT: 501bs. (22.7kg)

+5 volt output, set to 6.2
STABILITY:

± 0.4 volts

OPERATING TEMPERATURE RANGE:

± 0.3% for 24 hours after warmup

4.4°C to 46.1 °C (Disk Drive limitation)
or disk media specification, whichever is more
stringent.

THERMAL PROTECTION:
Bi-metal thermostat on primary AC line
set to cut out at 82° C (180° F)

DIMENSIONS:
Height: 7.0 in. (17.8 cm) panel space
7.3 in. (18.5 cm) overall, (includes rubber
.feet on bottom)

FUSING:

Line Voltage:
110/115V
230 V

60 Hz
3 Amp* 3AG
1.5 Amp 3AG

Width: 19.0 in.(48.3 cm) with front bezel
17.5 in. (44.5 cm) without front bezel

50 Hz
3 Amp 5 x 20mm
1.5 Amp 5 x 20mm

Depth: 21.6 in. (54.9 cm) with all protrusions
20.0 in. (50.S cm) without front bezel

LINE CORD SUPPLIED:
60 Hz (Beldon No. 17250B)
50 Hz (Feller Model 1100)

Humidity: Up to 90% relative, noncondensing

FRONT PANEL INDICATOR:
Power-on
REAR PANEL CONTROLS:
AC Power ON/OFF
AC Fuse holder

AC Line receptacle/filter
AC Line voltage selector
IVF-22

ORDERING INFORMATION

DESIGNATOR

DESCRIPTION

PART NO.

RMDFSS

Rack-mountable, dual floppy-disk drive enclosure
with 8-inch single-sided disk drives
for 100/1151230 volt operation.
Includes interface cable to SDE-RMC6
or MD-RMC12, front bezel. and support
brackets for rack mounting. 60 Hz model

MK78183

RMDFSS-50

Same as above, 50 Hz model.

MK78185

SLD KIT

Slide mounting for above

MK78193

WARNING: This equipment generates, uses, and can radiate radio frequency energy and if not installed and used in
accordance with the instructions manual, may cause interference to radio communications. As temporarily permitted by
regulation it has not been tested for compliance with the limits for Class A computing devices pursuant to Subpart J of Part
15 of FCC Rules, which are designed to provide reasonable protection against such interference. Operation of this
equipment in a residential area is likely to cause interference in which case the user at his measures may be required to
correct the interference.

•
IVF-23

IVF-24

I!I

UNITED
TECHNOLOGIES
MOSTEK

COMPUTER
PRODUCTS
DIVISION

ENCLOSURE
MK77980, MK77981, MK77987, MK77988
FEATURES

SYSTEM PHOTO
Figure 1

o NEMA or 19 inch rack mountable

o

CC16 STO BUS card cage, 0.75 inch centers

o

150 or 300 watt triple output switching power supply

o

Strain relief for liD cables

o

Barrier strip for OC power

o

Fan and buffered air flow for proper cooling

o

STO BUS Industrial Enclosure

DESCRIPTION
The ICS 1 Enclosure provides packaging for STO Bus-based
industrial control systems. Provisions have been made for
adequate power for all sixteen card-cage slots. The optional
300 watt power supply contains sufficient drive to allow an
additional 15 Amp external load (5 volts). In addition, the .
card cage may be quickly disconnected and removed from
the enclosure.
Separate front panels for the card cage and power supply
sections are provided. This allows the user to work on the
cage and board assembly with power applied to the system
with no shock hazard. A disconnect 'switch' in the power
supply section removes AC power if the power supply
section has its cover and cable removed. The AC power is
fused where it enters the system, and the OC power is
internally fused in the power supply. Complete overcurrent,
overtemperature, and overvoltage protection is built in the
power supply.
A special strain relieved port is provided for user liD cabling
to the STO BUS card cage. A terminal str'ip is provided on the
power supply moLinting bracket of sufficient size to connect
up to 16 loads (300 watt supply, 8 loads with 150 watt
supply). Internal mounting provisions are included for a
power-fail-detect circuit and transformer assembly. The
enclosure may be side or top mounted to a wall or in a rack.

El-ECTRICAL SPECIFICATIONS
AC Power Requirements
Nominally 1151230 volts AC. Operating range 90-132
VAC, 47-63 Hz, si ngle phase, internally changeable to 180264VAC.
AC Fuse Requirements
Slow blow fuse only.
150 Watt supply - 115 volt
230 volt
300 Watt supply - 115 volt
230 volt

IVF-25

= MOL 5 Amp 250 volt (3AG)
= MOL 5 Amp 250 volt (3AG)
=MOL 10 Amp 250 volt (3AG)
=MOL 10 Amp 250 volt (3AG)

•

DC Power Available

Power Supply Minimum Loading

Adequate power is provided for a full card cage of STD BUS
compatible boards plus an external load. The user is
cautioned to check total power supply loading and derating
data.

To obtain full current from the +12 and -12. volt outputs of
the 150 Watt supply, the +5 volt output must hllve a
minimum load of 3.6 Amps. The 300 Watt supply requires a
minimum load of 7.2 Amps.

Card Cage Power 150 Watt supply (derated)
+5 volts 5% at 14 Amps
+ 12 volts 5% at 2.5 Amps
-12 volts 5% at 1 Amps

Operating Temperature Range
O°C to. 60°C Ambient
MECHANICAL SPECIFICATIONS

Card Cage Power 300 Watt supply (derated!'
+5 volts 5% at 15 Amps
+12 volts 5% at 2.5 Amps
-12 volts 5% at 2.5 Amps
Extemal Load Power 150 Watt supply (derated)
Nominally 1 Amp DC. May be increased by using fewer
than 16 boards in the card cage. Approximately one Amp
gained for each slot left empty. Absolute maximum is 8
Amps.
External Load Power 300 Watt supply (derated)

Height
Width
Depth
Top Clearance
Bottom Clearance
Front Clearance
Rear Clearance
Right Side Clearance
Left Side Clearance
Weight
ENCL, ENCL2
ENCL 1, ENCL3

13.97 inches
19.0 inches
9.53 inches
NONE
1.75 inches
0.5 inch
N/A
0.5 inch
1.5 inch
321b
281b

354.8 mm
482.6 mm
242.1 mm
44.4mm
12.7 mm
12.7 mm
38.1 mm
14.5 kg
12.7 kg

Maximum 15 Amps DC. May not be increased by leaving
boards out.
Connectors
DC Power Derating
Power supply was derated by 50% at 70 degrees Celsius.
Absolute maximum temperature is 75 degrees C within the
enclosure.

Function

Description

Overtemperature Protection

STD BUS

56-pin, dual

Power supply shuts down when internal temperature
exceeds maximum safe rating. Unit automatically reverts
back to normal operation when internal temperature is
within safe limits.

Mating
Connector
Viking 3VH28/1 CE5
(printed circuit)
Viking 3VH28/1 CND5
(wire-wrap)
Viking 3VH28/1 CN5
(solder lug)

Overload Protection

SYSTEM INSTALLATION

Current foldback overload protects against momentary
overload. Short circuit protection is continuous without
damage; current is limited to approximately 50% of rated
load current. Outputs are dynamically protected from
foldback lock-up. Recovery from overload is automatic.
Outputs 2 and 3 (+12 and -12 volt) are set to 20% of rated
current.

This system may be mounted in a 19-inch RETMA rack, or
mounted to a wall or other vertical surface. AC input power
is brought into the enclosure from the left. Input and output
connectors for signals and de power leave the box from the
right side panel. Thesl:! may then be routed to the external
loads. The input ac power may beclerived from the power
cord assembly, or the cord ,may be removed and % inch
conduit cable may be used to install the power connections.
permanently.

Overvoltage Protection
Output power is removed when the output voltage exceeds
an internally set trip point. The trip point is factory set at 6 to
6.5 volts on the main +5 volt output. This protection is reset
by cycling the input power. Outputs 2 and 3 also have this
feature. Their trip point is set at 110% to 120% of their
nominal output voltage.

Wall Mounting
Two mounting support brackets are bolted to the rear sides
ofthe enclosure with ten (1 0) #8-32 bolts and lock washers
as shown in Figure 2. The top and bottom of the enclosure
may be used as mounting points if desired (see Figure 3).
The complete assembly of enclosure and brackets may then

IVF-26

be mounted using bolts or screws to a flat surface. This
enclosure requires at least a 14-inch by 19-inct) flat surface
for .proper mounting.

inch RETMA rack using mounting bolts or other appropriate
hardware. The enclosure requires a 14-inch high rack
space, plus a 1% inch gap on bottom for cooling purposes.

Rack Mounting

Clearance

The ENCL is shipped ready for rack mounting. The two
mounting support brackets are attached to the front sides of
the enclosure. Ten (10) #8-32 bolts are used to hold the
brackets in place. The enclosure may be installed in a 19-

When installing the enclosure, it is important to allow at
least 1% inch clearance on the bottom to ensure adequate
ventilation.

ASSEMBLY OF MOUNTING BRACKETS FOR WALL
MOUNTING (SIDE)
Figure 2

~.~
Ib

/

/'
~

/,p;
/~

~~

)1)

/

'0

/

/~
".-

~

~

~~

II
• -r---

13.97

I

11.00

DETAIL, MOUNTING SUPPORT BRACKET.

IVF-27

ASSEMBLY OF MOUNTING BRACKETS FOR WAll
MOUNTING (TOP)
Figure 3

a. Remove upper front panel of unit and disconnect the
cable from inside.

V
0'1':
iii
I
l4

l~-O 2

o

2

3

o

o

J6 Header

4
J8:

4-3

PHANTOM EPROM - This jumper, when installed,
allows a peripheral device or controller to disable
the onboard EPROM. Normal shipping configuration is to NOT install J8.

5

o

o

6

7

J8

o

o

I ; Installed jumper, 0 ; open jumper

J8 Header

V-11

o
o
o
o

ROM MEMORY MAPS
Figure 17

MAP

0

1

2

3

4

5

6

7

RAM ADDRESS

FSoo-FFFF
F000-F7FF
U44 ESoo-EFFF
EOOO-E7FF
OSOO-OFFF
DOOO-07FF
CSoo-CFFF
COOO-C7FF
BSoo-BFFF
BOOO-B7FF
• ASoo-AFFF
AOOO-A7FF
9Soo-9FFF
9000-97FF
SSoo-SFFF
s000-S7FF
7Soo-7FFF
7000-77FF
6Soo-6FFF
6000-67FF
5Soo-5FFF
5000-57FF
4SOO-4FFF
4000-47FF
3Soo-3FFF
3000-37FF
2SOO-2FFF
2000-27FF
1SOO-1 FFF
1000-17FF
OSoo-OFFF
0000-07FF

U43
U43
U43

IUtr

U43
U43
U43
U43

-U44U43

U43

U44
U44
U44
U44
U43

~
U43
U43

All unused locations in all maps are RAM

POWER-ON JUMP
J10:

POWER-ON-RESET - This header allows the user
to jump selectively to any 4K byte memory
boundary upon a system reset. This feature may be
defeated by switch S1 located between SK3 and
SK4.lfS1 is OFF. theZSO CPU will resettoaddress
0000 if power is applied or switch S2 is pressed
momentarily. If S1 is ON. the ZSO starting address
will be determined by the jumper positions of J10.

V-12

J10

:1 !

o

0

o

0

J10 Header

:I:

POWER-ON-RESET JUMP ADDRESS
Figure 18

Address

3-4

7-8

1-2

5-6

0000
1000

0
0

2000
3000

0

0

0

4000
5000

0

0

6000
7000

0

0

0

0

0
0

8000

9000

0

0

Aooo

BOOO

0

0

0

0

0
0

0

0

0

0

0

0

0

0

0

COOO

DOOO

*

0

Eooo

FOOO

0

• =Normal shipping configuration

I

=Installed jumper, 0

SIO JUMPERING
J11
J11 :

OTR ASSERTEO -Ifthe user's terminal attached to
the SIO channel A does not support the Oata
Terminal Ready function, then J11 should be
inserted. Normal shipping configuration is with J11
removed.

11 0

01 2

J11 Header

ORDERING INFORMATION
Designator

Description

Part Number

SOlE Combo

SOlE Combo single board computer system
with Technical Manual

MK78202

SOlE Combo
Technical Manual

SOlE Combo Technical Manual only

4420312

V-13

= open jumper

V-14

IJ

UNITED
TECHNOLOGIES
MOSTEK

COMPUTER
PRODUCTS
DIVISION
OEM-80E
MK78122, MK78124-3

FEATURES

OEM-BOE BOARD PHOTO

o l80CPU
o 20K x 8 EPROM
o Accepts 2708, 2716, or 2532 EPROM's
o 256 x 8 static scratchpad RAM on-board
o 16K (4K) x 8 dynamic RAM
o l80 CTC - four counter/timer channels
o Restart to OOOOH or EOOOH (switch option)
DOn-board serial I/O port
o Software-programmable baud rate
o Current loop or RS-232-C (V.24) interface
o Four 8-bit parallel ports with handshake
o Ports buffered with TTL, socket-programmed

16K bytes on-board. The l80 built-in refresh logic reduces
the area taken by the dynamic RAMs to that required by
other manufacturers· 1K byte static RAM, the cost per bit
being significantly reduced. Also on-board are two memorydecoding bipolar PROMs. These allow a wide range of
RAM/PROM/ROM combinations to be selected by the
user; if the exact combination required is not already
supported, new PROMs can be easily programmed.

o Port direction in 4-bit blocks
o Programmable polarity on strobe lines
o Halt lamp
o Power-on-reset logic
o SDE BUS compatible

DESCRIPTION
The OEM-80E is a l80 CPU-based computer board. The
card has sufficient on-board 1/0 and memory to be used in a
stand-alone mode in many applications, yet it is fully
expandable to support more memory and 1/0 in
applications requiring it. The five EPROM sockets on-board
can be strapped to use a number of standard 24-pin
ROM/EPROM products including PROMs and ROMs with
capacities of up to 4K bytes each. The eight RAM sockets
can be strapped for 4K or 16K RAMs, giving a maximum

The user switch-selectable restart address allows the DDT80 debug program to reside in the system without conflict
with the user's own PROM-based software. If a problem
develops, the user can switch from address 0 reset to
address EOQO (where DDT-80 resides) and use the powerful
commands of the 2K byte DDT -80 to localize the problem.
The "E" format' and DIN connectors allow quick integration
into the user's system hardware. Putting all connectors on
one card edge is a unique feature in microcomputer
modules, although it is standard design practice for many
large system builders. The simplified maintenance and
clean cabling made possible by this technique should be
appreciated by all experienced users.

V-15

MEMORY ADDRESSING AND CAPACITY

COUNTER/TIMER CHANNELS.

The recommenped memory map is shown below:
.
0OOO-3FFF PROM (1 TO 16K)
4000-7FFF RAM (4 TO 16K)
8000-DFFF EXTERNAL MEMORY
EOoo-E7FF DDT-80 (2K) ,
.
E8oo-FEFF EXTERNAL MEMORY
FFOO-FFFF SCRATCHPAD RAM (256 bytes,
needed only if DDT-80 is used)

Four counter/timer channels are provided on the card in ,a
l80-CTC chip. One channel is" used as the baud rate'
generator of the serial I/O port. The other three channels
are availabletothe user. The channels may be programmed
as delay generators, event counters or simply discrete
interrupt inputs with a programmable edge trigger. The
device can generate four interrupts.

.

INTERRUPTS
Memory cycle time required for the PROMs is 450 ns.
The OEM-80E has nine on-board interrupts. They are:
One Z80 CPU NMI (non-maskable interrupt)
Four l80 PIO(2) Mod 2 Interrupts
Four l80 CTC Mod 2 Interrupts
More interrupt devices (up to 128 total) can be added to the
SDE bus.

SERIAL I/O PORTS
A UART with 20mA current loop and RS-232-C (V.24)
buffers/drivers provides a seria.!. cornmunication channel
for interiacingto TTY or CRT terminals or serial printers. The
baud rate is softwllre-programmable over the range of 110
to 9600 baud. .
.

PARALLEL I/O PORTS
The four parailelports are designed to allow maximum
flexibility in ma~ching the MOS I/O ports to the real world of
long lines or high voltages. Two ports support bidirectional
TTL I/O with hystersis inputs. The ports can also be
programmed for input or output only. The other ports are
supplied with sockets which support a number of standard
TTL devices for buffering. A list of pin-compatible devices is
given below:

TYPE
7400
7402
7408
7426
7437
7438

USE
16mA TTL inverting output.
TTL inverting input
16mA TTL non-inverting output
16mA high-voltage inverting opencollector output
48mA TTL inverting output
48mA TTL inverting open-coUector output

BUS INTERFACE
All l80 signals are buffered before leaving the OEM-80E.
The buffering protects the MOS components from static
charge during handling and from bus transients which
could otherwise destroy these devices. The bus supports
DMA transfers and the daisy-chained, multi-level interrupt
structure ofthel80. The bus uses hystersis-input receivers
and current-limited bus drivers to improve the noise margin
of the bus. Switching the bus drivers on only when data is
needed and stable further reduces the noise on the bus.
POWER REQUIREMENTS
+5V ±5% at 1.5 A
+12V ±5% at 0.175 A
-12V ±5% atO.l A
OPERATING TEMPERATURE RANGE

BOARD SIZE
233.4mm (9.19 in) X 250 mm (9.84 in.)
CONNECTORS
Two 64-pin DIN 41612 (a-c) indirect, male

V-16

.

ORDERING INFORMATION

D ESIGNATOR

DESCRIPTION

PART NO.

oEM-80E/4

OEM-80E/4 with 4K bytes of RAM (MK4027), 5 sockets for
EPROM or ROM, 2 PIOs with sockets for TIL buffering logic,
CTC, UART, socket for 256-byte scratch-pad RAM and sockets
for memory mapping PROMs.

MK78122

o EM-80E/16

Same as OEM-80E/4 except with 16K bytes of RAM
(MK4116)

MK78124

OEM-80E Operations Manual only

MK78548

V-17

V-18

t!l

UNITED
TECHNOLOGIES
MOSTEK

COMPUTER
PRODUCTS
DIVISION
DCC-80E
MK78192

FEATURES

o

4 independent full-duplex channels

o

Independent programmable Baud-rate clocks

DCC-80E BOARD

o Data rates - 75 to 38.4K bits per second
o Receiver data registers quadruply-buffered
o Transmitter data registers double-buffered
o Asynchronous operation
o Binary synchronous operation
o HOLC or IBM SOLC operation
o Both CRC-16 and CRC-CCITT (-0 and-1) hardware
implemented
o Modem control
o Operates as OTE or OCE
o Serial input and output as RS-232-C
o Address programmable
o SOE BUS compatible
o Each individual channel with NRZI encoder/decoder
o Scrambler cable included

DESCRIPTION
The Multichannel Serial Input/Output Module, OCC-80E,
is designed to be a multiprotocol asynchronous or

synchronous I/O module for the SOE BUS. The module is
designed around the Mostek MK3887™ (Z80-SI0) which
provides two full-duplex serial data channels. Eachchannel
has an independent programmable Baud rate clock
generator to increase module flexibility. Each channel is
capable of handling asynchronous, synchronous, and
synchronous bit-oriented protocols such as IBM BiSync,
SOLC, and HOLC. It can generate CRC codes in any
synchronous mode and can be programmed by the CPU for
any traditional asynchronous format. The serial input and
output data is fully buffered and is provided at the connector
as RS-232-C levels. A modem control section is also
provided for handshaking and status. The module can be
jumper-configured as a data terminal or as a modem in
order to facilitate a variety of interlace configurations.

™SDE SERIES is a trademark of Mostek Corporation

V-19

DCC-BOE BLOCK DIAGRAM
Figure 2

eTe
AS
BAUD
RATE

SK'
CONNECTOR

AND
CHANNEL
TIME
OUT

BUS
SYSTEM
BUS

INTER
FACE
AND

BOARD LEVEL

DECODe

110

BUS

ADDRESS

I--r-"""----

BLOCK DIAGRAM DISCUSSION
Figure 2 is a block diagram of the DCC-BOE module which
consists of eight main elements: The bus interlace and
address decode circuitry, the crystal clock and its associated
conditioning circuitry, the counter timer circuitry (CTC), the
serial input/output circuitry (510), the non-return-zeroinverted (NRZI) encode/decode circuitry, the channel
configuration headers, the RS 232-C interlace circuitry, and
the port configuration headers.
The bus interlace consists of both uni/bi-directional buffers
which reduces the DCC-BOE load on the bus to one LS-TTL
load. The address decoders, in addition to being buffered,
are jumper selectable to any one of the available 16 port
boundaries in the ZBO I/O map. The DCC-80E contains
command registers that are programmed to select the
desired operational mode. The addressing scheme is as
follows: (The X indicates the binary code necessary to
represent which one of the 16 port addresses is selected.)

PORT
PORT
ADDRESS FUNCTION
XOH
X1H
X2H
X3H

.. .
.. .
.. .
.. .

CTC as baud-rate generator for Channel A
CTC as programmable timer
510 Data Input/Output of Channel A
510 StatuS/Control for Channel A

X4H
X5H
X6H
X7H

.. .
.. .
.. .
.. .

CTC as baud-rate generator for Channel B
CTC as programmable timer
510 Data Input/Output of Channel B
510 Status/Control for Channel B

XBH .. .
X9H .. .
XAH .. .
XBH .. .

CTC as baud-rate generator for Channel C
CTC as programmable timer .
510 Data Input/Output of Channel C
510 Status/Control for Channel C

XCH .. .
XDH .. .

CTC as baud-rate generator for Channel 0
CTC as programmable timer
510 Data Input/Output of Channel 0
510 Status/Control for Channel D

XEH .. .
XFH .. .

V-20

The crystal and associated conditioning circuitry provides
an on-board stable clock capability for the counter timer
circuits.
The CTC's are used as programmable baud-rate generators
(Ports XOH, X8H, and XCH) as well as programmable timeout counters (Ports Xl H, X5H, X9H, and XCH). Each DCC80E channel has an individual programmable baud-rate
generator. The xl multiplier on the Z80-S10 must be used in
the synchronous mode. The x16, x32, or x64Z80-S10 clock
rate may be specified for the asynchronous mode. Table 1
indicates the standard baud rates available for both
operation modes.
STANDARD BAUD RATE
Table 1

Standard Baud Rates
Asynchronous

Synchronous

75
110
150
300
600
1200
2400
4800
9600
19,200
38.400

600
1200
2400
4800
9600
19,200
38.400

BINARY SYNCHRONOUS OPERATION
- One or two sync characters in separate registers
- Automatic sync character insertion
- CRC generation and checking

The MK3887 also provides modem control inputs and
outputs as well as daisy-chain priority interrupt logic. Eight
different interrupt vectors can be generated by the SIO in
response to various conditions affecting the data
communications channel transmission and reception. Ports
X6H, XAH, and XEH are data channels of Z80-S10 devices.
The CPU loads them with data to be sent and conversely
reads back data assembled in the receiver buffer. The Write
Registers (0-7) of the SIO are preset by a write operation on
ports X3H, X7H, XBH, and XFH to control proper operation.
The NRZI circuitry interlaces the SIO tothe channel headers
and allows the user to connect the NRZI data to the RS
232-C interface. The RS 232-C line drivers and receivers
not only provide the correct electrical signal levels, slew
rates, and impedances, but also allow the NRZI encoded
data to be configured as Data Terminal Equipment (DTE) or
Data Communications Equipment(DCE). The port configuration headers are then used to select the orientation of the
data communication interlace. This allows the user to
connect a DCC-80E module to a non-encoded modem.

The Mostek MK3887 (Z80-SI0) is the central element ofthe
DCC-80E module. This device is a multifunction component
designed to satisfy a wide variety of serial data
communications requirements in microcomputer systems.
Its basic role is that of a parallel-to-serial. serial-to-parallel
converter/controller, but within that role it is configured by
software progra mmi ng so that its function can be optimized
for a given serial data communications application. It has
the ability to compute circular redundancy checks making it
compatible with such protocols as SDLC. This devic~
provides two independent, full-duplex channels: A and B.
Each channel features the following:
ASYNCHRONOUS OPERATION
- 5, 6, 7, or 8 bits/character
- 1, 1 1/2, or 2 stop bits
- Even, odd, or no parity
- xl, x16, x32, and x64 clock modes
- Break generation and detection
- Parity, Overrun, and Framing Error Detection

HDLC OR IBM SDLC OPERATION
- Automatic Zero Insertion and Detection
- Automatic Flag Insertion
- Address Field Recognition
- I-Field Residue Handling
- Overrun protection for valid receive messages
- CRC generation and checking

Input and output to the board is provided via the SK2
connector. The configuration and pin out headers of each
channel are identical, and are diverted to the correct DB25
connector in the Matrix-80/SDS via a ribbon cable and
scrambler board which is sold as a separate prqduct (see
ordering information). The scrambler card installation and
pin outs are shown in Figures 3 and 5.
OPERATIONAL FEATURES
The channel interlace connects DCC-80E to data
terminal/communications equipment. It consists of four
basic parts:
1.
2.
3.
4.

Drivers and Receivers for RS-232-C
NRZI encoder
NRZI clock-recovery circuit
NRZI data-recovery circuit

Operation of DCC-80E can be tailored to any functional
environment by means of prewiring two jumper fields, per
channel, to any desired configuration.
WORD SIZE
Data: 5,6,7,8 bits
I/O addressing: 8-bits

V-21

1/0 ADDRESSING

SCRAMBLER CARD ORIENTATION
Figure 3

On-board fully programmable for 1 of 16 beginning port
addresses. Board may be addressed to anyone of sixteen
on-board port addresses.

MATRIX
BACK

PANEL

1/0 CAPACITY

SCRAMBLER

CARD
PLACEMENT

Serial: Four full-duplex serial ports, either synchronous or
asynchronous. Special control registers and circuitry to
permit implementation of SDLC, BiSync, Monosync, HDLC,
and other formats can be programmed. All synchronous
formats can be NRZI encoded.

MATRIX

INTERRUPTS

1/0 PANEL
REAR VIEW

FASTEN

ORIENTATION

Generates vectored interrupts to 32 different locations
corresponding to conditions within four SIO channels and
four CTC channels. Interrupt vector location programmable.
Daisy-chained priority interrupt maintained.

llli

WITHe
NO. 4-40
SCREWS

CARD DIMENSIONS
Figure 4

SYSTEM CLOCK
DeC-BOE

0

2.5MHz

± .05%

I

OPERATING TEMPERATURE

COMPONENT
SIDE

~1 -1 rI

POWER SUPPLY REQUIREMENTS

I
I
I

I

+12 volts ± 5% at 120 mA max.
-12 volts ± 5% at BO mA max.
+5 volts ± 5% at 1 .2 A max.

T

CARD DIMENSIONS
233.4 mm (9.19 in.) x 250 mm (9.B4 in.) x 1.6 mm (0.062 in.)
See Figure 4

V-22

DIMENSION

TYPICAL

MAXIMUM

L

Board Length

250.0 mm (9.84 in) 250.2 mm (9.850 in.)

W

Board Width

233.4 mm (9.19 in) 233.7 mm (9.200 in.)

H

Component Height -

13.0 mm (0.510 in)

T

Board Thickness

1.6 mm (0.062 in.)

1.7 mm (0.065 in)

D

Lead Length

2.3 mm (0.090 in.)

2.5 mm (0.100 in.)

DCC-BOE SCRAMBLER DIAGRAM
Figure 5

CTS-A
OSR-A

1a
1c

5l

(CB
cc

6

~===---~~~C~g~LX:~~A-------1:Bg~~r-------------====:s ~5

2a
2c
3a
3c

,>===--_~OT~R~-~A_ _--_-tC~0ii---------===:5

:~~~A

4a

AAI

4c

(gBA
<;=____~~O~A~TA~-~A~----1R~----------------~)

5a
5c

S:==
___ RXOATA-A
'-

20

~2'

iR~X~C~U~-~A!=====](O~O~)=============:~~~
~7
(BBI
AA

CHANNEL

'r

A

~~
9a <:
9c ~
10a
10c e
118
c:::
11c ('

<

12a c::
12c

e
13a

13c /c::'

CTS-B
OSR-B
OCO-B
TXCU-B
OTR-B
RTS-B
SCU-B
TXOATA-B
RXCU-B
RXOATA-B

(CQl
CC)
CF
DB
(COl
CA
(OAI
BA
(DO
(BBI

./ 5
~ 6
~ 8
~ 1
~ 2

/4
~ 2

;;

;;1

~

SK2

AB

17a <.
17c
18a c::

e
18c

<
19a'.(
19c

:

J13

~

(lCH"."
~~ I

iJ

;;
;; 317

~
AB.....
4-

V-23

CH. . ."
C

../

;;
;;
;;

GNO

/

iJ

~
~ 17
~ 3
1
AB
7

-"

'25 a e
25 Cc::
26 a e

!~
~~ I

1
7

J10

0

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NUMBER

OCC-80E

Four-channel data communication controller module with
operations manual and scrambler cable

MK78192

Scrambler

Converts SK2 Pin out to four 08-25 connectors mounted
on I/O panel of SOE-RMC6 or SOE-RMC6-50 or
MATRIX-80/S0S

MK78200

OCC-80E-OM

OCC-80E Operations Manual Only

MK79812

V-24

I!

UNITED
TECHNOLOGIES
MOSTEK

COMPUTER
PRODUCTS
DIVISION
FLP-80E
MK78146

FEATURES

FLP-80E BOARD PHOTO
Figure 1

o Soft-sector format compatible with IBM 3740 data entry
system format
o Capable of controlling up to four flexible disk drives per
subsystem
o Full disk initialization (Formatting)
o Full-sector (128 bytes) FIFO buffering for data
o Double buffering for control and status
o Automatic track-seek with verification
o Completely interruptable for real-time systems
o SDE BUS compatible

APPLICATIONS
o Flexible disk-drive interface for use with Mostek's
Software Development Board (OEM-80E) in a disk-based
Z80 Development System (MATRIX).
o Single or multiple flexible disk-drive controller/formatter
for disk-based OEM systems using the OEM-80E Single
Board Computer.

DESCRIPTION
The FLP-80E is an add-on flexible disk controller module
used to interface up to fourflexible disk drives to the Mostek
Software Development Board (OEM-80E).

The FLP-80E provides the necessary electronics to
accomplish track selection, head loading, data transfer,
error detection, flexible drive interface, status reporti ng and
format generation/recognition. The FLP-80E is designed to
operate with either Shugart SA-800 Single-Sided or SA850 Double-Sided Flexible Disk Drives. In addition to
functioning as an add-on card to the OEM-80E system, the
FLP-80E may be utilized directly in OEM applications to
control/format up to four flexible disk drives of either singleor dual-sided type in Z80 systems.

V-25

FLP-80E BLOCK DIAGRAM
Figure 2
DRIVE &

S~~~~E~:~: }

WRTGATE DIRECTION STEP

DRIVE & SIDE
SELECT CIRCUITS

HEAD LOAD
DELAY

. OSCILLATOR

V

CONTROL INTERRUPT
LINES

ADDRESS
BUS

+12V +12V +5V-=

DATA
BUS

AVAILABLE SOFTWARE

POWER SUPPLY REQUIREMENTS (Typical)

Software for the FLP-80E disk controller is the Mostek Disk
Operating System (FLP-80DOS). A user can easily design
his own OEM software package around 20 powerful disk
operating system commands permitting complex record
insertion, deletion, and position manipulation. Other
software includes application packages such as an
advanced monitor and debugger, disk-based Text Editor,
Z80 Assembler, Relocating Linking Loader, Peripheral
Interchange Program, and a channelized I/O system for
each peripheral interface. These programs provide state-ofthe-art software for developing Z80 programs as well as
establishing a firm basis for OEM products. Further
information is provided in the FLP-80DOS Data Sheet,
MK78556.

+12V ± 5% at 0.OO6A
+5V ± 5% at 1 .1 A
-12V ± 5% at 0.03A
INTERFACE LEVELS
TIL Compatible
BOARD SIZE
250mm x 233.4mm x 18mm

BOTTOM CONNECTOR
OPERATING TEMPERATURE RANGE
Dual 64-pin Eurocard Connector, DIN 41612 form D; A and
C pinned.

V-26

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NO.

FLP-BOE

FLP-BOE Disk Controller Board with Operations Manual,
FLP-BODOS bootstrap PROMs and diskette with FLP-BODOS
Operations Manual.

MK7Bl12

FLP-BODOS

FLP-BODOS bootstrap PROMs and diskette

MK7B142

FLP-BOE

FLP-BOE Disk Controller Board with Operations Manual.
(No Software)

MK7B146

FLP-BOE Operations Manual. Detailed description of use and
operation of FLP-BOE.

MK7B561

Disk Operating System data sheet.

MK7B556

LP-BODOS Data Sheet

FLP-BODOS Operations Manual. Detailed description of the use MK7B557
and operation of FLP-BODOS.

V-27

V-28

I!I

UNITED
TECHNOLOGIES

COMPUTER
PRODUCTS
DIVISION

MOSTEK

RAM-80E
MK78109, MK78110, MK78212

FEATURES
o Memory Capacity
• RAM-80AE - 16,384 (16K) bytes using MK4027
RAM
• RAM-80BE - 16,384 (16K) bytes expandable to
65,536 (65K) bytes using MK4116
RAM
• RAM-80BE under page-mode operation - up to one
megabyte of memory

RAM-80E BOARD PHOTO
Figure 1

o 1/0 Capacity (RAM-80BE only)
Four 8-bit ports with handshake lines

DESCRIPTION
The RAM-80E is designed to provide RAM expansion
capability for the Z80-based OEM-8OE microcomputer. For
user flexibility, it is offered in two basic configurations
designated RAM-80AE and RAM-80BE.
The RAM-80AE is the basic 16K-byte RAM board for users
requiring the most economical means for adding RAM to an
OEM-80E microcomputer. It is designed using the highperformance MK4027-4, 4096 x 1-bit dynamic RAM, and
includes address strapping options for positioning the
decoded memory space to start on any 4K incremental
address boundary.
The RAM-80BE is a combination memory and 1/0
expansion board. The memory may be configured to have a
memory capacity of 16K, 32K, 48K, or 65K bytes of RAM.
This on-board memory expandability is made possible by
population options of either 8, 16, 24, or 32 MK4116-4
(16,384 x 1 MOS dynamic RAM) memories. The RAM-

80BE provides strapping options for positioning the decoded
memory space to start on any 16K address boundary. In
addition to the add-on memory, the RAM-80BE provides
four 8-bit I/O ports from the two on-board MK3881 Z80 PIO
circuits. Each 1/0 port is fully TTL-buffered and has two
handshake lines per 1/0 port. The RAM-SOBE also includes
logic for ".page-Mode Operation" which permits up to 1
megabyte of memory (sixteen 65K x S RAM-SOBEs) to be
used in a single OEM-SOE system.
A complete set of documentation for each RAM-SOE board
is available to ensure easy utilization.

V-29

RAM.80AE BLOCK DIAGRAM
Figure 2

4

MEMORY ARRAY
16Kx 8
32 MK4027s

-5V

BUS

RAM·80BE BLOCK DIAGRAM
Figure 3

DATA
BUS

SK2 64-PIN - - - - - - - - - - - ,

MEMORY ARRAY
16K x8
8 MK4116s
32K x 8 16 MK4116s
48Kx8 24MK4116s
65K x 8 32 MK4116s

3

V-30

MEMORY ACCESS TIME

POWER SUPPLY REQUIREMENTS

345ns (maximum)

Voltage

RAM-SOAE

RAM-SOBE

+12V±5%

200mAtyp.
575mA max.

200mAtyp.
575mAmax.

-12V±5%

25mAtyp.
30mA max.

25mAtyp.
30mA max.

+5V±5%

370mAtyp.
550mA max.

1.1A typo
1.5A max.

MEMORY CYCLE TIME
450ns (minimum)

BOARD SIZE
250 mm x 233.4 mm x 18 mm

OPERATING TEMPERATURE
CONNECTOR
O°C to 50°C
Dual 64-pin Eurocard Connector

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NO.

RAM-80AE

16,384-byte RAM board with 32-MK4027s

MK78109

RAM-80BE

Expandable 16,384-byte RAM board with 8-MK4116s, sockets MK78110
for additional MK4116s, 2-MK3881 l80 PIOs, plus page-mode
capability.
RAM-80BE Operations Manual. Complete description of the
electrical specifications, timing, and circuit operation of the
RAM-80BE. Also includes a detailed schematic diagram,
assembly drawing and parts list.

MK78555

RAM-80AE Operations Manual. Complete description of the
electrical specifications, timing, and circuit operation of the
RAM-80AE. Also includes a detailed schematic diagram,
assembly drawing, and parts list.

MK78574

V-31

V-32

IJ

UNITED

COMPUTER
PRODUCTS
DIVISION

TECHNOLOGIES
t.'OSTEK

VDI-80E
MK78198, MK78033, MK78199, MK78035
FEATURES

SERIAL VERSION PHOTO
Figure 1

o 24-line x 80-character display

o

5 x 8 dot matrix

o

Upper and lower case display

o

96-character ASCII plus 32 special characters

o

Programmable TABs

o

Programmable Inverse Video

o

Bidirectional Scrolling

o

48-character FIFO

o

Auto repeat on keyboard interface

o

Direct and relative cursor addressing and cursor address
readback

o

Direct speaker drive for bell tone

o

PARALLEL VERSION PHOTO
Figure 2

Ability to read character. line. or screen information
. stored in screen RAM

o

Two versions
Serial: 110-9600 BAUD
Parallel: 3200 CharacterlSec

o

50/60 Hz versions

DESCRIPTION
The Video.Display Interface (VDI) board is a microprocessorbased video terminal controller system on a Double
Eurocard format printed circuit board. The VDI serves as the
interface between an ASCII encoded keyboard and an EIA
standard video monitor to a microcomputer development
system.
The display format is 24 lines of 80 characters. Each
character is formed by a 5 x 8 dot matrix in a 6 x 9 cell (60 Hz
version or a 6 x 11 cell (50 Hz version). See Figure 4.
Character generation is accomplished by the provided
MK34073 character generator. If other special characters
are desired. the user may generate a custom character set

in either a 2758 or 2716 EPROM and use it in place of the
MK34073.
The VDI board will allow lower case characters to be
generated from an upper case keyboard.

™ SDE Series is a trademark of Mostek Corporation

V-33

BLOCK DIAGRAM
Figure 3

""""l,ATA

PORT

4

HORIZCURSOIl

ADOR

COMP
SY~C

COMPOSITE
VIOfO

. -- PARALLEL VERSION

-

_ _ _ _ _ .1

BLOCK DIAGRAM DISCUSSION
The serial version VOl allows RS232-C or 20 mA Current
Loop operation via a Universal Asynchronous Receiver
Transmitter (UART) device. User strappil)g options include
BAUO rate (11 0-9600), number of stop bits, number of bits
per character, and even/odd parity.

The FS-PSU not only provides 1K bytes of ROM storage for
the VOl driver program, but has two I/O ports for vertical
cursor and scroll addressing.

The FS-PIOinierrupts the FS-CPU when keyboard data is
ready for transfer over the data bus.

The Master timing block consists of a hybrid crystal
oscillator module and a series of cciunters which generate
all necessary horizontal and vertical sync and blanking
pulses, plus a 12-bit screen address. Since only 11
addresses are required for the 2K-byte memory, the 12-bit
address must be compacted to 11 bits by the Address
Modifier. The horizontal and vertical screen memory
address are constantly being compared to the current
cursor address to generate proper read/write timing.
.

The FS-CPU controls the flow of data according to
instructions stored in the FS~PSU.Keyboard data received
from the FS-PIO is sent to the system via the UART or
zao-Plo. Oata received by the system is proeessed by the
CPU and characters are written to screen memory via port
1. Likewise, screen memory data can be sent back to the
system via port 1. The CPU also updates horizontal and
vertical cursor addresses. The 4S-character FIFO is
implemented using 4S bytes of the 64-byte scratchpad
RAM within the CPU.

The video monitor is refreshed with the contents of the
screen memory at a rate of 50/60 Hz. On power-up, screen
memory is first cleared (loaded with spaces), then loaded
with character data from the system. The 7 -bit ASCII
character from memory is latched and applied to the
character generator as a character address. The row
address is supplied by the mastertimer. The character dots
are then loaded into the shift register and output serii;llly to
the composite video driver along with sync, blanking, and
inverse video control signals. •
.

The parallel version VOl uses the Zoo-PIO for fast data
transfer with a Z SO-CPU. The VOl port addressing scheme
permits the use of up to 16 VOl's for use lII!ith one CPU.

V-34

MK34073 CHARACTER GENERATOR SYMBOLS
Figure 4

SPECIFICATIONS

TTL AUDIO:

VOL = 0.5 V max @ IOL = 20 rnA
VOH = 2.7 V min @ IOH = -1.0 rnA

SOE BUS INTERFACE
Inputs: One 74LS Load Max.
Outputs:

SPEAKER
OUTPUT:

A high level output is provided for
driving a 50 ohm speaker directly.
EIA RS-170 Compatible (75 Ohm. 1 V
p-p)

BAUD RATE:

VOL = 0.4 V max @ IOL = 12 mA
VOH = 2.4 V min @ IOH = -3 mA

VIDEO OUTPUT:

DATA BUS:

VOL = 0.5 V max @ IOL = 24 mA
VOH = 2.0 V min @ IOH = -15 mA

OPERATING TEMPERATURE

INTB & DINB:

(Open collector outputs)
VOL = 0.4 V max @ IOL = 16 mA
VOL = 0.7 V max @ IOL = 40 mA
IOH = 250 p.A max @ VOH = 30 V

KBDACK:

VOL = 0.5 V max @ IOL = 8 mA
VOH = 2.7 V min @ IOH = -0.4 mA

Oto50° C
POWER SUPPLY REQUIREMENTS
Serial Version:

Parallel Version:

V-35

+5 V ± 5% @ 1.8 A max
+12 V ± 5% @ 80 mA max
-12 V ± 5%@25 mA max
+5 V ± 5% @ 1.9 A max
+12 V ± 5% @ 50 rnA max

BOARD DIMENSIONS

CONNECTORS

o

I

COMPONENT
SIDE

SDE BUS

1~T~
I
I

L-r---I-T--T-'

FUNCTION

I
I

Dimension

Typical

L

Board Length

250.0 mOm (9.84 in) 250.2 mm (9.850 in)

W

Board Width

233.4 mm (9.19 in) 233.7 mm (9.200 in)

H

Component Height

--

13.0 mm (0.510 in)

T

Board Thickness

1.6 mm (0.062 in)

1.7 mm (0.065 in)

D

Lead Length

2.3 mm (0.090 in)

2.5 mm (0.100 in)

DESCRIPTION

MATING
CONNECTOR

Dual 64-pin
Wire Wrap Tail:
Eurocard
Winchester
Connector,
#96s-6033-0522-1
DIN 41612 form 0; ELCO #8257-096A and C pinned
648-124
Solder Tail:
Winchester
#96s-6033-0522-3
ELCO #8257-096649-124

Maximum

ORDERING INFORMATION

DESIGNATOR

DESCRIPTION

PART NO.

SVDI-80E-60

Serial version Video Display Interface board (60 Hz
operation) with Operations Manual.

MK78198

SVDI-80E-50

Serial version Video Display Inteface board (50 Hz
operation) with Operations Manual.

MK78033

PVDI-80E-60

Parallel version Video Display Interface board (60 Hz
operation) with Operations Manual.

MK78199

PVDI-80E-50

Parallel version Video Display Interface board (50 Hz
operation) with Operations Manual.

MK78035

VDI-80E

Operations Manual Only (for all versions of
VDI-80E boards).

MK79876

V-36

1983 COMPUTER PRODUCTS DATA BOOK

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~ TECHNOLOGIES
UNITED

COMPUTER
PRODUCTS
DIVISION

MOSTEK

SDE SERIES ACCESSORIES
SDE-ACC
MK78152, MK79062, MK79063,
MK79090, MK79088, MK79089, MK78187, MK78193
INTRODUCTION

SDE-ACC
Figure 1

The following items are available as accessories to support
design, development. and production of products designed
around the Mostek SDE Series Z80* microcomputer
modules:
SDE-WW1
SDE-EXT
SDE-CRT-C
SDE-CPTR-C
SDE-PPG-C
SDE-DFE-C
SDE-2DFE-C
SLD-KIT
RMDC

ncp

Wire-wrap board with bussed power
and ground
Extender board
Matrix to CRT Cable
Matrix to Centronics Printer
Matrix to PROM Programmer
Matrix to RMDFSS Cable
Matrix to two RMDFSSs
Rack Mount Slide-Kit
Rack Mount Dust Cover
Table Top Conversion Package

WIRE WRAP BOARD
TheSDE-WW1 (MK79063) isa wire wrap board with power
and ground lines on the board to facilitate fabrication of
circuits using wire-wrap sockets. Three rows of platedthrough holes (spaces on 0.100 inch centers) are provided
on the top edge of the board for mounting standard
connectors. The spacing of the holes throughout the board
are also on 0.1 00 inch centers to accommodate alilC Dual
in-line Packages, discrete components, and 0.025 inch
square posts.

system board. This allows a technician the space required to
use test probes or monitor signals at the component level on
the board. The board is of a mUlti-layer design (an insulated
ground plane sandwiched between the upper and lower
signal trace etches of the board). This design decreases the
amount of cross-talk between signal-runs. Additionally
three light emitting diodes (LEOs) are mounted on the SDEEXT board and are wired to the power signal etch lines. A
technician can tell at a glance that all three power sources
(+5 V, +12 V, and -12 V) are present.

EXTENDER BOARD
The SDE-EXT (MK79062) is a board that extends the bus
signals out from the enclosure to suspected malfunctioning

VI-1

CABLES
The SOE-CRT -C (MK78152) is a cable designed to interface
the Matrix with a Video terminal (CRT). Both ends are a
25-pin Ootype male connector. See Figure 2,

SDE-CRT-C MK78152
Figure 2
CRT

6FT

MATRIX-80/S0S
MATRIX-80/S0T

ADDS
HAZELTINE

The SOE-CPTR-C (MK79089) is a cable designed to
interface the Matrix with the Mostek printer (Centronics
model 702). See Figure 3.

SDE-CPTR-C MK79089
Figure 3
CINCH
SOLDER
RIBBON
MATRIX-SO/SOS
MATRIX-80/S0T

I

25-PIN
O-TYPE
MALE

6FT

I

I

36,PIN
O-TYPE
MALE

I

PRINTER
CENTRONICS 702

The SOE-PPG-C (MK79090) is a cable designed to interface
the Matrix-80/S0S with the PROM Programmer PPG8/16. See Figure 4.

SDE-PPG-C MK79090
Figure 4

MATRIX-SO/SOS

I

25-PIN
O-TYPE
MALE

I
I

20 INCHES

I

J
I

25-PIN
O-TYPE
FEMALE

I

50-PIN
O-TYPE
MALE

I

I

PPG-S/16

The SOE-OFE-C (MK79088) cable is designed to interface
the Matrix-80/S0S CPU enclosure to the Floppy-disk drive
enclosure. Both ends of the cable are 50-pin, Ootype, Male
connectors. See Figure 5.

SDE-DFE-C MK79088
Figure 5

MATRIX-SO/SOS
MATRIX-SO/SOT
MO-RMC12

I

50-PIN
O-TYPE
MALE

I

2V2 FT

I

J

VI-2

j

RMOFSS

The SOE-20FE-C cable is designed to interface the Matrix80/S0S CPU enclosure to two floppy-disk drive enclosures.
Both ends of the cable are 50-pi n, O-type, male connectors
with an additional connector (50-pin, O-type, male) in
between the ends spaced as shown in Figure 6.

SDE-2DFE-C
Figure 6
1% FT

1FT

MATRIX-BO/SOS
MO-RMC12

2 RMOFSSs

SLIDE KIT

which are being converted to a rack-mounted configuration.
The cover snaps-on in the same manner as does the
structural-foam lid, and is dimensioned to fit as a lid while in
the 19-inch rack, whereas the structural foam lid is not. The
top is not used for rack mounted enclosures when they are
stacked (butted up) one on top of each other. However,
when there is no enclosure above to prevent dust from
entering the unit, a top is recommended.

The SLO-KIT (MK78192) is designed specifically for
mounting Mostek's rack-mountable enclosures in a
standard E.IA 19-inch rack. The kit contains two slides
with mounting hardware. The slides are installed
underneath the enclosure. The SLO- KIT will mount the
following enclosures:
* Matrix-80/S0S
Matrix-80/S0T
SOE-RMC6
RMOFSS
RMOFSS-50
MO-RMC12
MO-RMC12-50

(MK78188, MK78189)
(MK78197)
(MK78182-1, MK78182-2)
(MK78183)
(MK78185)
(MK77966)
(MK77975)

TABLE TOP CONVERSION PACKAGE
The TTCP(MK78187) is a kit containing two structural-foam
side skins, lid, and mounting hardware. The purpose of this
kit is to be able to configure a rack mounted system to a table
top configuration. One TTCP kit is required for each rack
mounted enclosure. This kit is designed for the following
enclosures:

*Note: Two slide kits are required.

RACK MOUNT TOP
The Top is a black, solid metal plate which serves as a top.
This metal lid is required for all table top configured systems

VI-3

SOE-RMC6
RMOFSS
MO-RMC12
MO-RMC12-50

MK78182-1, MK78182-2
MK78183, MK78185
MK77966
MK77975

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NO.

SDE-WWl

Wire Wrap Board

MK79063

SDE-EXT

Extender Board

MK79062

SDE-CRT-C

Matrix to CRT Cable (Male)

MK78152

SDE-CPTR-C

Matrix to Centronics Printer

MK79089

SDE-PPG-C

Matrix to PROM Programmer

MK79090

SDE-DFE-C

Matrix to RMDFSS

MK79088

SDE-2DFE-C

Matrix to two RMDFSSs

:

SLD-KIT

MK78193

. Slide Kit

RMDC

Rack Mount Top

TTCP

Table Top Conversion Package

VI-4

MK78187

I!J

UNITED
TECHNOLOGIES
MOSTEK

COMPUTER
PRODUCTS
DIVISION
SDE-RMC6
MK78182-1, MK78182-2

FEATURES

SD-RMC6 PHOTO

o Standard 19-inch rack-mountable chassis; 7 -inch panel
height

o

Removable structural foam front panel for internal
access

o

Front panel RESET switch and POWER-ON indicator

o

Six-slot card cage

o

Cards mounted horizonta lIy for ease of cooling and cable
routing

o

Self-contained power supply and 115 CFM fan

o

100/115/230 Volt 50/60 Hz operation

SD-RMC6 Interior View

DESCRIPTION

Figure 2

The Mostek SO Series rack-mount system (SOE-RMC6)
offers a solution to rack mounting the line of SOE Series
Microcomputer modules. The system features a selfcontained power supply designed to work on voltages and
frequencies available world-wide. All components are
easily removed from front or top for i. nproved maintenance.
An attractive structural foam front panel is provided with
system RESET switch and POWER-ON indicator. The front
panel is designed with quick-release ball studs so that it can
be quickly removed for access to internal components. The
cards are mounted in a horizontal plane with I/O cabling at
the rear of the card cage. The back panel has an I/O panel
pre-punched for twelve 25-pin "0" type connectors, one
50-pin "0" connector, and one BNC connector for
versatility. AC components on the back panel were selected
to meet UL and VOE requirements and include: On/Off
switch, voltage selection switch, fuse holder (3AG or 5 x 20
mm), and AC input receptacle/line filter.

•
VI-5

SD~RMC6 Side View

SD-RMC6 Rear View

INPUT POWER

CARD CAGE

100/1151230 volts AC

± 10% 50/60Hz

Six slot for SD/E series module (250mm x 233.4mm) (9.19
x 9.84 in). Wire-wrap tail connector provided for SK2 I/O
connectors. All SK1 connectors wired one-to-one. No PC
modules supplied.

DC POWER AVAILABLE
+5 VDC at 12A max.
+ 12 VDC at 1.7A max.
-12 VDC at 1.7A max.

FUSING
UneVoltage

MK78182-1

MK78182-2

110/115V

3 Amp 3AG*

3Amp5x20 mm

230 V

1.5 Amp 3AG

1.5Amp
5 x20mm*

LOAD REGULATION

± .05% for a 50% load change
OUTPUT RIPPLE

*Configuration as shipped

3.0 mV PK-PK max.

LINE CORD SUPPLIED

TRANSIENT RESPONSE

MK78182-1
Similar to Belden model
17205B

30 microseconds for a 50% load change

MK78182-2
Similar to Feller model
1100

SHORT CIRCUIT AND OVERLOAD PROTECTION

FRONT PANEL CONTROLS

Automatic current limit/foldback

RESET switch
POWER ON Indicator

OVERVOLTAGE PROTECTION
REAR PANEL CONTROLS
+5 Volt output, set to 6.2

± 0.4 volts
AC Power On/Off
AC fuse holder
AC line receptacle/filter
AC line voltage selector

STABILITY

± 0.3% for 24 hours after warmup
THERMAL PROTECTION

WEIGHT

Bi-metal thermostat or primary AC line set to cut Ol:lt at
180°F (82°C)
VI-6

25 Ibs (11.3 kg)

CHASSIS

DIMENSIONS

a) 19" rack-mountable using the two rails supplied.
b) Slide mounting available with optional slide mounting
bit and requires two inches of panel space below the
unit.

Height: 7.0 in. (17.8 cm) panel space
7.3 in. (18.5 cm) overall, including feet
Width: 19.0 in. (48.3 cm) at front panel
17.5 in. (44.5 cm) behind front panel

OPERATING TEMPERATURE RANGE
Depth: 21.1 in. (53.6 cm) with all protrusions
20.0 in. (50.8 cm) without foam front

HUMIDITY
Up to 90% relative, non-condensing

ORDERING INFORMATION

DESIGNATOR

DESCRIPTION

PART NO.

SDE-RMC6

Rack-mounted CPU subsystem with SDIE series six-slot
card cage with U.S. line cord and fuse. 100/115/230 Volts
50/60 Hz AC operation front panel, rails for rack mounting
and operation manual included.

MK78182-1

SDE-RMC6-50

Same as above except with 5 x 20 mm fuse and European
line cord.

MK78182-2

SDE-RMC6 to CRT

CRT Interface Cable Only

MK78152

SDE-RMC6 Operations Manual Only

MK79783

SLD Kit

Slide Kit

MK78193

TTCP

Table Top Conversion Package

MK78187

The following Mostek modules are compatible with the above CPU subsystem
OEM-80E
RAM-80E
FLP-80E
VDI
AlD-80E

CPU Module Data Sheet
RAM Expander Data Sheet
Floppy Disk Interface Data Sheet
Video Display Interface Data Sheet
AlD-DI A Interface Data Sheet

VI-7

MK78550
MK78590
MK78572
MK78591
MK79709

VI-8

1983 COMPUTER PRODUCTS DATA BOOK
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I!I

UNITED
TECHNOLOGIES
MOSTEK

COMPUTER
PRODUCTS
DIVISION
RADIUSTM
REMOTE DEVELOPMENT STATION

FEATURES

RADIUS
Figure 1

D Microcomputer development with host computer
• Software development on the host
• Download to RADIUS
• Hardware debug and software integration on RADIUS
D Utilizes standard Mostek SDE series AIM modules

D Host software available
• Preconfigured for selected hosts
• Reconfigurable for other hosts
D Upload/download performed with error tolerant protocol
D Emulation possible while disconnected from the host
D Serial I/O Baud rate up to 9600
D Supports optional
programmer

local

line

printer

and

PROM

D Self-diagnostic test

INTRODUCTION
Mostek RADIUS - Remote Access Development and
Integration tLcomputer System - is a state-of-the-art
microcomputer development system, designed specifically
to be used in a host computer environment. RADIUS
provides software development capability via the host
computer and hardware development and software
integration using the advanced in-circuit-emulation capability of Mostek AIM modules.

In Local Mode, the user can:
• Set optional Baud rates and special RADIUS control
characters
• Perform self diagnostics on RADIUS
In Utility Mode, the user can:

RADIUS is installed between the user's CRT terminal and
the host computer via an ASCII RS-232 serial interface. See
Figure 2. It can be operated in any of three modes:
Transparent, Local or Utility.

• Run the host components of the RADIUS Utility
Packages (i.e. AIM-Z80BE, AIM-7XE, Line Printer
Utility, PROM Programmer Utility, etc.).
• Perform hardware debug and software integration.

In Transparent Mode, the user can:

RADIUS has no mass storage. Instead it uses the mass
storage capabilities of the host. Once the user's target
program is downloaded, the user has the option of
disconnecting the RADIUS from the host. This allows the
user to save connect time and long distance charges.

• Perform any function that can be performed on the
host computer. RADIUS becomes completely transparent to the user.

VII-1

RADIUS SYSTEft"S CONFIGURATION
f,igu~'2

HOST

PROM PROGRAMMER
(OPTIONAL) .'

CRT

RADIUS

TARGET
BOARD

be

RADIUS can
configured in a single-user environment or
in a multi-user environment. in which several RADIUS
units areconne~d to an appropriate host and operated
simultaneously. "performing entirely separate jobs. This
configuration supports the development of multiple
microprocessor/microcomputer systems. See Figure 3.

compartment on the right. The processing compartment
can house up to five boards: a RADIUS processor board.
two-card AIM module set. and two slots for· future
expansion.
The RADIUS processor board contains:

• zao CPU

DEVELOPMENT SYSTEM

RADIUS is a cost effective microcomputer development
tool. It consists of an integrated cabinet. power supply. I/O
panel. and a Z80 based processor module with four serial
I/O ports.
RADIUS is supplied with a host communications sOftware
package configured for several popular mini/microcomputer systems. (See ordering information.) A user
rehostable version is available for other host computers.
Additional, preconfigured versions of the RADIUS host
software will be pr()vided in the future.
RADIUS HARDWARE FEATURES

RADIUS consists of a structural foam cabinet. a Z80 based
RADIUS processor board. and a power supply board, The
user can addAIM-68000.AIM-Z80BE. or AIM-7XE modules
to RADIUS to perform the full range of real time in-circuit
emulation needed for hardware development and software
integration. Future AIM products will be completely
supported on RADIUS.
The cabinet is divided into two compartments: the power
supply compartment on the left and the processing
VII-2

• 64 Kbyte internal systems memory
• Four SID ports;
- one dedicated to user terminal. one to the host
" computer. and two for optional printer and PROM
programmer
.
'
- RADIUS supports 11 standard Baud rates from 50 to
9600 Baud
RADIUS SOFTWARE FEATURES

• Local mode to set options on RADIl)S and to perform
. local diagnostics.' .
.
• Most link parameters set at host cOnfiguration time
• 'Full AIM command set available
• AIM packages can run command files from th~ host
• AIM packages can log all terminal output to the host
• Progress of download/upload indicated on CRT
• Protocol re-transmits messages upon line error
• Self-expl,:matory error messages
• Translators to convert INTELHEX. TEKHEX. Motbrola SRecord. and F8HEX object formats to Mostek HEX
• Local PROM programming (optional)
• Local printing (optional)
• Self diagnostic test

RADIUS local mode provides the following commands:

SPECIFICATIONS

•
•
•
•
•
•

The power supply board has single phase AC input at 47 Hz
to 63 Hz for the following voltage ranges:
• 95 Vto 132 V
• 190 V to 264 V

HELP
PORT
MEMORY
OPTIONS
DIAGNOSE
QUIT

The approximate dimensions are:
• Width: 9.2"
• Height: 10.8"
• Depth: 12.6"

RADIUS INSTALLATION IN A MULTI-USER ENVIRONMENT
Figure 3

CRT

CRT

CRT

HARDWARE/SOFTWARE
DEVELOPMENT STATIONS

PROM
PROGRAMMER
(OPTIONAL)
HARDWARE/SOFlWARE

DEVELOPMENT STATION
VIA MODEM

ORDERING INFORMATION
For detailed ordering information refer to the Development
System Products Ordering Guide.

VII-3

VII-4

I)

UNITED

COMPUTER
PRODUCTS
DIVISION

TECHNOLOGIES
MOSTEK

AIM-6BOOO
FEATURES
o In-circuit emulation for the MK68000 processor

AIM-68000
Figure 1

o Real-time execution to 10 MHz with no wait states
o Direct interface to Mostek's RADIUS Station and
MATRIX Development System
o 16K words of Emulation Memory mappable in 2K word
blocks on 2K address boundaries; Illegal "Write-toMemory" Detection provided
o "Stand-alone" Mode allows Software Debug with no
Target System
o Flexible breakpoints: Hardware, Software, and Timer
o Single Step execution with Break on Register Contents
o Instruction trace memory for
Execution History ("Soft Trace")

tracing

Instruction

o Exception Handler Routines provided
o Symbolic Addressing Capabilities
o Batch Mode and User Activity Logging provided
o Extensive HELP facility
o Disassembly of Instructions in memory
o English oriented Command Structure

Single Step capability allows the user to execute
instructions one at a time and examine registers to see the
exact effect of each instruction. The Single Step function
operates in either ROM or RAM.
Upto 16K words of Emulation RAM can be used to emulate
user Target ROM or RAM. This memory may also be used
while the emulator operates in Stand-alone mode, allowing
software development prior to hardware availability.

GENERAL DESCRIPTION
AIM-68000 is an advanced development tool which
provides debug assistance for both hardware and software
via in-circuit emulation of the MK68000 microprocessor.
All CPU signals are active during user program execution.
No memory wait states are required.
The user friendly command structure consists of Englishlike commands. A structured HELP facility and the ability to
enter keywords allow easy system familiarization. As the
user becomes more familiar with the system, commands
may be abbreviated. A BATCH facility with PAUSE allows a
list of commands on the host to be executed. This feature is
useful for test environments and lengthy program setups.

AIM-68000 breakpoint conditions allow 8 software
breakpoints, one- hardware breakpoint, and one timer
breakpoint to be set.
The Hardware Breakpoint detect circuitry allows user
program execution to proceed until a specified bus condition
OCcurs. The Breakpoint consists of address, data, function
codes, and an external "ARM" bit which allows the
Hardware Breakpoint to be slaved to an external TTL input.
Any of the Breakpoint condition bits may be designated as a
"don't care" bit by setting the "match bits" option. An Event
Count and Timer Breakpoint further enhance the Hardware
Breakpoint facility.
A software Trace Buffer allows the storage of register

VII-5

AIM68000 BLOCK DIAGRAM
Figure 2

contents and processor status during single step or Invisible
Trace. Invisible Trace allows single stepping to proceed with
no information displayed at the user's console. A powerful
additional feature of the software trace is the Register
Content Breakpoint Function which forces stepping to stop
upon the occurrence of a specified set of register conditions.
The Trace Buffer may be Reviewed after stepping
terminates.

generator, the DTACK timeout hardware, and a number of
buffers and associated steering logic.

USING AIM-68000
When AIM-68000 is attached to the user Target System, it
effectively becomes part of the user's system. It is important
to understand the implications of this addition. The
considerations may be grouped into four areas. They are:

BLOCK DIAGRAM DESCRIPTION
The AIM-68000 emulator consists oftwo boards, Control 1,
Control 2, and a Personality Module. The two control boards
are attached to the personality module which contains the
MK68000 CPU and plugs into the Target system 'CPU
socket directly. Switch options in the personality module
allow the user to operate AIM-68000 in a Stand-alone
mode.
Control Board 1 contains the Emulation Memory, the
Emulation Memory Map, Control RAM, the Control RAM
Map, and the two port memory access circuitry. In addition,
the Write Violation Detect circuitry is located pn Control
Board 1.
Control Board 2 contains circuitry for the Hardware
Breakpoint, Timer Breakpoint, the Exception Vector Map,
and Keyboard Escape.
The Personality Module contains an on board 10 MHz clock

1. System (i.e., Emulation) Memory
2. Control Memory
3. Exception Vector Memory
4. MK68000 CPU Control Signals

SYSTEM MEMORY
System Memory may be mapped into or out of the user's
memory space via the MAP command. If a block of memory
is mapped as System resident, the memory will appear in
the user's memory map. AIM-68000 provides a DTACK
signal to the MK68000 CPU for those areas which are
mapped as System and the memory cycles terminate with
no wait states.

CONTROL MEMORY
Control Memory: AIM-68000requires 1K words of the
user's memory space. The default location for this memory
is 24000H; however, it may be relocated via the INIT

VIt-6

command to reside anywhere in the MK68000 memory
space. Control Memory is a two-port memory which may be
accessed both by the MK68000 and the development
system's Z80 CPU. The user software must not access the
1K word area of Control Memory.
The MK68000 executes in control memory whenever user
software is not being executed. Execution in control
memory may include the insertion of several wait states in a
memory cycle; however, all user software is executed in
real time with no wait states up to 10 MHz.

EXCEPTION VECTOR MEMORY
Exception Vector Memory is located at addresses O-OFFH.
Each exception Vector may be mapped as System or Target
resident. If a vector is mapped as System Resident, AIM68000 will provide the DTACK signal for the MK68000
CPU.
The RESET, NMI. and ILLEGAL INSTRUCTION vectors are
special cases and are used to perform emulator functions.
They operate as follows:
RESET: Is mapped as System Resident upon Initialization
(lNIT Command). Immediately after initialization, this vector
is mapped as Target resident. It may not be remapped as
system resident.
NMI: NMI is a shared Level 7 Autovector interrupt used by
both AIM-68ooo and the user. It may be mapped as either
System or Target resident. If it is mapped as System
resident, the response to a Level 7 Autovector Interrupt will
be a message displayed on the user console. The user NMI
vector is read from the Target system prior to execution. The
user must not alter the Level 7 Autovector during program
execution.
ILLEGAL INSTRUCTION: Illegal Instruction is the vector
used by AIM-68ooo to generate the Software Breakpoint. It

may be mapped as either System or Target resident. The
user Illegal Instruction vector is read from the target system
prior to the start ot execution. The user must not alter the
vector during program execution.
Since the actual exception vectors fetched by the MK68000
are not always the vectors in Target memory, the user
should not attempt to run memory verification programs on
the Exception Vector Table.

MK68000 CPU CONTROL SIGNALS
All address lines, address strobe, and data strobes are
presented to the Target System at the CPU socket for all
memory accesses, whether they are for Target or AIM68000 system resident memory. Data i.s presented on the
data lines only during memory write cycles. MK68000
signal delay information is provided in the Specifications
section.

AIM-68000 SOFTWARE
AIM68K is the software which operates the AIM-68000
emulator in either the RADIUS or MATRIX development
system. In the RADIUS environment, Target software
programs are generated and assembled on the host
computer. The hex object module is downloaded into AIM68000 and/or Target memory via the GET command.
The AIM68K software for use with the RADIUS station is
available on several different formats for a variety of host
computers. The software will be supplied on a flexible
diskette for use in the MATRIX Development System.

COMMAND SUMMARY
The user commands for AIM68K are summarized in Table
1. Each command may also be entered in an abbreviated
form. Keywords are allowed in the command syntax to
promote rapid user familiarization.

VII-7

AIM-68000 USER COMMANDS
Table 1

COMMAND
ACCESS
BASE
BATCH
BREAK

CLEAR
COpy
DELETE
DISASSEMBLE
DUMP
EXECUTE
FILL
GET
GO
HELP
HEXADECIMAL
INITIALIZE
LOCATE
LOG
MAP
MEMORY
QUIT
RAMTEST
REGISTER
REVIEW
SELECT
SET
SYMBOL
STEP
TRANSPARENT
VERIFY

DESCRIPTION
Define memory accesses as word or byte
Set or Display Memory Offset
Submit a Batctl File
Set or Display a Breakpoint
Hardware Breakpoint
Event Count for Hardware Breakpoint
Trigger for Hardware Breakpoint
Mask for Hardware Breakpoint
Software Breakpoint (RAM only)
Timer Breakpoint
Register Contents ~reakpoint (for use with STEP or GO
command)
Clear one or more Breakpoints
Copy a block of memory to another area
Delete a symbol
Disassemble instructions in memory
Dump memory to a file
Begin user' program execution
Fill memory with a data pattern
Load user program or mapping configuration
Invisible Single Step with Trace
Display command syntax and description
Structured to provide two levels of information for commands
Evaluate a hexadecimal expression
Initialize AIM-68000; Relocate Control Memory
Locate,a pattern of data in memory
Log user activity to a host file
Map emulation memory into target memory space
Display and/or update memory
Terminate AIM-68000 operation
Test RAM memory; continuous test option
Examine or modify register contents
Examine the Software Trace buffer
Choose registers or symbols for Step and Trace Display
Set Exception Vector Map
Enter or display symbols in table
Single Step with Software Trace
Communicate with the host transparently
Verify memory against other memory

Note that the ACCESS command limits emulator accesses
to word wide or byte wide operations only. A write only

option for the MEMORY command allows the user to set up
programmable peripheral devices manually.

VII-8

IlDS,/UDS

SPECIFICATIONS
Target Operating Frequency

1.0 to 10 MHz

Standalone Operating Frequency

10 MHz

Operating Temperature Range

0° - 40°C

Target Power Requirement

None

IDTACK

Signals from the MK68000 have the following maximum
delays:
Signal

Delay

Al-23

o ns

lAS

o ns

o ns
14 ns

E

o ns

FC2-0

o ns

IHAlT

o ns

IPl2-0

40ns

R/W

o ns

IRESET

o ns

IVMA

o ns

IVPA

20 ns

IBERR

40 ns

IBR

22 ns

IBG

o ns

** On a write cycle, DATA valid at the Target after the
falling edge of S2, t CLDO max.

IBGACK

Ons

ORDERING INFORMATION

ClK*

8 ns

For information on ordering AIM-68oo0 hardware and the
appropriate AIM68K software, refer to the Development
Products Ordering Guide.

*

DO-D15 t CLDO **

145 ns @ 10 MHz
135 ns@8 MHz
100 ns@6 MHz

,,11-9

Skew from the Target ClK to the MK6BOOO ClK input.

VII-10

I!I

UNITED

COMPUTER
PRODUCTS
DIVISION

TECHNOLOGIES
MOSTEK

AIM-Z80BE
APPLICATION INTERFACE MODULE

FEATURES

AIM-Z80BE PRODUCTS
Figure 1

o Direct interface to Mostek's RADIUS Development
Station and MATRIX-80/SDS Development System
o In-circuit emulation of the l80 microprocessor
o Real-time execution (to 6 MHz with no wait states)
o Flexible breakpoints (one hardware, eight software, and
one timer)
o Single-step execution
o 16 K bytes of emulation RAM
o Memory mappable into target or AIM system memory in
256 byte blocks
o Illegal write-to-memory detection
o Non-existent memory mapping and access detection
o Forty-eight-channel-by-l 024-words history memory for
tracing bus events
o T-state timer to measure execution time
o English-oriented command structure
o Disassembly of instructions
o System configuration parameters can be saved forfuture
use
GENERAL DESCRIPTION
AIM-l80BE is an advanced development tool which
provides debug assistance for both software and hardware
via in-circuit-emulation of the l80 microprocessor. Use of
the AIM-Z80BE is transparent to the user's final system
configuration (referred to as the "targe!"). No memory space
o'r user ports are used, and all signals, including RESET INT,
and NMI are functional during emulation. No memory wait
states are required.
Single-step circuitry allows the user to execute target
instructions one at a time to see the exact effect of each

instruction. Single step is functional in both ROM and RAM.
Up to 16K bytes of contiguous emulation RAM can be used
to emulate the target microprocessor RAM or ROM. Thus,
debugging can begin before the user system is completely
configured with memory.
Breakpoint-detect circuitry allows real-time execution to
proceed to any desired point inthe user's program and then
terminate execution. All CPU status information and
register contents can be displayed forthe user and saved for
later continuation of execution or single-stepping. Realtime execution may be terminated by the user at any time.
EVENT and DELAY counters associated with the hardware
breakpoint give added flexibility for viewi ng the exact point
of interest in the user's program.
A forty-eight channel history memory records up to 1024
bus transactions. The address bus, data bus, control signals,
and 18 external probes may be logged into the history
memory and later displayed by the user.

VII-ll

AIM·l80SE SLOCK DIAGRAM
Figure 2

PERSONALITY MODULE

HISTORV MODULE

TIMER

R':."~~':,§E!~.!."~~·:'0I%r.!.b':;;;:;8~8i"f=:~:::':':':"C"':::',"'C::':":,:,:,:~:,:,:,:::,:::,C,:::: ,: .: ,:,:,:,:,:,:,:, : : : : :
ADDRESS CONTROL BUS

BLOCK DIAGRAM DESCRIPTION

logging elapsed time and generating the timer breakpoint.

The ZSO emulation system is composed of two boards, the
Control Module and the History Module, as shown in Figure
2. These boards are attached to a Personality Module which
contains the target CPU and plugs directly into the target
system CPU socket. Address, data, and control signals are
buffered by the Personality Module and cabled to the
Control and History Module installed in the development
system.

USING THE AIM-Z80SE

The Control Module has the circuitry for detecting the
breakpoint condition(s) and forces program execution to
begin in a separate System Interface RAM. The System
Interface RAM is loaded with an interface program and is
shadowed into the target memory space. This control
program makes the target CPU a slave to the development
system. When the user desires to resume execution of his
program,the control program activates the execution
control circuit and execution resumes at the .desired
address. The Control Module contains 16 K bytes of emulation
RAM, which may be mapped into any address space
required by the target system. Alternatively, if the user's
system has memory available, he may use that as his target
memory instead of the memory on the Control Module.
The History Module has a 24-bit comparator circuit, an
EVENT counter, and a DELAY counter to detect a hardware
breakpoint condition. The 48-channel·by-1024-word history RAM is controlled bY the History Control Circuit.

The Control and History Modules of AIM-Z80BE are
installed directly into the development system. To complete
the emulation system the Personality Module is used as a
buffer interface between the first two boards and the target
system's
CPU socket.

zao

The program which controls the AIM-Z80BE emulator
system is AI MZ80. After execution of AIMZ80 is started, the
program takes control of the AIM-Z80BE emulation system.
The user can then initialize the target system and use .the
AIMZ80 commands to load, test, and debug the target
program.
AIMZ80 SOFTWARE
AIMZ80 is the software which operates the AIM-ZSOBE
emulation system in the RADIUS Development Station or
MATRIX Development System. Target system programs
may be developed on a Mostek disk system by use of the
apprppriate assembler. Programs may be developed for
RADIUS cross products supplied by Mostek or other
vendors. The AIM software.is supplied on a variety of media
for use with Mostek disk-based development systems and
with different host systems for RADIUS. The commands
available in AIMZ80 are summarized below. Each
command also has a "short form" which allows abbreviated
input with fewer keystrokes.

The Timer Circuit is used to count target processor clocks for

VII-12

BATCH
BREAK
CLEAR
COpy
DISABLE
DISASSEMBLE
DUMP
ENABLE
EXECUTE
FILL
GET
HEXADECIMAL
HELP
HISTORY
INIT
LOCATE
LOG
MAP
MEMORY
OFFSET
PORT
QUIT
RAMTEST
REGISTER
STATUS
STEP
TRACE
TRANSPARENT
VERIFY

Read AIM commands from a file
Display and set breakpoints (8 software, 1 hardware, and 1 timer breakpoint)
Clear one breakpoint or all breakpoints
Copy one block of memory to another block
Disable target CPU interrupts
Display and/or update instructions
Dump a block of memory to a file
Dump the memory map to a file
Enable target CPU interrupts
Start or continue execution of the target program
Fill memory with a data byte
Load a target program into memory
Load the target memory map from a file
Perform hexadecimal arithmetic
Display a menu of commands for the user
Set history logging options
Reinitialize target handshake
Locate a pattern in a memory block
Log all console output to a file
Map the block of memory as target supplied, AIM system supplied, or nonexistent, and write protected or not write protected
Display and/or update memory
Set an offset value for relative module debugging
Display and update a port on the target CPU
Output a value to a port without reading it
Return to the resident operating system
Perform a test on the target RAM
Display and/or update the target CPU registers
Display the current status of the AIM system
Perform a single or mUlti-step execution
Display the contents of the history RAM
Allows the RADIUS user to temporarily access the host
Verify the contents of a block of memory with another block or with a file.

SPECIFICATIONS
Target operating frequency: 500 kHz to 6 MHz (MK78204)
Target interface: all signals meet the specifications for the
Z80 with the following exceptions:
1. The output low voltage is 0.5 V max at 1.8 mA for the
ADDRESS, DATA. IORQ, RFSH, HALT, and BUSAK
signals.
2. The input low current is 400 microamps max for the PHI
clock, RESET, INT, NMI, and DATA signals.
3. The input high current is 20 microamps for the PHI
clock, RESET, INT, NMI, and DATA signals.

4. The Signals M 1, MREQ, RD, and WR have a maximum
of 25 nanoseconds added propagation delay.
5. The input signals RESET, INT, and NMI have a
maximum of 45 nanoseconds propagation delay.
Target system power requirements: +5 V
milliamps (maximum)

± 5%

System compatibility: RADIUS, MATRIX-80/SDS,
Operating temperature range; 0 to +50 degrees C

ORDERING INFORMATION
For detailed ordering information refer to the Development
System Products Ordering Guide.

VII-13

@ 600

VII-14

IJ

UNITED

COMPUTER
PRODUCTS
DIVISION

TECHNOLOGIES
MOSTEK

AIM-7XE
APPLICATION INTERFACE MODULE

FEATURES

o

AIM-7XE
Figure 1

Direct interface to Mostek's RADIUS Development
Station and MATRIX-80/SDS Development System

o In-circuit emulation of all MK3870 and MK3873 family
microprocessors (does not include piggy-back parts)
o Real-time execution (to 4 MHz with no wait states)
o Flexible breakpoints (one hardware, eight software, and
one timer breakpoint) and any number of manuallyinserted breakpoints
o Single-step execution
o 4 K bytes of emulation RAM
o Option of on-board oscillator or user clock
o Illegal write-to-memory detection
o Forty-eight-channel-by-1024-words history memory for
tracing bus events
o Event counter and delay counter for monitoring bus
events

Breakpoint-detect circuitry allows real-time execution to
proceed to any desired point in the user's program and then
terminate execution.

o T-state timer to measure execution time
o English-oriented command structure
o Disassembly of instructions

GENERAL DESCRIPTION
AIM-7XE is an advanced development tool which provides
debug assistance for both software and hardware via incircuit-emulation of the MK3870 and MK3873 family of
microprocessors. Use of the AIM-7XE is completely
transparent to the user's final system configuration
(referred to as the "target"). No memory space or user ports
are used, and all signals, including /RESET and /EXT INT,
are functional during emulation. No memory wait states are
required.
Single-step circuitry allows the user to execute ,target
instructions one at a time·to see the exact effect of each
instruction. 4 K bytes of emulation RAM are used to
emulate the target microprocessor ROM.

All CPU status information and registers can be displayed
for the user and saved for later continuation of execution or
single-stepping. Real-time execution may be terminated by
the user at any time. EVENT and DELAY counters
associated with the hardware breakpoint give added
flexibility for viewing the exact point of interest in the user's
program.
A forty-eight channel history memory records up to 1024
bus transactions. The address bus, data bus, ports 0, 1, and
either port 4, 5, or 8 external probes may be logged into the
history memory and later displayed by the user.

BLOCK DIAGRAM DESCRIPTION
The MK3870 Family emulation system is composed of both
the AIM-7XE system and personality modules. AIM-7XE
consists of two boards, the Control Module and the History
Module, as shown in Figure 2. These boards are attached by
cables to the Personality Module which contains the target

VII-15

AIM-7XE BLOCK DIAGRAM
Figure 2

APM

xx

AIM PERSONALITY MOOUlE

TARGET
SYSTEM

, -_ _ _-t:}-;:;=;;;;;-=;;-:;-;,--_ _ _ _ _...,AIM.7X?'_ _ _--i}-_===;;;-;;-;-____----,

FA

__

~NR

CPU and plugs directly into the target system CPU socket.
Address, data, and control signals are buffered by the
Personality Module.
The Control Module ha.s the circuitry for detecting the
breakpoint condition(s) and forces program execution to
begin in the System Interface RAM. The System Interface
RAM is loaded with an interface program and is shadowed
into the target memory space. This control program makes
the target 'cPU a slave to the development system. When
the user desires to resume execution of his program, the
control program activates the execution control circuit and
execution resumes at the desired addresS.
The History Board has a 24-bit comparator circuit, an
EVENT counter, and a DELAY counter to detect a hardware
breakpoint condition. The 48-channel-by-1024-word history RAM is controlled by the History control circuit. The
Timer circuit is used to count target processor clocks for
logging elapsed time and generating the timer breakpoint.
USING THE AIM-7XE
The Control and History Modules of the AIM-7XE are
ir)stalled directly into the Mostek development system. To
complete the emulation system a Personality Module is
required. This module is a buffer interface between the first

two boards and the target system's CPU socket. Note that a
complete user target system is not required to do software
debugging. Only the AIM-7XE boards and a Personality
Module are needed.
The program which controls the AIM-7XE emulator system
is named AIM7X. After execution of AIM7X is started, the
program takes control of the AIM-7XE emulation system.
The user can then initialize the target system and use the
AIM7X commands to load, test, and debug the target
program.
AIM7X SOFTWARE
AIM7X is the software which operates the AIM-7XE
emulation system in the Mostek RADIUS Development
Station or MATRIX Development System. Targetsystem
programs may be developed on a Mostek disk system for
RADIUSTM using cross products supplied by Mostek or other
vendors. The AIM7X software is available on a diskette for
Mostek disk-based systems and on a variety of media for
different host systems for use with RADIUSTM. The
commands available in AIM7X are summarized below.
Each command also has a "short form'.' which allows
abbreviated input with fewer keystrokes.

VII-16

BATCH
BREAK
CLEAR
COpy
DISABLE
DISASSEMBLE
DUMP
ENABLE
EXECUTE
FILL
GET
HEXADECIMAL
HELP
HISTORY
INIT
LOCATE
LOG
MEMORY
OFFSET
PORT
QUIT
RAMTEST
REGISTER
STATUS
STEP
TRACE
TRANSPARENT
VERIFY

Read AIM commands from a file
Display and set breakpoints (8 software, 1 hardware, and 1 timer breakpoint)
Clear one breakpoint or all breakpoints
Copy one block of memory to another block
Disable target CPU interrupts
Display and/or update instructions
Dump a block of memory to a file
Enable target CPU interrupts
Start or continue execution of the target program
Fill memory with a data byte
Load a target program file into memory
Perform hexadecimal arithmetic
Display a menu of commands for the user
Set history logging options
Reinitialize target handshake
Locate a pattern in a memory block
Log all console output to a file
Display and/or update memory
Set an offset value for relative module debugging
Display and update a port on the target CPU
Return to the resident operating system
Perform a test on the target RAM
Display and/or update the target CPU registers
Display the current status of the AIM system
Perform a single or multi-step execution
Display the contents of ~he history RAM
Allows the RADIUS user to temporarily access the host
Verify the contents of a block of memory with another block or a file

SPECIFICATIONS
Target operating frequency: 1 to 4 MHz
Target interface: All signals meet the specifications of the
MK3870 family exceptthat the XLT2 input will not accept a
user crystal. It requires a TTL clock input.
System compatibility: RADIUS, MATRIX-SO/SDS
Operating temperature range: 0 to +50°C

ORDERING INFORMATION
For detailed ordering information refer to the Development
System Products Ordering Guide.

VII-17

VII-18

!t

COMPUTER
PRODUCTS
DIVISION

UNITED
TECHNOLOGIES
MOSTEK

EPP-1
MK78229
EPROM PROGRAMMER
FEATURES

EPP-1
Figure 1

o Provides EPROM programming capability for RADIUS
o May be adapted for use with other computers
o Communicates with host via half-duplex RS232 or TIL
serial link
o Programs, reads, and verifies most +5 V EPROMs
available today
o 4 Selectable Baud rates: 300, 1200, 2400,9600
o Emulates a subset of DATA 110's System 19 command
set
o Includes wall mount transformer power supply
o 8K x 8 bits of on-board RAM
o 28 pin zero-insertion-force socket for 24 and 28 pin
EPROMs
o LED indicators for "programming" and "power on".
o High level commands for ease of use with RADIUS

GENERAL DESCRIPTION
The EPP-1 is a microcomputer controlled MOS EPROM
programmer capable of programming most MOS EPROMs
currently available. It can be upgraded by adding a bipolar
PROM to allow programming of new EPROMs when they
become available.

LED indicators are provided to show when the power is on
and when an EPROM is being programmed. A 28 pin zeroinsertion-force socket is supplied for use with 24 and 28 pin
EPROMs. 24 pin EPROMs are inserted with pin 1 of the
EPROM in pin 3 of the 28 pin socket as shown below,

The EPP-1 is designed to be used with the RADIUS remote
development station. The software for the RADIUS allows
use of all the commands supported by EPP-1 and additional
higher level commands for ease of use by the operator.
Communication with the host computer is via a serial link
which can be RS232 or TIL compatible. Baud rates are
selectable to 300, 1200, 2400 or 9600 Baud. The unit is
powered by a II'/all mount transformer which provides
unregulated DC voltages to the programmer.

VII-19

•

EPROMs SUPPORTED
The following EPROMs may be programmed by the EPP-1.

MANUFACTURER

PART #

SIZE

FAMILYIPINOUT
CONFIGURATION #

ADVANCED MICRO DEVICES

4716

2K x8

1923

ELECTRONIC ARRAYS

2716

2K x8

1923

FUJITSU

8516 (2716)

2Kx8

1923

HITACHI

46532

4Kx8

1925

HITACHI

46732

4K x8

1924

INTEL

2758

1K x8

1922

INTEL

2716

2K x8

1923

INTEL

2732

4Kx8

1924

INTEL

2764

8Kx8

3533

MITSUBISHI

2716

2Kx8

1923

MOSTEK

2716

2K x8

1923

MOTOROLA

MCM2716

2Kx8

1923

MOTOROLA

2532

4Kx8

1925

MOTOROLA

68764

8K x8

6424

NATIONAL SEMICONDUCTOR

2716

2K x8

1923

NATIONAL SEMICONDUCTOR

2532

4Kx8

1925

NATIONAL SEMICONDUCTOR

2732

4K x8

1924

NIPPON ELECTRIC

2716

2Kx8

1923

OKI

2716

2Kx8

1923

TEXAS INSTRUMENTS

2508

1Kx8

1922

TEXAS INSTRUMENTS

2516

2K x8

1923

TEXAS INSTRUMENTS

2532

4Kx8

1925

TEXAS INSTRUMENTS

2564

8Kx8

3130

TOSHIBA

323

2Kx8

1923

VII-20

SOFTWARE

COMMAND

The high level commands supported by the RADIUS
software for EPP-l are:

OUTPUT xxxx xxxx
'filename'

COMMAND

DESCRIPTION

BATCH 'filename'

Accept command input
from a Host file

BIT

Illegal bit test on EPROM

BLANK

Check if EPROM is blank

COMPARE 'filename'

Compare data from Host to
EPROM Programmer

DEVICE xxxx

Select the device address
to be used for
programming, verifying, or
loading device data

DIRECT

Allows direct entry of
commands to the EPROM
programmer via the consale. May be terminated
with control-C.

FAMILY [xxxx]

Select/display the family/
pinout

HELP [Command name]

Display a HELP description
of all commands or of a
specific command

DESCRIPTION

Output data from EPROM
programmer to Host

*(pause [msg])

Pause while in batch
mode; message can be
displayed,

PROGRAM

Program EPROM device
with data in RAM

QUIT

Exit the utility; return
EPROM programmer to
keyboard control

RAM xxxx

Select RAM address to be
used for data transfer

SHUFFLE xxxx

Merge 2 blocks of RAM;
complement of SPLIT

SIZE xxxx

Select the hex number of
bytes to be transferred;
must be selected after
RAM command

SPLIT xxxx

Split even/odd numbered
bytes into 2 blocks;
complement of SHUFFLE

SUM

Calculate check-sum of
programmer RAM

INPUT 'filename'

Input data from Host to
EPROM programmer

SWAP

Swap nibbles in every byte
in RAM

LOAD

Load EPROM data from the
EPROM into RAM

TRANSPARENT

LOG 'filename'

Log console activity to a
Host file

Allows RADIUS
development system transparent communication to
Host

VERIFY
MEMORY xxxx [xxxx]

Display or update EPROM
programmer RAM

Verify EPROM device with
data in RAM

MOVE xxxx xxxx xxxx

Move a block of data in
RAM

OFFSET xxxx

Select an offset to be
added to input addresses
and subtracted from output
addresses

VII-21

EPP-' DIRECT COMMAND SUMMARY
CONTROL COMMANDS
RETURN·

Execute a command

ESC

Abort a command

UTILITY COMMANDS

G

Software Configuration number

This command returns a 4-digit hex number
representing the software configuration of the programmer.

(HHHH)<

Set Begin RAM

BLOCK LIMIT L 1 . Defines first RAM address (in HEX) to
be used for data transfers. Also functions as the RAM
source address in the RAM-RAM Block Move command.

(HHHH);

Set Block Size

BLOCK LIMIT L2. Sets number of bytes (in HEX) to be
transferred. Must be set after the Set Begin RAM
command is used.

(HHHH):

Set Begin Device

BLOCK LIMIT L3. Sets the first device address (in HEX)
to be used in data transfers. Also functions as the
destination address in the RAM-RAM Block Move
Command.

S

Sum-Check

Causes programmer to calculate the check-sum of RAM
data and output it to the computer.

F

Error-Status Inquiry

EPROM programmer returns a 32 bit error code.

X

Error-Code

EPROM programmer outputs Error Codes stored in
scratchpad RAM and then clears them from memory.

H

No operation

This is a null command and always returns a prompt
character (».

T

Illegal Bit Test

Test for illegal bit in a device.

B

Blank Check

Check that no bits are programmed in a device.

Family and Pinout

EPROM programmer sends a 4-digit number (FFPP)
where FF is the family code and PP is the pinout in
effect.

Select Family and Pinout

A 2-digit family code (FF) and pinout code (PP) specifies
programming of a particular device.

R

Respond

Programmer indicates status and outputs device word
limit, byte size, and programming pulse polarity.

L

Load

Load device data into RAM.

P

Program

Program RAM data into device.

V

Verify

Verify device against RAM.

DEVICE COMMANDS

(FFPP)@

VII-22

1/0 COMMANDS
Set Address Offset

Sets the specified offset to be subtracted from all
incoming addresses and added to all outgoing addresses.

Input

Input data from computer to RAM.

o

Output

Output data from RAM to computer.

C

Compare

Compare RAM data with data from computer.

RAM-RAM Block Move

Initiates transfer of data from one block RAM to another.
Block limits must first be set.

W

EDITING COMMANDS
\

PROGRAMMER RESPONSES
>+RETURN + LINE FEED

Prompt character. Informs the computer that the
EPROM programmer has successfully executed a
command.

F+RETURN + LINE FEED

Fail character. Informs the computer that the EPROM
programmer has failed to execute the last-entered
command.

?+RETURN + LINE FEED

Question mark. Informs the computer that the EPROM
programmer does not understand a command.

TECHNICAL SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

Dimensions

Serial Communication Unk

7.8 in (19.8 cm) x 10.8 in. (27.4 cm)
2.0 in. (5.1 cm) maximum thickness

RS232 or TfL compatible
Operating Temperature

20°C to 40°C
Power Supply Requirements
115 V AC @ 200 ma

VII-23

ORDERING INFORMATION
Designator

EPP-'
EPP-'

Part No.

, Description

EPROM PROGRAMMER w/wall mount transformer (US)

MK78229-0

, EPROM PROGRAMMER' w/in line transformer (international)
EPP.' Technical Manual

• MK78299-'
4420379

.'

.'{

.

,~,

l!

UNITED

COMPUTER
PRODUCTS
DIVISION

TECHNOLOGIES
MOSTEK

MATRI)(TM-80/SDS
MICROCOMPUTER DEVELOPMENT SYSTEM
INTRODUCTION

MATRIXTM-80/SDS
Figure 1

The Mostek MATRIXTM is a complete state-of-the-art, floppy
disk-based computer. Not only does it provide all the
necessary tools for software development, but it provides
complete hardware/software debug through Mostek's
AIMTM series of in-circuit emulation cards for the 68000,
Z80, and the 3870 family of single-chip microcomputers.
The MATRIX has at its heart the powerful OEM-80E (Single
Board Computer), the RAM-80BE (RAM I/O add-on board),
and the FLP-80E (floppy disk controller board). Because
these boards and software are available separately to OEM
users, the MATRIX serves as an excellent test bed for
developing systems applications.
The disk-based system eliminates the need for other mass
storage media and provides ease of interface to any
peripheral normally used with computers. The file-based
structure for storage and retrieval consolidates the data
base and provides a reliable portable media to speed and
facilitate software development.
Development System Features
The MATRIX is an excellent integration of both hardware
and software development tools for use throughout the
complete system design and development phase. Debug
can then proceed inside the MATRIX domain using its
resources as if they were in the final system. Using
combinations of the Monitor, Designer's Debugging Tool,
execution time breakpoints, and single step/multistep
operation along with a formatted memory dump, provides
control for attacking those tough problems. The use of the
Mostek AIMTM options provides extended debug with
versatile hardware breakpoints 'ln memory or port
locations, a buffered in-circuit emulation cable for
extending the software debug into its own natural hardware
environment.
Package System Features
From a system standpoint, the MATRIX has been designed
to be the basis of an end-product, such as a small
business/industrial computer. Other hardware options are
available, with even more to be added. Expansion of the disk
drive units to a total of four single-sided or double-sided
units provides up to two megabytes of storage. This
computer uses the third-generation Z80 processor
supported with the power of a complete family of peripheral
chips. Through the use of its 158 instructions, including

16-bit arithmetic, bit manipulation, advanced block moves
and interrupt handling, almost any application from
communication concentrators to general purpose accounting
systems is made easy.
OEM Features
The hardware and software basis for the MATRIX is also
available separately to the OEM purchaser. Through a
software licensing agreement, all Mostek software can be
utilized on these OEM series of cards.
MATRIX RESIDENT FIRMWARE (DDT-80)
The Designer's Debugging Tool consists of commands for
facilitating an otherwise difficult debugging process. The
MATRIX allows rapid source changes through the editor
and assembler. This is followed by DDT operations which
close the loop on the debug cycle. The DDT commands
include:

VII-25

Memory
Port
Execute
Hexadecimal
Copy

-display, update, or tabulate memory
- display, update or tabulate I/O ports
-execute user's program
- performs 16 bit add/sub
-copy one block to another

•

provided. Symbolic addressing and an extensive HELP
Facility ease the uSEl of AIM-6S000.

MATRIX SYSTEM SPECIFICATIONS
•
•
•
•
•
•
•
•
•
•

Z80CPU
4K-byte PRDM bootstrap and Z80 debugger
60K bytes user RAM (56K contiguous)
8 x 8.bit I/O. ports (4 x PID) with user-definable
t;lrivers/ receivers
Serial port, RS 232 and 20 mA current loop
4 channel counter/timer (CTC)
2 single-density, single-sided disk drives; 250K bytes
per floppy disk
3 positions for AIM modules, Serial Interface, etc.
PRDM programmer I/O. port. Programmer itself is
optional.
Bus compatible with Mostek SDE series of DEM boards

HARDWARE DESCRIPTION OEM-SOE
CPU Module
The DEM-80E provides the essential CPU power of the
system. While using the Z80 as the central processing unit,
the DEM-80E is provided with other Z80 family peripheral
chip support. Two.ZSO PID's give 4 completely programmable
8 bit parallel I/O. ports with handshake from which the
standard system peripherals are interfaced. Also on the
card is the Z80-CTC counter timer circuit which has 3 free
flexible channels to perform critical counting and timing
functions. Along with 16K of RAM, the DEM-80E provides 5
RDM/PRDM sockets which can be utilized for 10120K of
RDM or 5/1 OK PRDM. Four sockets contain the firmware.
The remaining socket can be strapped for other
RDM/PRDM elements.
RAM-SOBE

AIM-ZSOBE (6.0 MHz max. clock rate)
The AIM-Z80BE is an improved Z80 In-Circuit-Emulation
module usable at ZSO-CPU clock rates of up to 6MHz. The
AIM-Z80BE is a two processor solution to In-Circuit
Emulation which utilizes a Z80-CPU in the buffer box for
accurate emulation at high clock rates with minimum
restrictions on the target system. The AIM-Z80BE provides
real time emulation (no WAIT states) while providing full
access to RESET, NMI and INT control lines. Eight single
byte software breakpoints (in RAM) are provided as well as
one hardware trap (RAM or RDM). The emulation RAM on
the AIM-Z80BE is mappable into the target system in 256
byte increments. A 1024 word x 48 bit history memory is
triggerable by the hardware intercept and can be read back
to the terminal to provide a formated display of the Z80-CPU
address, data, and control busses during the execution of
the program under test. Several trigger options are available
to condition the loading of the history memory.
AIM-7XE
The AIM-7XE module provides debug and in-circuit
emulation capabilities for the 3870 series microcomputers
on the MATRIX. Multiple-breakpoint capability and singlestep operation allow the designer complete control over the
execution of the 3870 Series microcomputer.
Register, Port display, and modification capability provide
information needed to find system "bugs." All I/O is in the
user's system and is connected to AIM-7X by a 4O-pin
interface cable.

The RAM-80BE adds additional memory with Mostek's
MK4116 16K dynamic memory along with more I/O.. These
two fully programmable 8-bit I/O. ports with handshake
provide additional I/O. expansion as system RAM memory
needs to grow. Standard system configuration is 48K bytes
for a system total of 60K bytes user RAM (56K contiguous).

The debugging operation is controlled by a mnemonic
debugger which controls the interaction between the Z80
host computer and the 3870 slave. It includes a history
module for the last 1024 CPU cycles and also supports all
3870 family circuits.

FLP-SOE

DCC-SOE

Integral to the MATRIX system is the floppy disk controller.
The FLP-80E is a complete IBM 3740 single-density/
double-sided controller for up to 4 drives. The controller has
128 bytes of FIFO. buffer resulting in a completely
interruptable disk system.

The DCC-8bE multi-channel serial controller board was
developed as a general purpose four port serial I/O. card.
DCC-80E can be user configured to interconnect computer
systems and will support SDLC and BYSINC protocols.

OPTIONAL MODULES COMPATIBLE WITH MATRIX

Assembly and linking are done using cross products
supplied by Mostek or other vendors.

AIM.6S000 (10 MHz max. clock rate)
MECHANICAL SPECIFICATIONS
The AIM-68000 is an advanced development tool which
provides project debug capabilities for both hardware and
software via in-circuit emulation of the MK68000
Microprocessor. Real-time emulation is provided up to 10
MHz operation. Flexible breakpoints and Single-Step
emulation with. Invisible Break on Register Contents are

Dverall Dimensions:
CPU subsystem
- 8" High x 21" wide x 22." deep
(20.3 cm x 53.3 cm x 55.8 cm)
- 8" High x.21" wide x 22" deep
Disk Subsystem
(20.3 cm x 53.3 cm x 55.8 cm)

VII-2.6

Humidity: up to 90% relative, noncondensing.

ELECTRICAL SPECIFICATIONS

Material: Structural Foam (Noryl)

INPUT 100/1151230 volts AC ± 10%
50 Hz (MK78189) or 60 Hz (MK78188)

Weight: CPU Subsystem 25 Ibs (11.3 Kg)
Disk Subsystem 50 Ibs (22.7 Kg)

OUTPUT
CPU subsystem

Fan Capacity: 11 5 CFM

+5 VDC at 12A max.
+12 VDC at 1.7A max.
-12 VDC at 1.7A max.

Card Cage: Six slots DIN 41612 type connectors
Disk subsystem
Operating Temperature: +10°C to +35°C

+5 VDC at 3.0A max.
-5 VDC at 0.5A max.
+24 VDC at 3.4A max.

ORDERING INFORMATION
See Development System Products ordering guide.
PERIPHERALS AND CABLES

NAME

DESCRIPTION

PART NO.

PPG-8/16

Programmer for 2708, 2758 and 2716 PROM
Includes interfacing cables to MATRIX.

MK79081-1

SD-WW

Wire wrap card compatible with MATRIX.

MK79063

SD-EXT

Extender card compatible with MATRIX.

MK79062

LP-CABLE

Interface cable from MATRIX Microcomputer to Centronics
306 or 702 printer

MK79089

PPG-CABLE

Interface cables from MATRIX to PPG-8/16 PROM
programmer (MK79081 ).

MK79090

III
VII-27

VII-28

!t

UNITED

COMPUTER
PRODUCTS
DIVISION

TECHNOLOGIES
MOSTEK

EVAL-70
3870 EVALUATION SYSTEM

FEATURES

o

An ideal hardware and/or software design aid for the
MK38P70 and MK3870 family of Single-Chip
Microcomputers

o

Includes a 2K byte firmware monitor

o

Keypad for command and data entry

o

7-segment address and data display

o

Programming socket for MK2716/2758's

o

Crystal controlled system clock

o

2K bytes of MK4118 static RAM (up to 4K optional)

o

Sockets for up to 4K bytes of MK2716 PROM's

o

Flexible memory map strapping options

o

Current loop or RS-232 serial loader optional (110-300·
1200 baud)

o

3 general purpose timer/counters

o

3 general purpose external interrupt!,

o

Easy to use - requires only two supplies for normal
operation (+5, +12)

o

Ideal for evaluation of MK3870familysingle-chip microcomputers

o

Full in-circuit emulation of MK3870 single-chip microcomputer family.

EVAL-70
Figure 1

USING EVAL-70

DESCRIPTION
EVAL-70 is a single board computer with on-board keypad,
address and data displays, and 2716 PROM programmer.
EVAL-70 is designed to be an easy-to-use introduction to the
industry standard MK3870 family of single-chip computers.
Programs can be written and debugged in RAM using the
powerful DDT-70 operating system. The 40 pin AIM cable
can be used to perform real-time emulation of the MK3870
family of devices. After debugging, programs can be loaded
into MK2716's for final circuit checkout (and emulation).

The photograph above shows how EVAL-70 is used as a
program development tool. Only an external power supply is
required for operation of EVAL-70; the built-in keyboard and
display offer all the functions needed to design, develop, and
debug programs for the MK3870 family of single-chip
microcomputers at the machine code level.
COMMAND SUMMARY
DM:

Display memory: allows memory to be displayed
and (RAM) updated.

DR:

Display registers: allows the user's register values
to be displayed and updated.

DP:

Display ports; allows the contents of ports 0 thru

F to be displayed and updated
HX:

Hex calculator: allows hexadecimal arithmetic
calculations to be performed (add and subtract)

GO:

causes execution of a user program at a specified
address

VII-29

BK:

Breakpoint all,ows a breakp,ointt,o be set,or reset

ST:"

'Step: bauses single-stepexecuti,on,of a user program at a specified address

LD:

I.,..oad: initiates the serial loader (,opti,onal)

MV:

Move: all,ows a block,of mem,ory to be moved ,or
copied from one space to another

RO, R8:

Read PROM: causes the PROM programmer
socket to be read into address space 00-7FF or
BOO-F7F'
,

PO, P8:

Program PROM: causes the contents,of address
space 000-7FF or 800-F7F to be programmed
into the PROM programmer socket

EVAL-70 KEYBOARD DRAWING

IElulRILlllol

BLOCK DIAGRAM
EVAL-70 uses several membersofthe F8 multichipfamily.A
MK3850 Central Processing Unit (CPU) provides the ALU,
registers, system control and two 8-bit ports. A MK90071
Peripheral Input Output chip (PIO) provides two more 8-bit
ports plus a flexible timerlinterrupt c,ontrol block, These four
ports are connected to the AIM cable connector for in-circuit
emulation of the MK3870 family devices, and also to the
PROM programmer socket. An additional PIO (MK90073)
interfaces the LED display and keyboard. A MK3853 Static
Memory Interface chip(SMI) interfaces the operating system
ROM, uptotw02K PROMs and uptofour 1 K RAMs. A switch
option allows either the 4K of PROM or the 4K of RAM to
appear at address OOOOH, with the other 4K appearing at
1000H. The operating system ROM may be up to 8K
(currently 2K) starting at8000H. A switch option allows reset
to either OOOOH or to the 8000H ROM.

USING EVAL-70 WITH LARGER SYSTEMS

BLOCK DIAGRAM

Although the EVAL-70 operating system (DDT-70) was
designed to make program machine code entry simple and
quick, many users will find it more efficient to assemble their
programs on a larger computer and then download to
EVAL-70,
The download to EVAL-70 may be accomplished in either of
two ways:
1)

SMI
MK3853

I

I

I:"
,

PIO
MK90073

2)

':

KEYBOARD

VII-30

A PROM may be programmed on the Development System, and then read into RAM by the
EVAL-70 for debugging.
A direct connection may be made between a
serial port on the Development System and the
serial loader port on EVAL-70, An optional,serial
l,oader program is provided in the EVAL-70
Operations Manual.

DEVELOPMENT SYSTEM

DEVELOPMENT SYSTEM

EVAL-70

•
VII-31

EVAL-70 BOARD

SPECIFICATIONS
Operating Temperature: DoC - 50°C
Power Supplies Required: +5VDC ±5% 1.0A max
+12VDC ±5% O.1A max
+25VDC ±5%O.1A max
Board Size: 8.5 in. (21 .6 cm) x 12 in. (30.5cm) x 2 in. (5cm)
Connectors and Cables: .40 pin in-circuit-emulation cable
is provided.

ORDERING INFORMATION
See Develepment System Products ordering guide.

VII-32

Il

UNITED

COMPUTER
PRODUCTS
DIVISION

TECHNOLOGIES
MOSTEK

PPG8/16C
PROM PROGRAMMER

FEATURES

PPG 8/16C
Figure 1

o Programs, reads, and verifies 270S-, 275S-, and 2716type PROMs (275S and 2716 PROMS must be 5-Volt
only type)
o Interfaces to MATRIX and MDX-PIO
o Driver software included on system diskette for
M/OS-SO
o Zero-insertion-force socket
o Power and programming indicators
DESCRIPTION

The PPG-S/16C PROM Programmer is a peripheral which
provides a low-cost means of programming 2708, 275S, or
2716 PROMs. It is compatible with Mostek's MATRIX
Microcomputer Development System and the MDX-PIO.
The PPG-S/16C has a generalized computer interface (two
S-bit 1/0 ports) allowing it to be controlled by other types of
host computers with user-generated driver software. A
complete set of documentation is provided with the PPGS/16C which describes the internal operation and details
user's operating procedures
The PPG-S/16C is available in a metal enclosure for use
with the MATRIXTM and the MDX-PIO. Interface cables for
either the MATRIX or MDX-PIO must be purchased
separately.
SOFTWARE DESCRIPTION

The driver software accomplishes five basic operations.

These are (1 ) loading data into host computer memory, (2)
reading the contents of a PROM into host computer
memory, (3) programming a PROM from the contents ofthe
host computer memory, (4) verifying the contents of a
PROM with the contents of the host computer memory, and
(5) display and update of the host computer memory.
The driver software is provided on the M/OS-SO system
diskette. The user documentation provided with the PPGS/16C fully explains programming procedures to enable a
user to develop a software driver on a different host
computer.

VII-33

•

PPG 8/16C' BLOCK DIAGRAM
Figure 2

J1
CONNECTOR

TO
HOST
COMPUTER
01

MODE
SELECT
CIRCUIT

J2

+12VDC

CONNECTOR
TO
+5, +12, -12
POWER SUPPLV

+5VDC
GND
-12VDC

PROGRAM
PULSE
CONVERTER

R':U~~R I

fI

+27.5 VDC
PROGRAM
LED

STEP-UP
VOLTAGE
REGULATOR

-5VDC +5 VDC

+12VDC

INTERFACE

OPERATING TEMPERATURE

25-pin control connector (0 type)
4O-pin control connector (0.1-in. centers card edge)
for AIO-SOF, SOB-SO, SOB-50170, or MATRI)(TM
12-pin power connector (0.156-in. centers card edge)
All control signals are TTL-compatible

PROGRAMMING TIME

POWER REQUIREMENTS

270S - 2.5 minutes
275S - 0.9 minutes
2716 - 1.S minutes

+ 12 VOC at 250mA typical
+5 VOC at 1OOmA typical
-12 VOC at 50mA typical

ORDERING INFORMATION
See Development System Products ordering guide.

VII-34

08
2758/
MK2708/
MK2716
SOCKET

l!I

UNITED

COMPUTER
PRODUCTS
DIVISION

TECHNOLOGIES
MOSTEK

DEVELOPMENT SYSTEMS PRODUCTS
ORDERING GUIDE
RADIUS - Remote Development Station
RADIUS is a hardware/software development station that connects to a host computer. When you order a RADIUS, you
must specify the operating voltage characteristics. The host software must be ordered separately (as described in the next
section).

DESCRIPTION

ORDER

RADIUS for 60 Hz, 115 VAC Operation

MK78213

RADIUS for 50 Hz, 230 VAC Operation

MK78214

RADIUS HOST SOFTWARE
RADIUS host software is provided on a variety of media depending on host environment. When you order please specify one
of the following.

DESCRIPTION

ORDER

M/OS Version - implemented for M/OS-80 and CP/M supplied on single-sided,
single-density, 8-inch floppy diskette.

MK78224-11

RSX Version - implemented for RSX-11 M V3.2 supplied on DEC DOS-11
format 9-track magnetic tape, 800 BPI. Host must have a FORTRAN IV (ANSI-66)
compiler.

MK78224-33

VMS Version - implemeted for VMS V2.3 supplied on DEC DOS-11 format
9-track magnetic tape, 800 BPI. Host must have a FORTRAN IV (ANSI-66)
compiler.

MK78224-34

Rehostable Version - supplied in source form. Host must have a FORTRAN IV
(ANSI-66) compiler. Supplied on ASCII 9-track magnetic tape, 800 BPI, blocked in
80-character records.

MK78224-45

MATRIX - Microcomputer Development System
MATRIX is a stand-alone, floppy disk-based development system. It is supplied with FLP-80DOS, an editor, an assembler,
and a linker. When you order a MATRIX, you must specify the operating voltage characteristics.

DESCRIPTION

ORDER

MATRIX for 60 Hz, 115 VAC operation

MK78188

MATRIX for 50 Hz, 230 VAC operation

MK78189

VII-35

•

AIM-7XE (Application Interface Module for 387X)
AIM-7XE is the in-circuit-emulator for the 387X family. It will function in both RADIUS and MATRIX. When AIM-7XE is
ordered, a personality module must also be ordered. This personality module provides emulation forthe 3870 or 3873 family.
In addition, the AIM-7X software must be ordered separately (as described in next section).

DESCRIPTION

ORDER

AIM-7XE - control board and history board for 387X families.

MK79094

APM-70 - personality module for 3870 family

MK79093

APM-73 - personality module for 3873 family

MK79092

AIM-7X (Software for AIM 7XE)
The following software configurations are available for use with AIM 7XE. Please specify one ofthe following when ordering.

DESCRIPTION

ORDER

FLP-80DOS Version - configured for use with MATRIX. Supplied on singlesided, single-density, 8-inch floppy diskette.

MK78225-22

M/OS-80 Version - configured for use with M/OS-80 and CP1M host and
RADIUS. Supplied on single-sided, single-density, 8-inch floppy diskette.

MK78225-10

RSX and VMS Version - configured for use with RSX-11 M V3.2 and
VMS V2.3 host and RADIUS. Supplied on DEC DOS-11 format 9-track magnetic
tape, 800 BPI.

MK78225-30

ASCII Version - configured for use with general host and RADIUS. Supplied
on ASCII 9-track magnetic tape, 800 BPI.

MK78225-40

M/OS-80 Version - configured for use with MATRIX. Supplied on single-sided,
single-density, 8-inch floppy diskette.

MK78225-11

AIM-Z80AEI AIM-Z80BE (Application Interface Modules for Z80)
AIM-Z80AE and AIM-Z80BE are the in-circuit-emulators for theZ80. Theywill function in both RADIUS and MATRIX. When
either of the two is ordered, the AIM-Z80 software must be ordered separately (as described in the next section).

DESCRIPTION

ORDER

AIM-Z80AE - In-circuit-emulator for 2.5 and 4 MHz Z80. Provides 32K
emulation RAM

MK78181-4

AIM-Z80BE - In-circuit-emulator for 2.5, 4, and 6 MHz Z80. Provides
16K emulation RAM

MK78204

VII-36

AIM-Z80 (Software for AIM-Z80AEI AIM-Z80SE)
The following software configurations are available for use with AIM-Z80AE or AIM-Z80BE. Please specify one of the
following when ordering.

DESCRIPTION

ORDER

FLP-80DOS Version - configured for use with MATRIX. Supplied on single-sided,
single-density, 8-inch floppy diskette.

MK78226-22

M/OS-80 Version - configured for use with M/OS-80 and CPIM host and
RADIUS. Supplied on single-sided, single-d''lnsity, 8-inch floppy diskette.

MK78226-10

RSX and VMS Version - configured for use with RSX-11 M V3.2 and VMS V2.3
host and RADIUS. Supplied on DEC DOS-11 format 9-track Magnetic tape, 800
BPI.

MK78226-30

ASCII Version - configured for use with general host and RADIUS. Supplied on
ASCII 9-track magnetic tape, 800 BPI.

MK78226-40

M/OS-80 Version - configured for use with MATRIX. Supplied on single-sided,
single-density, 8-inch floppy diskette.

MK78226-11

AIM-68000 (Application Interface Module for 68000)
AIM-68000 is the in-circuit-emulator for the 68000. It will function in both RADIUS and MATRIX. When AIM-68000 is
ordered, the AIM-68000 software must be ordered separately (as described in the next section).
.

DESCRIPTION

ORDER

AIM-68000 - In-ciruit-emulator for up to 10 MHz 68000. Includes two (2) control
boards and a buffer boxlcable assembly.

MK78228

-----

AIM-6BOOO (Software for AIM-6BOOO)
The following software configurations are available for use with AIM-68000. Please specify one of the following when
ordering.

DESCRIPTION

ORDER

RSX and VMS Version - configured for use with RSX-11 M V3.2 and VMS V2.3
host and RADIUS. Supplied on DEC DOS-11 format 9-track magnetic tape, 800
BPI.

MK78232-30

ASCII Version - configured for use with general host and RADIUS. Supplied on
ASCII 9-track magnetic tape, 800 BPI.

MK78232-40

VII-37

..

PPG-8/16C (EPROM Programmer)
PPG-8/16Gfs8 programmer for use with MATRIX.It,includes interiacecableto MATRIX and FLP-80DOS compatible driver
(on floppy diskette).

DESCRIPTION

ORDER

PPG-8/16C EPROM programmer

MK79081-1

EVAL-70
EVAL-70 is a 3870 family evaluation system. Itincludes an .in-circuit-emulation cable.

'I DESCRIPTION

ORDER

EVAL-70

MK79086

SD/SDE ADAPTER
This board adapts SDE form factor boards to previous systems using SD form factor boards. This allows current AIM's to be
used with the AID-80F system.

';,':

DESCRIPTION

ORDER

SD/SDE ADAPTER

MK79095

"

VII-38

1983 COMPUTER PRODUCTS DATA BOOK

!t

UN1T,ED '
TECHN.OLOGIES'
,MOSTEK,'"

COMPUTER·
PRODUCTS
DIVISION
APPLICATION NOTE #1
INTERFACING MOSTEK'S
MDX-PIO TO OPTO-22'S PB24

INTRODUCTION

SYSTEM CONSIDERATIONS

The impact of the microprocessor has, at . least, been
overwhelmiDg.: As consumers, most of us would be' hard
pressed toJihd any appliance that doesn't have some type of
microprocessor conta,ned within. Ln the area of i I'lstrumentation the microprocessor has brought about the development of a new generation of "smart" instruments.

In general, when controlling valtages in excess of 5 volts
and currents,in excess of 50 milliamps, devices other than
ICs must be used. The salid state relay has provided the
system designer with the perfect interface between the low
current, law valtage world of the microprocessar and that of
the real world. These relays come in many different sizes
and specificatians with regards to voltage and current. For
this application ,note, we will be dealing with the plug-in
modules offered ,by such manufacturers as Opto-22,
Gordas, and Guardian. These modules come in bathAC and
DC versions with inputs and .outputs available in each type.
In general, these modules are capable afcontralling up to 3
amps at their respective voltage ratings. This fact serves to
limit the applications .of these devices ta low power direct
control or high power indirect cantral through the use of
higher power relays. Figure 1 shaws a block diagram of this
system.

Even though the areas of instrumentation and consumer
products have .provided.· great in,roads for the microprocessor, its utilization is still limited by the "real-world"
interfaces through which the microprocessor must
communicate.These interfaces must handle such things as
current and voltage levels which would be destructive t.othe
MOS circuitry contained within the IC package. The advent
of the solid-sta.te optically-isolated relay has lessened the
impact of these "real-world" interface,problems. It iswith
this in mind that this application nate will show haw ta
interface a microcomputer system (based upan Mostek's
MD-SERIES) to an OPTO-22 PB24 which is a 24-channel
110 panel utilizing,Opto 22's family .of solid-state relays.

Figure 1

".

L
MDX-CPU2

I
r

'I
~

)

J
MDX·PIO

IJl

:::J

'"
0

PB24

co
N

0
~

• • §J §]

IJl

LlNE----------~1-~~~---------*~--~1
OUTPUTS

VUI-1

INPUTS

•

HARDWARE CONSIDERATIONS
As mentioned above, this particular application will make
use of the MDX-PIO for the parallel interface between the
microcomputer and the opto panel. In order to utilize this
board the user must be aware of the many options available.
This particular board is based upon the Z80-P10 peripheral
chip. It is beyond the scope of this application note to go into
great detail about this chip. For those readers wishing to
gain more knowledge about this chip, please refer to the
Microcomputer Data Book.
1981

zao

For the type of operation that the opto panel is generally
used, the data is handled as discrete bits. With this in mind,
we will use the MDX-PIO in the bit-control mode. For more
detail on this board, consult the MDX-PIO Operations
Manual. When operating in this mode, the board can be
configured such that I/O bits are assigned in four bit groups;
all bits within a given group must be either inputs or
outputs. This comes about owing to the type of interface
chips used on the MDX-PIO. The user must be aware ofthis
when it comes time to configure the opto panel. Port bits are
assigned as either input or output by strapping the PIO
accordingly. Figure 2 summarizes the various I/O straps for
the PIO. The installation of a strap selects the corresponding
Figure 2
J3

PORTB
1/0 CONTROL
7

17
PORTA
1/0 CONTROL
23

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

-- ---

2

8
18

24

B2

BrrS4-7

B1

BrrSO-3

B2

BrrSO-3

B1

BITS4-7

A2

OUTPUT

A1

OUTPUT

A2

INPUT

A1

INPUT

bits as outputs unless.otherwise noted. Note that port B can
be strapped as two four bit quantities while port A l'!1ust be .
strapped as an eight bit qi.iantity. To improve flexibility, the
cable assignments in Tables 1 and 2 provide for the first 16:
channels to be assigned to Port B1 and B2. Channels '7 -24
are split between Port A' and A2. In order for the software
to use positive logic to activate the opto modules, the buffet
chips on the PIO should be the inverting type. For channel A,
74LS240 devices should be used and for channel B,
74LS242 devices shoukt be used.
The address assignment ofthe PIO is not critical owing to its
having "ported" .1/0 as opposed to "memory-mapped" 1/0.
For this application note; the sample software routine
expects the PIO to reside at 1/0 location SO hex. To
aCcomplish this assignment, simply strap the following pins
on J4: 3-4, 5-6, 7-8, and 9-' O.

SOFlWARE CONSIDERATIONS
There are two basic operation~ which are accomplished in
software: progra'mming the PIO and controlling the opto
panel. Figure 3 is a source listing for the demonstration
program. For detailsc6ncerning the programming of the
PIO, consulttheZSO-PIO section of the ZSO Microcomputer
Data Book. The software routine provided with this
application note runs the PIO as a polled device rather than
interrupt-driven. The assignment of I/O bits is dependent
upon the application. In this case, four bits are assigned as
inputs and four as outputs.
.
All that is necessary to proQram the PIO is the selection of bit
control mode and assignment of 1/0 bits. Once
programmed, the interraction between the application
software . and the physical devices which are being
controlled is simply a matter of doing 1/0 instructions to I/O
port SOH. A "'" in one of the input bits indicates that the
device has been turned on. One nice feature of the PIO is
that the software can read back the state of the output bits.
This feature provides for storage of the state of the output
bits.

VIII-2

A PARTIAL BASIC ROUTINE TO CONTROL THE OPTO PANEL
Figure 3

COMMENT: MASK CONTAINS THE 3 1/0 MASKS; PORT
FOR I = 1 T03
OUT (21 + 127),255

=BOH

OUT (21 + 127), MASK (I)
NEXT I

OUT PORT, DATA
A= INP(PORn

PINOUT ASSIGNMENTS
FROM P10-J1 TO PB24
Table 1
PIOPINOUT

J1-1
J1-2
J1-3
J1-4
J1-5
J1-6
J1-7
J1-8
J1-9
J1-10
J1-11
J1-12
J1-13
J1-14
J1-15
J1-16
J1-17
J1-18
J1-19
J1-20
J1-21
J1-22
J1-23
J1-24
J1-25
J1-26

PB24 PINOUT

ARDY
ASTB
A7
A5
A3
A1
BO
B2
B4
B6
BSTB
BRDY
N/C
GND
GND
A6
A4
A2
AO
B1
B3
B5
B7
GND
GND
N/C

VIII-3

9
13
47
43
39
35

CHANNEL 19
CHANNEL 17
CHANNEL 0
CHANNEL 2
CHANNEL 4
CHANNEL 6

11
15
45
41
37
33

CHANNEL 18
CHANNEL 16
CHANNEL 1
CHANNEL 3
CHANNEL 5
CHANNEL 7

PINOUT ASSIGNMENTS
FROM P10-J2 TO PB24
Table 2
PIO PINOUT

J2-1
J2-2
J2-3
J2-4
J2-5
J2-6
J2-7
J2-S
J2-9
J2-10
J2-11
J2-12
J2-13
J2-14
J2-15
J2-16
J2-17
J2-1S
J2-19
J2-20
J2-21
J2-22
J2-23
J2-24
J2-25
J2-26

PB24 PINOUT

ARDY
AST8
A7
A5
A3
A1
80
82
84
86
8ST8
8RDY

5
31
27
23
19

CHANNEL 23
CHANNEL 21
CHANNELS
CHANNEL 10
CHANNEL 12
CHANNEL 14

7
29
25
21
17

CHANNEL 22
CHANNEL 20
CHANNEL 9
CHANNEL 11
CHANNEL 13
CHANNEL 15

N/C

GND
GND
A6
A4
A2
AO
81
83
85
87
GND
GND
N/C

VIII-4

IJ

UNITED

COMPUTER
PRODUCTS
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TECHNOLOGIES
MOSTEK

MDX-RMC121MD-RMC12-50
APPLICATION NOTE #2
INTRODUCTION

CABLE ASSEMBLY

The MD-RMC12 is a subsystem enclosure for the
successful STD BUS line offered by Mostek and several
other vendors. The subsystem has a power supply, a fan, a
12-slot card cage, and is packaged in a 19-inch rackmountable frame.

Figure 2

PIN 1

(3)

This application brief will detail the components for the
cables that might be used and gives suggestions that might
help improve the product's value to the user.
CABLES
The rear liD panel was provided for the convenience of the
user. No cables are provided with the MD-RMC12 because
of the diverse needs of the end user, but here are some
recommended components and suggested cables to help
configure a system.
MDX-PIO. MDX-SI02. MDX-CPU2. and
MDX-EPROM/UART (DEBUG)
A typical interface cable from a Mostek module to the back
ofthe liD connector panel is described in the following text.
See Figure 1. The cable will be the interface for Mostek's
MDX-EPROM/UART module, MDX-PIO. MDX-CPU2 or
serial modules MDX-SIO, and MDX-SI02; however, the
cable will accommodate all of Mostek's modules that have a
26-pin header for the liD connector.

Ansley 609-2601-01, Winchester Electronic's #51-112601 or 3M's #3399-6026. The header is then pressed on the
cable. Pressing the header on the cable can be
accomplished with the manufacturer's suggested presses.
A bench vise, if used with care, can also be used. Note that
pin 1 ofthe header connector is the pin marked by the arrow
on the housing. See Figure 2.
2. 24 inches of 26-conductor flat-ribbon cable: T&B
Ansley's #171-26, Winchester Electronic's #55-262810/11 or 3M's #3365/26.
3. A 25-pin D-type socket connector, (T&B Ansley part
#609-25S, or Winchester Electronic's #49-1125S), should
be attached to the liD panel with the socket-jack assembly
with #4 lock washer and #4-40 hex nut. (T&B Ansley 609003 or Winchester Electronic's 49-603-S) or #4 screws and
nuts. The suggested method is the socket-jack assembly.

CABLE INTERFACE
Figure 1

RMC12 REAR 1/0 PANEL

o~oo~ooC

o~oo~ooC
o~oo~ooC

\

7

Note: This method provides direct one-to-one pinout of
MDX module signal wiring. Any scrambling which may be
required to suit a particular application should be done with
multi-conductor discrete wire; i.e. Beldon 8459 (25conductor; 22 AWG.)

The D connector has 25 pins, and the flat ribbon cable has
26 conductors; therefore, the cable needs to have the last
conductor (header pin 26) trimmed back approximately a
half-inch to allow for pressing. This conductor isn't used by
Mostek's liD modules. The D-type connector is then
pressed on the corrected end of the cable. making sure pin 1
of the D-type connector end matches pin 1 of the header
end. The liD panel position selected is uptothe user, but to
make it compatible with other Mostek MATRIX-80 systems, •
J3 is the suggested slot for the RS-232C (MDXEPROM/UART, SID, and SI02 modules) interconnect. The
printer position defined by Mostek is Jl and J2 is the PROM
programmer position.

1. The mating connector for the 26-pin header, on the liD
modules, is a mass-terminated type connector, like T&B

VIII-5

PRINTER. PROM PROGRAMMING
When a printer is going to be used with the RMC12
subsystem the interface cable will depend on what type of

interface the printer has: parallel Centronics type or RS-232
serial. type.
the parallel interface uses the MDX-PIO and an internal
cable described in the preceding text (Figure 2). The external
cable is detailed in Table 2.

of the PPG-8/16 with a 12-pin card-edge connector. There
are many sources for the connector but here is a list of a
few: AMP #583970-1 housing; #66067-5 contacts, and
Winchester Electonic #HCA6S. (See Figure 3)
THE WIRING LIST FOR THE POWER CONNECTOR
Table 1

When a serial interface is going to be used, a MDX-SIO or
MDX-SI02, the same internal cable as described in Figure 2
of the previous text is used. The external cable is the same
as the CRT cable discussed later in the text and is detailed in
Table 4.
The PPG 8/16 uses the MDX-PIO as the interface module
and as such will also use the same internal cables as the
previous paragraphs described. (Figure 2). The external
cable is detailed in Table 3. The software for the PPG 8/16
is provided with M/OS-80 and FLP-80DOS operating
systems.
The Mostek PROM programmer, PPG-8/16, will need a
power harness brought from an external source, like a lab
supply, or from the RMC12 itself. The PPG-8/16 requires
5 Vdc, and plus and minus 12 Vdc. The power can be taken
directly from the RMC12 power supply by soldering 24guage wire from the solder lugs on the power supply to the
connector. The power connector attaches to J2 on the back

Power Supply Connector Pin #
Vdc
(J2)
+12
+5
GND
-12

4,
1,
2,
6,

D, 5, E
A
B, 3, C
F

Color of Wire
(24 AWG)
Blue
Red
Black
,White

MDX-FLP. MDX-FLP2
When the user needs Floppy Disk capabilities, another
cable must be made. It interfaces Mostek's MDX-FLP
module to the 1/0 panel. Mostek has a disk drive subsystem
that contains two single-sided, single-density/doubledensity drives in a 19" rack-mount system called the
RMDFSS. The cable suggested below is designed to
interface the Mostek MDX-FLP Module to the rear 1/0
panel.

PPG/RMC 12 POWER CABLE
Figure 3

VIII-6

RS-232C DEVICE TO REAR PANEL

MDX-FLP MODULE TO THE REAR 1/0 PANEL
Figure 4

The cable used to connect to a terminal device is a one-toone 25-pin D connector (male). The Mostek cable can be
purchased from Mostek or it can be constructed from the
following components: Two 25-pin D-type pin connectors
and five or six feet of twenty-five conductor flat ribbon cable.

(AMC12 REAR liD PANEL)

MOX-FLP

MDX-FlP2

'~~ f::Li1

The twenty-six conductor cable could be used if the last
conductor is removed or trimmed back on both ends. The D
connectors are like the T&8 Ansley 609-25P. The cable is
like T&8 Ansley #609-25S, 26 conductor flat ribbon cable.
The connectors are crimped on both ends to complete the
cable.

l--\r------,
_----'I
\c-.

Materials for constructing the cable are listed below.

RMC12 TO RMDFSS CABLE

1. The MDX-FLP has a 50-pin header for I/O. The
connector, like the previous cable discussed, is a massterminated crimp-on type of connector. (T&8 Ansley part
#609-5001 M, Winchester Electronics #51-1150-01, or
3M' #3425-6050)
2. The cable is 50-conductor flat cable, 24 inches long.
(T&8 Ansley #171-50, Winchester Electronic #55-5028101-11 or 3M's #3320/50.)
3. The connector that is attached to the rear I/O panel is
also a mass-terminated connector. (T&8 Ansley #609-50F
or 3M #3489-1001)

EXTERNAL CABLES

When floppy disk-drive units are to be utilized with the
RMC12, Mostek can provide a complete disk-drive
subsystem, the RMDFSS. The RMDFSS is a rackmountable, dual-floppy subsystem with two single-sided,
single-density or double density drives with the power
supply and muffin fan also provided in the enclosure. The
disk drives are Shugart model number 800-2 drives and can
be connected via a mass-terminated fifty-conductor cable
from the rear of the I/O panel of the RMC12 and the rear of
the RMDFSS subsystem via an external fifty-pin male
connector (T&8 Ansley 609-50M) on both ends of 50conductor cable (T&8 Ansley #609-50F). See Figure 6.

RMDFSS SUBSYSTEM
Figure 6

The external cables needed to interface the RMC12 and its
complement boards will vary according to the user needs as
do the internal cables. Detailed here are a few common
cables.

EXTERNAL CABLING
Figure 5
RMC12 REAR PANEl

~,~
~oo~oo~o
~oo~oo~o

\'--______7

~\~

CRT DeVICE

MK78152
EXTERNAL CABLE

RS-232e

1::::::0.:: I:::=~:I

1==-"'-= 1=:..--=-1
!!11I1!!1/!11!!!!!!
'"!!!I'"'IIIIII

"IIIIII!!!!II!!II!

II
VIII-7

Table 2

Table 3

Wire list for a cable from the Mostek Parallel Interface
Module (112 MDX-PIO) to the rear I/O panel, and from the
I/O panel to a parallel printer (Centronics-compatible). See
MDX-PIO manual for board strapping instructions and
component changes.

26-Pin
PIO Header
Signal Conn.

ARDY
ASTB
AO
Al
A2
A3
A4
A5
A6
A7
BRDY
BSTB
BO
Bl
B2
B3
B4
B5
B6
B7
GND
GND
GND
GND

*
Jl-l
Jl-2
Jl-19
Jl-6
Jl-18
Jl-5
Jl-17
Jl-4
Jl-16
Jl-3
Jl-12
Jl-ll
Jl-7
Jl-20
Jl-8
Jl-21
Jl-9
Jl-22
Jl-l0
Jl-23
Jl-14
Jl-15
Jl-25
Jl-24

Wire list for a cable from a Mostek parallel interface module
(112 MDX-PIO) and a PROM programmer (pPG-8/16) to

the rear I/O cable. See the MDX-PIO manual for board
strapping instructions and component changes.

Centronics Centronics
Female Male Connector
Parallel
Socket Pin
Socket
Signals
**
Jl-l
Jl-2
Jl-19
Jl-6
Jl-18
Jl-5
Jl-17
Jl-4
Jl-16
Jl-3
Jl-12
Jl-ll
Jl-7
Jl-20
Jl-8
Jl -21
Jl-9
Jl-22
Jl-l0
Jl-23
Jl-14
Jl-15
Jl-25
Jl-24

***
****
Jl-l
Jl-2
Jl-19 2
Jl-6 3
Jl-18 4
Jl-5 5
Jl-17 6
Jl-4 7
Jl-168
Jl-3 9
Jl-12
Jl-ll 10
Jl-7 1
Jl-20
Jl-8
Jl-21
Jl-9 12
Jl-22 11
Jl-l0
Jl-23
Jl-14
Jl-15
Jl-25 19
Jl-24 20

rINTERNA~L
MASS TERMINATED
CABLE

PIO 26 Pin
Signal I/O

ARDY
ASTB
AO
Al
A2
A3
A4
A5
A6
A7
BRDY
BSTB
BO
Bl
B2
B3
B4
B5
B6
B7
GND
GND
GND
GND

DATA 1
DATA 2
DATA 3
DATA 4
DATA 5
DATA 6
DATA 7
DATA 8
ACKNLG
STROBE

PE
BUSY

GND
GND

(EXTERNAL)
DISCRETE CABLE

--1

*
J2-1
J2-2
J2-19
J2-6
J2-18
J2-5
J2-17
J2-4
J2-16
J2-3
J2-12
J2-11
J2-7
J2-20
J2-8
J2-21
J2-9
J2-22
J2-10
J2-23
J2-14
J2-15
J2-25
J2-24

Female Male
25 D-Panel
Connectors
Socket Pin
**
J2-1
J2-2
J2-19
J2-6
J2-18
J2-5
J2-17
J2-4
J2-16
J2-3
J2-12
J2-11
J2-7
J2-20
J2-8
J2-21
J2-9
J2-22
J2-10
J2-23
J2-14
J2-15
J2-25
J2-24

~INTERNA9)
MASS TERMINATED
CABLE

*26-pin header connector: T&B Ansley #609-2601-01
**25-pin D-type ribbon socket connector: T&B Ansley
609-25S******
***25-pin D-type discrete pin plug connector: Cinch (TRW)
#DBM-25P
****36-contact female connector: Cinch (TRW)
#57-403060*****
*****Housing for the above 25-pin connector: Cinch (TRW)
#DB-51226-1
******Pin 26 ofthe ribbon cable must betrimmed V,' before
crimping

***
J2-1
J2-2
J2-19
J2-6
J2-18
J2-5
J2-17
J2-4
J2-16
J2-3
J2-12
J2-11
J2-7
J2-20
J2-8
J2-21
J2-9
J2-22
J2-10
J2-23
J2-14
J2-15
J2-25
J2-24

PPG-8/16
25-Pin D PPGCon8/16
nector
Signal
Socket

****
J3-10
J3-1
J3-2
J3-3
J3-4
J3-5
J3-6
J3-7
J3-8

ASTB
PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7

J3-17
J3-20
J3-21
J3-11
J3-12
J3-13
J3-14
J3-15
J3-16
J3-22
J3-24
J3-25
J3-23

BSTB
PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7
GND
GND
GND
GND

(EXTERNAL)
-DISCRETE CABLE

I

~

*26-pin header connector: T&B Ansley #609-2601-01
**25-pin D-type ribbon socket connector: T&B Ansley
#609-25S******
***25-pin D-type discrete pin plug connector: Cinch (TRW)
#DBM-25P
****25-pin D-type discrete socket connector: Cinch (TRW)
#DBM-25S*****
*****Housing for the above 25-pin connectors; Cinch (TRW)
#DB-51226-1
******Pin 26 ofthe ribbon cable must betrimmed V,' before
crimping

VIII-8

Table 4

Notes for Table 4

Wire list defining the cable from the communications
modules, MDX-EPROM/UART, MDX-SIO, and MDX-SI02,
to the 1/0 panel and a communications device (i.e. Printer,
CRT Terminal, etc.). The strapping information for the
modules is detailed in the module operations manual.

SIOI
SI02
(J1orJ2) 26-Pin Female Male
EPROMI Header
UART Conn. Socket Pin
Signal

*
CHASSIS J3-1
GND
XMIT J3-2
DATA
RECV J3-3
DATA
REO TO J3-4
SEND
ClRTO J3-5
SEND
DATA SEl J3-6
RDY
GND J3-7
CARRIER J3-S
DETECT
J3-9
J3-10
J3-11
20mA- J3-12
RECV RET
20mA+ J3-13
SEND
J3-14
J3-15
READER J3-16
STEP(+)
J3-17
J3-1S
J3-19
DATA J3-20
TERM
RDY
READER J3-21
STEP(-)
J3-22
J3-23
20mA+ J3-24
RECV
20mA- J3-25
SEND

~

***
J3-1

***
J3-1

J3-2

J3-2

J3-2

J3-3

J3-3

J3-3

J3-4

J3-4

J3-4

J3-5

J3-5

J3-5

J3-6

J3-6

J3-6

J3-7
J3-S

J3-7
J3-S

J3-7
J3-S

J3-9
J3-9
J3-9
J3-10 J3-10 J3-10
J3-11 J3-11 J3-11
J3-12 J3-12 J3-12
J3-13

J3-13

J3-13

J3-14
J3-15
J3-16

J3-14
J3-15
J3-16

J3-14
J3-15
J3-16

J3-17
J3-18
J3-19
J3-20

J3-17
J3-1S
J3-19
J3-20

J3-17
J3-18
J3-19
J3-20

J3-21

J3-21

J3-21

J3-22
J3-23
J3-24

J3-22
J3-23
J3-24

J3-22
J3-23
J3-24

+

J3-25

(INTERNAL)
MASS TERMINATED
CABLE

MOSTEK PRODUCTS ORDERING INFORMATION

25-Pin D
Printer or
Connector
RS-232C
Device
Socket

**
J3-1

J3-25

J3-25

*26-pin header connector: T&B Ansley #609-2601-01
**25-pin D-type ribbon socket connector: T&B Ansley
609-25S****
***25-Pin D-type ribbon pin plug connector: T&B Ansley
609-25P
****Pin 26 of the ribbon cable must be trimmed V>" before
crimping

DESCRIPTION

MOSTEK #

NOTES

PROM Programmer
PPG-S/16

MK79081-1

Cable included

PPG-81 16 cable only

MK79090

Power not
provided

PIO to PPG
Cable

MK77957

Power not
provided

Centronics cable only

MK79089

used with
scrambler

CRT cable only

MK78152

MDX-PIO-parallel 1/0
MDX-PI0-44 MHz

MK77650
MK77650-4

STD-Z80
Module

20mASEND RET
20mA+
RECV

MDX-SIO
MDX-SIO-4

MK77651
MK77651-4

STD-Z80
Module

MDX-SI02
MDX-SI02-4

MK77670
MK77670-4

STD-Z80
Module

READER
STEP(+)

MDX-FlP

MK77654

STD-SO
Module

MDX-EPROM/UART
MDX-EPROM/UART

MK77753
MK77753-4

STD-Z80
Module

RMDFSS 115/220 V
50/60 Hz

MK78183
MK78185

Cable
provided

RMDFSS cable only

MK79088

CHASSIS
GND
XMIT
DATA
RECV
DATA
REO TO
SEND
ClRTO
SEND
DASET
RDY
GND
CARRIER
DETECT

DATA
TERM
RDY
READER
STEP(-)

20mA+
SEND
20mARECV

(EXTERNAL)
MASS TERMINATED
CABLE

-1
VIII-9

II

VIII-l0

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DEVELOPMENT
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TECHNOLOGIES
MOSTEK

RESET CIRCUIT
FOR MDX-CPU2A
This application brief will detail the differences and the
reason for the differences between the MDX-CPU2 and the
MDX-CPU2A CPU cards.

The change allows the /SYSRESET to be sourced by
another card other than the CPU card (i.e. MDX-PFD). See
Figures 1 and 2 for changes. Refertothe MDX-PFD manual
for specifics on the power-fail detect usage.

The difference between the two cards is in the way
/SYSRESET is handled. The actual change is limited to a
simple Printed Circuit Board change on the CPU card.

The changes do not affect the parts count or the option
strapping headers.

RESET CIRCUIT FOR CPU2

RESET CIRCUIT FOR CPU2A

Figure 1

Figure 2

PBRESEf

2

B

PBRESET

U17
MK3aaO
zao CPU

Q

U4

2

B

Q

U17
MK3aaO
zao CPU

13

U4
4

26

26

RESET

-

+5
·5

UR2
1K
12
SYSRESET

U27

U27
.IT

a

a

74LS244

SYSRESET

VIII-11

13
~

74LS244

RESET

VIII·12

IJ

UNITED

COMPUTER
PRODUCTS
DIVISION

TECHNOLOGIES

MOSTEK

APPLICATION NOTE #4
RESET CIRCUIT FOR MDX-CPU1A
This application note will detail the difference and the
reason for the difference between the MDX-CPU1 and the
MDX-CPU1A CPU cards. The difference between the two
cards is in the way ISYSRESET is handled. The actual
change required the addition of an IC and a change to the
Printed Circuit Board.
These changes allow the ISYSRESET to be sourced by a
card other than the CPU card (i.e. MDX-PFD). See Figures 1
and 2 for the affected circuitry.

For specifics on how to use the power-fail detect card, refer
to the MDX-PFD Operations Manual.
The addition of the IC provided the opportunity to bring the
nomenclature screen up to date with the present practices
in labeling headers and parts. These changes affect the
parts count, nomenclature screen, and the option-strapping
headers. Tables 1 and 2 will point out the changes in the
option-headers and the parts designators.

OPTION HEADERS
Table 1

Old Designator

New Designator

U5
U10
E3,E4
E5,E6
E1,E2
E7

Comments
number scheme changed
number scheme changed
Pins 1 and 3 of J2
Pins 4 and 2 of J2
No functional change
No functional change.

J3
J4
J2
J2
J5
J6

Option-header Jumpers
From (CPU1)
US/U10

o
o

016

To (CPU1A)
J3/J4
10 o 2

o

0

~14
4

7

0

Memory and 1/0 Expand jumper options

~6

I
I

0

0

0

0

0

0

0

0

0

0

0

0

80

0

To (CPU1A)
J6

]1

0

0

9

From (CPU1)
E7

M

E
o M

I
I

M
E

o M

•

150 016

Example:
US 4 to 14 = J3 7 to 6

VIII-13

Wait State Jumper Options (I/O and Memory)
From (CPU1)

To (CPU1A)

E5
0

(I/O)
1)

E6

D D D EJ
E40
(Memory)
E30

+
+

1

2

3

4

0-0 (Memory)
0-0 (I/O)

PARTS DESIGNATORS
Table 2

CPU1 Designator
U1
U11
U12
U13
U14
U15
U17
U18
U2,16
U20
U21
U22,25,27
U23
U24
U26
U28
U29
U3
U4
U8
U9,19
UR1, UR2
UR3
UR4
X14
X15
X23
X6,X7
C2
C3-5, 7-13,15
C6,14
CR1
Q1
R12,13
R3,5,8,11
R4, 10
R6
R7
R9

PART
74S04
74LS14
74LS138
74LS04
MK3882
MK3880
74LS165
74LS393
74LS74·
74LS32
74LS02
74LS244
35392
74LS245
74LS373
74LS08
OSC.5/8MHz
74LSOO
74LS10
74S74
74LS30
1K RES,SIP 6 PIN
22K RES,SIP 6 PIN
1K RES,SIP 8 PIN
28 PIN SOCKET
40 PIN SOCKET
22 PIN SOCKET
24 PIN SOCKET
CAP. 33PF
CAP .. 1UF
CAP. 15UF
DIODE IN914
TRANSISTOR 2N3906
RES. 4.7K OHMS
RES. 1.1 K OHMS
RES. 270 OHMS
RES. 10K OHMS
RES. 22 OHMS
RES. 510 OHMS

VIII-14

CPU1 A Designator
U1
U9
U10
U11
U12
U13
U17
U15
U2,14
U19
U20
U21,24,26
U22
U23
U25
U27
Y1
U3
U4
U7
U8,18
UR1, UR2
UR3
UR4
X12
X13
X22
X5,X6
C1
C2-3, C5-19
C4,C20
CR1
Q1
R2,5
R3,4,6,9
R1
R7
R8
R10

RESET CIRCUIT FOR CPU1

RESET CIRCUIT FOR CPU1A

Figure 1

Figure 2

+6
+6

SYSRESET

UR2
1K
5

U13
MK3880
Z80CPU
U22

SYSRESET

U13
MK3880
zao CPU

UR2
1K

U22
15

1-"15'--....___2Q
6 RESET

5

26 _ _

>=-'--Q RESET

74LS244

74LS244

10
74LS02

• IC ADDED TO BOARD

II
VIII-15

VHI-16

I!I

UNITED

COMPUTER
PRODUCTS
DIVISION

TECHNOLOGIES
MOSTEK

APPLICATION NOTE #5
CUSTOMIZING THE MDX-CPU3 PROM
.. ----,,-, .",.., .. _--.,,_ ..._,,------SCOPE:

CUSTOMIZING U24 (MK6359):

This application note will detail how to customize the two
PROM's (U23 and U24) on the MDX-CPU3.

U24 is a bipolar PROM programmed at the factory (part
number MK6359) to provide several functions for the MDXCPU3, First, it provides the chip select signal to the
EPROM/ROM socket; Second, it provides the A 15 address
line to select upper or lower 32K memory for on-board
dynamic memory; Third, it provides the RAM select (RSEL)
signal (on-board vs off-board) for an input to the PAL; And
fourth, it provides the memory expand (MEMEX) signal for
use in bank selecting of additional off-board memory.

CUSTOMIZING U23 (MK6360):
This bipolar PROM performs several functions. First, it
provides the address decoding for the chip select signal to
the Serial Timer Interrupt device (MK3801); Second, it
provides the clocking pulse for the parallel output latch;
Third, it provides the clocking signal pulse for the memory
configuration latch; And fourth, it provides the input to the
Programmable Array Logic (PAL) device indicating that an
onboard port is being addressed.
The data contained in the bipolar PROM provided on the
MDX-CPU3 is listed at the end of this application note. If a
change is required (such as using a different address other
than BO-BF for the serial port or DO for the printer output
port), anew bipolar PROM must be programmed. See Table
1 for the information needed to compute the correct data for
your PROM.
BIPOLAR PROM OUTPUT-PIN AND DATA BIT
DEFINITION

Tre data contained in the bipolar function PROM provided
o~"the MDX-CPU3 is listed at the end of this application
note. If a change is required (such as using memory maps
other than those provided), a new bipolar PROM must be
programmed. See Table 2 for the information needed to
compute the correct data for your PROM.
BIPOLAR PROM OUTPUT-PIN AND DATA BIT
DEFINITION
Table 2
OUTPUT
PIN #
12
11

Table 1
OUTPUT
PIN#
12
11
10

9

PROM DATA BIT SIGNAL
1
3
2
0 DESCRIPTION

-

X

-

-

X

X
-

-

-

X
-

-

STI Chip Select (MK3801 )
Output Latch Select (PTR)
Memory Config Select
Any Port Select (PAL input)

PROM DATA BIT SIGNAL
1
0 DESCRIPTION
3
2

10
9

ACTIVE
STATE
HI
HI
HI

X
X
X

-

X EPROM/ROM Select
A 15 Address Line
Select On-board RAM
Memory Expand Output

ACTIVE
STATE
LO

*.

LO
LO

** = Tracks A 15 input line, on shipped PROM. Potential use
of this feature could be to have two separate 32K RAM
memory banks on-board when using a MK38000 ROM
(32Kx8.)

LO

For example', if a user wishes to have the STI port at 10-1 F
instead of BO-BF, the data in the remaining location 10-1 F
would be 1 H (0001), The data in the remaining locations cif
the PROM must also be computed and programmed.

The 64K memory map is shown in Figure 1. Note that each
PROM location represents a 2K block of CPU addressable
memory. The PROM location for the MAP 0 is depicted in
Figure 1.

NOTE: Depending on the bits being changed and the type
of unprogrammed bit (unprogrammed bit'" 1 or 0) of the
PROM, if may be possible to use the existing PROM.

VIII-17

MEMORY MAP Sti0WING PROM ADDRESS
LOCATIONS
Figure 1
CPU Address Change
F800 - FFFF
Fooo - F7FF
E800 - EFFF
Eooo - E7FF
0800 - OFFF
0000 - 07FF
C800 - CFFF
Cooo - C7FF
B800 - BFFF
Booo - B7FF
ABOO -AFFF
Aooo -A7FF
9800 - 9FFF
9000 - 97FF
8800 - 8FFF
8000 - 87FF
7800 -7FFF
7000 -77FF
6800 - 6FFF
6000 - 67FF
5800 - 5FFF
5000 - 57FF
4800 -4FFF
4000 - 47FF
3800 - 3FFF
3000 - 37FF
2800 - 2FFF
2000 - 27FF
1800 -1 FFF
1000 -17FF
0800 - OFFF
0000 - 07FF

PROM LOCATIONS AND PROM DATA BIT
INFORMATION
Figure 2

1F
OF
1E
.OE
10
00
1C.
OC
1B
OB
1A
OA
19
09
18
08
17
07
16

06
15
05
14

04
13
03
12
02
11
01
10
00

CROSS REFERENCE
CPU Address Bus to Prom Address Bus
Figure 3

PROM
LOC

BIT #
3210

DATA

OOOOH
1000H
2000H
3000H
4000H
5000H
6000H
7000H
BOOOH
9000H
AoooH
BoooH
CoooH
OoooH
EoooH
FoooH

OOH
01H
02H
03H
O4H
05H
06H
07H
08H
09H
OAH
OBH
OCH
OOH
OEH
OFH

1100
1001
1001
1001
.1001
1001
1001
1001
1011
1011
1011
1011
1011
1011
1011
1011

CH
9H
9H
9H
9H
9H
9H
9H
BH
BH
BH
BH
BH
BH
BH
BH

0800H
1800H
2800H
3800H
4800H
5800H
6800H
7800H
8800H
9800H
A800H
B800H
C800H
0800H
E800H
F800H

10H
11 H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
10H
1EH
1FH

1001
1001
1001
1001
1001
1001
1001 .
1001
1011
1011
1011
1011
1011
1011
1011
1011

9H
9H
9H
9H.
9H
9H
9H
9H
BH
BH
BH
BH
BH
BH
BH
BH

MEMORY
MAP

PROM Address

NOTE: A contiguous addressing of memory does not
enable sequential PROM address locations.

U24
A7

PROM

AS
A5
All

A4

A1S

A3

A14

A2

A13

Al

A12

AO

A3 - AO = lOWER NIBBLE

EXAMPLE

OF PROM ADDR ESS

To truely understand the memory mapping PROM (U24).
.the following examples are given.
Eample #1 - You have a 2K EPROM (2716) that you would
like to place in the memory map (Map 0) at location OOOOH.
Refer to Table 2. Bit 0 must be enabled (0 =active low) and
the remaining three Bits selected accordingly. The PROM
location to be programmed Would be OOH. See Figure 2.

VIII-18

Example #2 - You have a 2K EPROM (2716)thatyou would
like to place in the memory map (Map 0) at location E8ooH.
Refer to Table 2. Bit 0 must be enabled (0 = active low) and
the remaining three Bits selected accordingly. The PROM
location to be programmed would be 1 EH. See Figure 3.

Figure 4 (cant.)

0800H
1800H
2800H
3800H
4800H
5800H
6800H
7800H
8800H
9800H
A800H
B800H
C800H
D800H
E800H
F800H

Example #3 - You have a 4K EPROM (2732)thatyou would
like to place in the memory map (Map 0) at location OOOOH.
Refer to Table 2. Bit 0 must be enabled (0 = active low) and
the remaining three Bits selected accordingly. The PROM
locations to be programmed would be ooH and 10H.
Example #4 - You have a 4K EPROM (2732)that you would
like to place in the memory map (Map 0) at location 28ooH.
Refer to Table 2. Bit 0 must be enabled (0 = active low) and
the remaining three Bits selected accordingly. The PROM
locations to be programmed would be 12H and 03H.
Example #5 - You have a 8K EPROM (2764) that you would
like to place in the memory map (Map 0) at location OOOOH.
Refer to Table 2. Bit 0 must be enabled (0 = active low) and
the remaining three Bits selected accordingly. The PROM
locations to be programmed would be ooH, 1OH, and 11 H.

Figure 5

Figure 4

OOOOH
1000H
2000H
3000H
4000H
5000H
6000H
7000H
8000H
9000H
AOOOH
BOOOH
COOOH
DOOOH
EOOOH
FOOOH

ooH
01H
02H
03H
04H
05H
06H
07H
08H
09H
OAH
OBH
OCH
ODH
OEH
OFH

BIT #
3210
PROGRAMMED
(BINARY)
DATA (HEX)
1100
1100
1100
1100
1100
1100
1100
1100
1011
1011
1011
1011
1011
1011
1011
1011

CH
CH
CH
CH
CH
CH
CH
CH
BH
BH
BH
BH
BH
BH
BH
BH

MAP 1 FOR EXAMPLE 6

MAP 0 FOR EXAMPLE 6

PROM
LOe

1100
1100
1100
1100
1100
1100
1100
1100
1011
1011
1011
1011
1011
1011
1011
1011

Programmed data is a HEX value arrived at by using
information from Table 2.

Example #6 - You have a 32K ROM (MK38000) that you
would like to place in the memory map (Map 0) at location
OOOOH. You would also like to take full advantage of having
64K Dynamic memory on the MDX-CPU3 board. i.e., you
would like to have one memory map use one half of memory
with the same 32K ROM. Thus, you essentially would have
a 32K ROM system with 64K of Dynamic RAM on the same
board. By installing jumper J5, the 02 input to U13 is no
longer tied high and will follow the logic level represented
by the 02 bit. Also, sincetheA15 address line is selected by
the bipolar PROM, the A15 line is enabled to select the
lower half of RAM for Map 0 and upper half of RAM for Map
1 as shown in Figures 4 and 5.

MEMORY
MAP

10H
11 H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH

CH
CH
CH
CH
CH
CH
CH
CH
BH
BH
BH
BH
BH
BH
BH
BH

VIII-19

BIT #
3210
PROGRAMMED
(BINARY)
DATA (HEX)

MEMORY
MAP

PROM
LOe

OOOOH
1000H
2000H
3000H
4000H
5000H
6000H
7000H
8000H
9000H
AOOOH
BOOOH
COOOH
DOOOH
EOOOH
FOOOH

20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH

1100
1100
1100
1100
1100
1100
1100
1100
1001
1001
1001
1001
1001
1001
1001
1001

CH
CH
CH
CH
CH
CH
CH
CH
9H
9H
9H
9H
9H
9H
9H
9H

0800H
1800H
2800H
3800H
4800H
5800H
6800H
7800H
8800H
9800H
A800H
B800H
C800H
D800H
E800H
F800H

30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH

1100
1100
1100
1100
1100
1100
1100
1100
1001
1001
1001
1001
1001
1001
1001
1001

CH
CH
CH
CH
CH
CH
CH
CH
9H
9H
9H
9H
9H
9H
9H
9H

I
I

Ii

Il

BANK SWITCHING
An application may require morethan one bank of memory.
The MDX-CPU3 board supports bank switching by
addressing the control port FF and sending it the bank
number the user wishes to select. However, bank numbers
and memory map numbers are not one and the same. See
Tables 3A and 3B.
BANK SWITCHING WITH JUMPER J5 INSTALLED
Table3A
DATA
WRITTEN
TO PORT FF

TO
SELECT
BANK#

AND
SELECT
MAP#

15

RESET (00)
00
01
02
04
08
10
20
40
80

0
0
1
2
3
4
5
6
7
8

0
0
1
2
4
0
0
0
0
0

0
0
0
0
0
0
0
0
0
1

ADDRESS BIT
14 13 12 11
0
0
0
0
0
0
0
0
1
0

0
0
0
0
0
0
0
1
0
0

0
0
0
0
0
0
1
0
0
0

02

0
0
0
0
0
1
0
0
0
0

0
0
0
0
1
0
0
0
0
0

ADDRESS BIT
14 13 12 11

02

PROM BIT
01
DO
0
0
0
1
0
0
0
0
0
0

0
0
1
0

0
0
0
0
0
0

BANK SWITCHING WITH JUMPER J5 NOT INSTALLED (BIT 02 REMAINS HIGH FOR PROM)
Table3B
DATA
WRITTEN
TO PORT FF

TO
SELECT
BANK#

AND
SELECT
MAP#

15

RESET (00)

0
0
1
2
3
4
5
6
7
8

0
4
5
6
4
4
4
4
4
4

0
0
0
0
0
0
0
0
0
1

00

01
02
04
08
10
20
40
80

0
0
0
0
0
0
0
0
1
0

0
0
0
0
0
0
0
1
0
0

0
0
0
0
0
0
1
0
0
0

0
0
0
0
0
1
0
0
0
0

0

*

PROM BIT
01
DO
0
0
0
1
0
0
0
0
0
0

0
0
1
0
0
0
0
0
0
0

* = 1 for Memory Decode PROM

o for Data off-board

EXPANDING THE NUMBER OF MEMORY MAPS

PAL PIN DEFINITIONS:

The devices shipped and discussed above will allow a
maximum of 8 maps. However, should a user require more
maps and not need to follow Mostek's bank selecting
scheme, 16 maps are possible. The user can place a MMI6306 (512 x 4) bipolar PROM (with users' programmed
data) in socket U24; Lift pin U24-14 and connect a wire
wrap wire from it to U13-1 0 and insert jumper J5. Now the
user will have access to a total of 16 memory maps
available.

Listed in Table 4 are the Boolean expressions for the PAL
logic. These are listed to help the user know which signals
are affected when changes are made to either of the two
PROMs mentioned earlier.

VIII-20

- - - - ,.

,-,"

,,-,---------------------------------

PAL OUTPUT-PIN SIGNAL DESCRIPTION
Table 4

OUTPUT
PIN#

SIGNAL

DESCRIPTION

CASSOFF =
=
EN ROM
=
INTAK
IWRTLTH =
IMCYCLE =
10ATAIN =

RFSH + IORO + EPSEL*RO +/RSEL*/EPSEL
RO*MREO
M1*IORO
IIORO + IWR +/PORTSEL
1M REO +/RFSH*IWR*/RO
RO*MREO*RSEL + RO*MREO*EPSEL
+ RO*IORO*PORTSEL
+ M1 *IORO* IIEI*IEO
+ IBUSAK* IRO*MREO
+ IBUSAK*1M 1* IIORO* IMREO
+ IBUSAK* IRO*IORO* IM1

16
17
19
12
15
18

PROM PATTERN (MM16301-1J 256 x 4)
U23 MK6360
LOC DATA LOC DATA LOC DATA LOC DATA LOC DATA LOC DATA LOC DATA LOC DATA

00
01
02
03
04
05
06
07

8
8
8
8
8
8
8
8

20
21
22
23
24
25
26
27

8
8
8
8
8
8
8
8

40
41
42
43
44
45
46
47

8
8
8
8
8
8
8
8

60
61
62
63
64
65
66
67

8
8
8
8
8
8
8
8

08
09
OA
OB
OC
00
OE
OF

8
8
8
8
8
8
8
8

28
29
2A
28
2C
20
2E
2F

8
8
8
8
8
8
8
8

48
49
4A
4B
4C
40
4E
4F

8
8
8
8
8
8
8
8

68
69
6A
6B
6C
60
6E
6F

10
11
12
13
14
15
16
17

8
8
8
8
8
8
8
8

30
31
32
33
34
35
36
37

8
8
8
8
8
8
8
8

50
51
52
53
54
55
56
57

8
8
8
8
8
8
8
8

18
19
1A
1B
1C
10
1E
1F

8
8
8

38
39
3A
3B
3C
30
3E
3F

8
8
8
8

58
59
5A
5B
5C
50
5E
5F

8
8
8
8
8

NOTE:

8
8
8

8
8

8
8
8
8

8
8
8

85
86
87

8
8
8
8
8
8
8
8

AO
A1
A2
A3
A4
A5
A6
A7

8
8
8
8
8
8
8
8

CO
C1
C2
C3
C4
C5
C6
C7

8
8
8
8
8
8
8
8

EO
E1
E2
E3
E4
E5
E6
E7

8
8
8
8
8
8
8
8

8
8
8
8
8
8
8
8

88
89
8A
8B
8C
80
8E
8F

8
8
8
8
8
8
8
8

A8
A9

AA
AB
AC
AO
AE
AF

8
8
8
8
8
8
8
8

C8
C9
CA
CB
CC
CO
CE
CF

8
8
8
8
8
8
8
8

E8
E9
EA
EB
EC
EO
EE
EF

8
8
8
8
8
8
8
8

70
71
72
73
74
75
76
77

8
8
8
8
8
8
8
8

90
91
92
93
94
95
96
97

8
8
8
8
8
8
8
8

BO
B1
B2
B3
B4
B5
B6
B7

00
01
02
03
04
05
06
07

2
8
8
8
8
8
8
8

FO
F1
F2
F3
F4
F5
F6
F7

B
8
8
8
8
8
8
8

78
79
7A
7B
7C
70
7E
7F

8
8
8
8
8

98
99
9A
9B
9C
90
9E
9F

8
8
8

B8
B9
BA
BB
BC
BO
BE
BF

08
09
OA
OB
OC
00
OE
OF

8
8

F8
F9
FA
FB
FC
FO
FE
FF

8
8
8
8
8
8

8
8
8

80
81
82
83

84

Oata is in HEX
VIII-21

8
8
8
8
8

8
8
8
8
8
8

8
4

II

PROM PATIERN (MMI6301-1J 256 x 4)
U24 MK6359
LOC DATA LOC DATA LOC DATA LOC DATA LOC DATA LOC DATA LOC DATA LOC DATA
20
21
22
23
24
25
26
27

F
F
F
F
F
F
F
F

40
41
42
43

05
06
07

C
9
9
9
9
9
9
9

08
09
OA
08
OC
00
OE
OF

8
8
8
8
8
8
A
8

28
29
2A
28
2C
20
2E
2F

10
11
12
13
14
15
16
17

C
9
9
9
9
9
9
9

18
19
1A
18
1C
10
1E
1F

8
8
8
8
8
8
A
8

00

01
02
03
04

45
46
47

F
F
F
F
F
F
F
F

60
61
62
63
64
65
66
67

F
F
F
F
F
F
F
F

80
81
82
83
84
85
86
87

0
0
0
0
0
0
0
0

AO
A1
A2
A3
A4
A5
A6
A7

9
9
9
9
9
9
9
9

CO
C1
C2
C3
C4
C5
C6
C7

0
0
0
0
0
0
0
0

EO
E1
E2
E3
E4
E5
E6
E7

F
F
F
F
F
F
F
F

F
F
F
F
F
F
F
F

48
49
4A
48
4C
40
4E
4F

F
F
F
F
F
F
F
F

68
69
6A
68
6C
60
6E
6F

F
F
F
F
F
F
F
F

88
89
8A
88
8C
80
8E
8F

F
F
F
F
F
F
8
8

A8
A9

C8
C9
CA
C8
CC
CO
CE
CF

F
F
F
F
F
F
8
8

E8
E9

A8
AC
AD
AE
AF

8
8
8
8
8
8
8
8

E8
EC
ED
EE
EF

F
F
F
F
F
F
F
F

30
31
32
33
34
35
36
37

F
F
F
F
F
F
F
F

50
51
52
53
54
55
56
57

F
F
F
F
F
F
F
F

70
71

77

F
F
F
F
F
F
F
F

90
91
92
93
94
95
96
97

0
0
0
0
0
0
0
0

80
81
82
83
84
85
86
87

9
9
9
9
9
9
9
9

DO
01
02
03
04
05
06
07

0
0
0
0
0
0
0
0

FO
F1
F2
F3
F4
F5
F6
F7

F
F
F
F
F
F
F
F

38
39
3A
38
3C
3D
3E
3F

F
F
F
F
F
F
F
F

58
59
5A
58
5C
50
5E
5F

F
F
F
F
F
F
F
F

78
79
7A
78
7C
70
7E
7F

F
F
F
F
F
F
F
F

98
99
9A
98
9C
90
9E
9F

F
F
F
F
F
F
8
8

88
89
8A
88
8C
80
8E
8F

8
8
8
8
8
8
8
8

08
09
OA
08
DC
DO
DE
OF

F
F
F
F
F
F
8
8

F8
F9
FA
F8
FC

F
F
F
F
F
F
F
F

44

72

73
74
75
76

NOTE: Data is in HEX

VIII-22

AA

EA

FD

FE
FF

COMPUTER
PRODUCTS
DIVISION

UNITED

~ TECHNOLOGIES
MOSTEK

UPGRADING FROM MDX-FLP1 TO MDX-FLP2
APPLICATION NOTE #6
INTRODUCTION
With the advent of the MDX-FLP2, Mostek STD-ZSO BUS
systems have the capability of maintaining up to 4 MB of
floppy storage on-line. In orderfor this benefitto be realized,
the appropriate hardware and software products need to be
brought together. This application note will detail the
required software (M/OS-SO) and hardware configurations
necessary in order to make use of the above-mentioned
benefit. The information contained herein is sufficient to
make the transition from a FLP1-based system to a FLP2based system. It is assumed that the system contains a CPU
card (CPU 1, 2, 3, etc.), sufficient memory to meet the
operating system's needs, and at least a console interface
(510, 5102, EPROM/UART, etc.). Additional information
may be gained from the M/OS-SO operations manual, the
MDX-FLP2 data sheetltechnical manual, and the MOSGEN
operations manual. (See references.)

memory sockets. As shipped from the factory, the default
floppy controller in a phantom system is the MDX-FLP2. So,
in most cases there will not need to be a migration path for
MDX-FLP1 to MDX-FLP2 in phantom systems. There are,
however, driver routines provided in the MOSGEN package
which will allow the use of an MDX-FLP1 in a phantom
system. Table 1 summarizes the various combinations of
software and hardware which Mostek offers.
When utilizing the double-density capabilities of the MDXFLP2 in a non-phantom system, the user must be aware of
the requirement for tracks one and two to be formatted as
single density. This is a requirement of the DCF EPROMs.
The technique for generating a double-density operating
system diskette in a non-phantom system is as follows:
1. Format the whole diskette as single density.
2. WRTSYS the diskette from a single-density source.

SOFTWARE
A system which is currently running M/OS-SO in
conjunction with an MDX-FLP1 should have FLP1-DCF
EPROM# MK62S6 and one of several DDT EPROMs for the
console and printer interfaces. There is no need to change
the DDT EPROM when upgrading to an MDX-FLP2. The
correct EPROM for an MDX-FLP2 system is FLP2-DCF
EPROM #MK6340. Of course these EPROMs only apply to
those M/OS-SO versions which are designed to run as
non-phantom systems. Any version of M/OS-SO which is
less than 5.0 is non-phantom.
Mostek uses the term "phantom" to indicate those systems
in which the boot firmware is non-resident. In addition, the
disk drivers are brought in as part of the operating system
rather than being EPROM-resident. This gives greater
flexibility to the system due to the increased space for
software on a disk versus permanent EPROM storage in the
system memory space. Through the use of a phantom
system, only a bare bones disk driver need be resident
during the boot phase. This driver determines the
appropriate software routines which need to be loaded for a
given hardware configuration. After this decision has been
made, the boot firmware is phantomed out of the system
memory space, thus freeing up additional memory.

3. Go back into the format program and reformat the
diskette beginning at track 2 as double-density.
After having completed the above procedure, the diskette
can now be filled with data from other sources. The file area
will have data stored in a double-density format while the
system area will have data stored in a single-densityformat.
The above procedure isn't necessary for a phantom system
due to its ability to determine which floppy controller device
is in the system and in what format the data is stored on the
diskette.

HARDWARE
As shipped from the factory, the MDX-FLP2 is strapped
correctly for operation with either M/OS-SO or FLP-SODOS
and S inch drives. It is still a good idea to verify that the
appropriate straps are in place. Figure 1 shows a board
outline of the MDX-FLP2 and the placement of the jumper
headers. Figure 1 also shows the correct strapping for the
MDX-FLP2 as it is shipped from the factory. The following
discussion details the operation of each strap on the
MDX-FLP2.
J4:

Versions 5.0 or greater are designed to run as phantom
systems and require a special "boot" EPROM. These
systems are, in general, designed to utilize the MDX-CPU3
and MDX-CPU4 due to their ability to phantom certain

VIII-23

Auto Precomp - When open, double density write
precompensation is always in effect (provided
DDEN* is low). This is primarily for 5'.14 inch drives
that require write precompensation of every track.
When strapped, write data is precompensated only
for tracks greater than 43; (factory setting)

•

MIOS 80 CONFIGURATIONS
Table 1

CPU

Configuration

FileName

Memory(K)

CPU MHz O/S

Peripheral Devices

PROMs

Size

Console

Printer

Floppy

Hard Disk

DDT/DCF
DDT/DCF
DDT/DCF
DDTlDCF
DDT/DCF
DDT/DCF
DDT/DCF
DDTlDCF

32
48
56
64
32
48
56
64

ALLCONI
ALLCONI
ALLCONI
ALLCONI
ALLCONI
ALLCONI
ALLCONI
ALLCONI

PIOLST
PIOLST
PIOLST
PIOLST
SIOLST
SIOLST
SIOLST
SIOLST

FLPI [EO,SBO,50,4D,A:,SDB,SDO]
FLPI [EO,8BO,50,4D,A:,SD8,SDO]
FLPI [EO,SBO,50,4D,A:,SDB,SDO]
FLPI [EO,SBO,50,4D,A:,SDB,SDO]
FLP1[EO,8BO,50,4D,A:,SD8,SDO]
FLPI [EO,SBO,50,4D,A:,SDB,SDO]
FLPI [EO,8BO,50,4D,A:,SDB,SDO]
FLPI [EO,SBO,50,4D,A:,SDB,SDO]

NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE

DDT/DCF
DDT/DCF
DDT/DCF
PHANTOM
DDT/DCF
PHANTOM

64
64
64

ALLCONI
ALLCONI
ALLCONI

PIOLST
SIOLST
PIOLST

NONE
NONE
NONE

64

ALLCONI

SIOLST

FLPI [EO,8BO,50,4D,A:,SD8,SDO]
FLPI [EO,SBO,50,4D,A:,SDB,SDO]
FLP2[EO,SBO,50,4D,A:,SDB,DDO]
FLP2[EO,SBO,5BO,4D,A:,DDB,DDO]
FLP2[EO,SBO,50,4D,A:,SDB,DDO]
FLP2[EO,SBO,5S0,4D,A:,DDB,DDO]

64
64
64
64
64

ALLCON2
ALLCON2
ALLCON2
ALLCON2
ALLCON2

ALLST
SIOLST
ALLLST
SIOLST
ALLLST

FLP2[EO,SBO,5S0,4D,A:,DDB,DDO]
FLP2[EO,SBO,5BO,4D,A:,DDB,DDO]
FLP2[EO,8BO,5BO,2D,A:,DDB,DDO]
FLP2[EO,SBO,5BO,2D,A:,DDB,DDO]
FLP2[EO,SBO,3BO,4D,A:,DDB,DDO]
+FLP2[CO,SO,50,3D,E:,DDO]

NONE
NONE
NONE
NONE
NONE

64
64
64
64
64

ALLCON2
ALLCON2
ALLCON2
ALLCON2
ALLCON2

ALLLST
SIOLST
ALLLST
SIOLST
ALLLST

FLP2[EO,SBO,5BO,4D,A:,DDB,DDO]
FLP2[EO,SBO,5BO,4D,A:,DDB,DDO]
FLP2[EO,SBO,5BO,4D,C:,DDB,DDO]
FLP2[EO,SBO,5BO,4D,C:,DDB,DDO]
FLP2[EO,SBO,5BO,4D,A:,DDB,DDO]
+FLP2[CO,SO,50,3D,E:,DDO]

SASll[AO,5BO,2D,E:,DDB,DDO]
SASII [AO,3BO,2D,E:,DDB,DDO]
SASII [AO,5BO,2D,A:,DDB,DDO]
SASII [AO,5BO,2D,A:,DDB,DDO]
SASII [AO,5BO,2D,H:,DDB,DDO]

M/OS-SO-4
Customer Update
(MOS-AP32)
MOS-AP4S
MOS-AP56
MOS-AP64
MOS-AS32
MOS-AS48
MOS-AS56
MOS-AS64
System Release
(MOS-AP64)
MOS-AS64
MOS-DAP6
MOS-DAS6

1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2

2&4
2&4
2&4
2&4
2&4
2&4
2&4
2&4

13

1,2
1,2
1,2

2&4
2&4
2&4

13
13
14

1,2

2&4

14

3,4
3,4
3,4
3,4
3,4

4.0
4.0
4.0
4.0
4.0

9
9

9

PHANTOM
PHANTOM
PHANTOM
PHANTOM
PHANTOM

3,4
3,4
3,4
3,4
3,4

4.0
4.0
4.0
4.0
4.0

12
12
12
12
12

PHANTOM
PHANTOM
PHANTOM
PHANTOM
PHANTOM

9
9
9
13

9
9
9

NONE

M/OS-SO-5
System Release
(MOS-PHM)
MOS-TS
MOS-SK
MOS-TSSK
MOS-FS5

S
S

M/OS-SO -6
System Release
(MOS-HTTF)
MOS-HTSF
MOS-HTTH
MOS-HTSH
MOS-HFS5

): FILE NAMED SYSTEM.COM ON RELEASE DISK
ALLLST: STI OR PIO AT PORT ODOH
CPU MHz 2&4: CALCULATED BAUD RATE AT BOOT-UP 2.5 TO 4.0
PIOLST: MDX-PIO AT PORT ODOH
CPU 1,2 : MDX-CPUI OR MDX-CPU2
SIOLST: MDX-SIO AT PORT ODEH
ALLCONI : UART OR SIO AT PORT ODCH
PHANTOM: PHANTOM BOOTM PROM
ALLCON2: STI AT PORT OBOH OR UART/SIO AT PORT ODCH
PHANTOMX: MODIFIED PHANTOM PROM TO OPERATE NON-PHANTOM
FLOPPY: FLP2[EO,SBO,5B0,4D,A:,SDB,SDO] ~ MDX-FLP2, PORT OEOH, S" BOOT10PERATION, 5;' BOOT10PER, 4 LOGICAL DRIVES, START DRIVE A:,
SINGLE DENSITY BOOT-UP, SINGLE DENSITY OPERATION
HARD DISK: SASll[AO,5BO,2D,E:,DDB,DDO] ~ MDX-SASll, PORT OAOH, 2 LOGICAL DRIVES, START DRIVE E:, DOUBLE DENSITY BOOT, OPERATION

(

VIII-24

J12:

FLP2 STRAPPING LOCATIONS
Figure 1

J3

One ofthe major additions to the MDX-FLP2 is the abilityto
support multiple DMA devices. This capability is accomplished through the implementation of a DMA daisy-chain
which adheres to the STD BUS Practice for mUltiple DMA
devices. Connections to the daisy chain are made on
connector J2. The MDX-FLP1 does not support this feature,
there is generally no need to be concerned with it. It is,
however, a feature that one should be aware of especially if
one plans to have other mass storage interfaces such as an
MDX-SASI2 hard disk interface. Additional information on
this topic can be gained from the 1981 STD BUS
Specification and Practice which is available from the STD
Manufacturing Group. Figure 2 details the pin-out of
connector J2.

J4

1

2

1

2

D

8::r=l
Gl s"r:-:l 1
5~ L:J8"L::J

JS

J7

J6

J8

x

J9

1 2
.---

DAISY CHAIN CONNECTOR
Figure 2

A3
A4
AS
AS
A7

'--J10

EXT Request Level - This jumper determines
whether the EXTREQ input to the FLP2 DMA is
active low or active high. For an active low
EXTREQ, strap pins 2 and 3 (factory setting); for an
active high EXTREQ, strap pins 1 and 2.

'rn

7~1

8~2

11:l

J11

J2-TOPVIEW

J12~

\

J1

(

J5:

Test Points - Test points shown on the schematic
are located on this jumper.

J6:

VCO Clock - This clock is either a 4 MHz (8 inch
drive) or 2 MHz (5% inch drive) clock.

J7:

8 Inch Ready - When using an 8 inch drive, this

PIN NO.
1,3,5,7

Ground

FUNCTION

2

8AI (8us ACK In)

4

8AO (Bus ACK Out)

6

No connection

8

External DMA Request Input

The pin-out of J3 is unchanged therefore the cable used
between the MDX-FLP1 and the disk devices can also be
used with the MDX-FLP2.
SUMMARY

strap connects the READY signa) to FLP2. When
using a 5% inch drive, this strap is not connected.
Thus, 5% drives will always appear ready.
J8:

8 or 5% inch Clock - Strap for either a 4 MHz (8
inch) or 2 MHz (5% inch) clock.

J9:

5% inch drive - This strap is used by Mostek
software to determine whether 5% or 8 inch drives
are used. Only strap J9 for 5% inch drives.

J10:

Port Address Select - This header block is used to
place the FLP2 on any of 32 possible 8-port
boundaries. A jumper installed selects the given
address bit to be a "zero".

J11:

1/0 Expand - 10EXP* is normally not used on
Mostek boards. Thus, the factory straps pins 2 and
3. If the user desires to use 10EXP*, strap pins 1
and 2 plus pins 3 and 4.

The upgrade from an MDX-FLP1 to an MDX-FLP2 should
pose few, if any, problems. The major stumbling blocks are
in the various software options the user has at his disposal.
Table 1 provides a comprehensive cross-correlation
between CPU boards, FLP boards, and software. As
indicated above, the hardware should pose no problems.
Keep in mind, however, that Mostek software usually
expects the system disk drive to be of the 8 inch variety. If it
is desired to have a 5% inch drive as the system drive,
Version 5.0 or greater should be used. Again, this is possible
due to the phantom capabilities of these versions.
REFERENCES
MDX-FLP2 Ops Manual

#4420262

M/OS-80 Ops Manual

#4420064

MOSGEN Ops Manual

#4420270

VIII-25

II

VIII-26

!t

UNITED

COMPUTER
PRODUCTS
DIVISION

TECHNOLOGIES
MOSTEK

MDX-SASI1: THE HARD DISK INTERFACE
APPLICATION NOTE #7
INTRODUCTION
As microcomputer systems have increased in their
complexity, so have their mass storage needs also
increased. It isn't uncommon to see as much as 10 MB of
mass storage attached to an 8-bit microcomputer. Mostek
has responded to this need with the introduction of the
MDX-SASI-1: a Shugart Associates System Interface
(SASITM) bus adapter for the STD-Z80 BUS.
This application note will highlight the features of the SASI
bus as well as provide a fairly comprehensive list of the
controllers and disk drives which are compatible with the
MDX-SASI-1. There will also be a brief discussion of the
versions of M/OS-80 which are designed to utilize the
capabilities of a hard disk. For more in-depth coverage, the
reader should refer to the references listed atthe end ofthis
Application Note.

are those bus devices which perform the operation. A bus
device may have a fixed role as an initiator or target, or the
bus device may be able to assume either role.
Figure 1 shows a simple SASI system composed of two bus
devices; one, the computer, is the initiator and the other, the
control unit, is the target. In this figure the MDX-SASI-1
serves as the host adaptor. This is the most common use for
the MDX-SASI-1 in STD-Z80 BUS systems.

BASIC TWO CONTROL UNIT SYSTEM
Figure 2

SASI
The Shugart Associates System Interface is an asynchronous, parallel bus designed to allow efficient transfer of data
between computers and input/output devices. Due to its
asynchronous nature, SASI allows speed independent
communications. In general. SASI is oriented towards
intelligent I/O devices.
Bus Ports are the lowest level of interface for a SASI system.
There may be a maximum of 8 bus ports for a given SASI
bus. Attached to the bus ports are bus devices which are in
turn attached to the peripheral devices. A 50-pin flat ribbon
cable connects the bus devices. There are 9 data lines and 9
control lines. Each of the 18 lines has a ground trace
between it and adjacent traces to reduce noise sensitivity.
The other traces are reserved for future use. During a
communication session one bus device must be the initiator
and the other must be the target. Initiators are those bus
devices which start an operation on the bus while targets

SIMPLE SYSTEM
Figure 1

Figure 2 shows a more complex system in which there are
two control units. With the MDX-SASI-1 , there can be up to
7 control units. SASI also provides for multiple initiators;
however, MDX-SASI-1 does not support this feature.

HARDWARE
A hard disk system must be composed of 4 hardware blocks.
These blocks are the microcomputer, the bus adaptor, the
hard disk controller, and the hard disk. Table 1 is a list of
some of the manufacturers of hard disk controllers and
drives which Mostek has evaluated and found to be
compatible with MDX-SASI-1. This list is not "all inclusive"
and the reader is urged to survey the trade journals for other
possible vendors. One trend that is beginning to emerge is
that of combining the controller with the drive with a SASI
Bus Interface. Shugart has introduced a series of 8" drives
(floppy and winchester) which support this feature.
Of course, MDX-SASI-1 serves as the bus adaptor. In this
capacity it accepts parallel data from the microcomputer
and sends it down the 50-pin ribbon cable. The pinout of
MDX-SASI-1 allows for the use of a "mass terminated"
ribbon cable. Several manufacturers provide the associated
hardware to build these cables i.e. Ansley, Winchester, etc.

SASITM is a trademark of Shugart Associates.

VIII-27

•

MANUFACTURERS OF HARD DISK CONTROLLERS AND DRIVES
Table 1

CONTROLLER MFG.

514"

DTC-510Al520A

XEBEC 1410

CMS

CM5206, 5412, 5619

SAME

IMI

5006,5007,5012

SAME

RMS

RMS504, 509, 513

SAME

SEAGATE

ST506,412

SAME

SHUGART.

SA602, 604, 606

SAME

TAN DON

TM602S, 603S

SAME

TI

525/62,/61,/122

SAME

S"

DTC-101D

MEMOREX

101 OEM

DRIVE MFG.

SHUGART

DTC-1401.

SA-1ooo

SOFTWARE

MANUFACTURERS

Mostek's M/OS-SO operating system has provisions for
adding hard disk storage to a Mostek microcomputer
system. Release version MK71012C-S1 is designed to
support operation with MDX-SASI-1 and the XEBEC 1410
disk controller board. This particular version is generated to
. utilize the Seagate ST-506 drive or its equivalent.
The hardware set that this version of M/OS-SO is designed
around is composed of: MDX-CPU3 or MDX-CPU4, MDXFLP2, MDX-SASI-1, and the phantom boot ROM. Boot up
can take place from either the floppy disk or the hard disk.
The system contained on the diskette will support up to four
S" floppy disk drives and two 5%" floppy disk drives or three
5%" hard disk drives. There are four other versions supplied
on the release diskette which provide for various mixes of
floppy (S" and 514") and hard disk drives.
For those users wishing to use MDX-SASI-1 in systems
which do not contain an operating system, Appendix A
shows examples of software routines which can be used to
do reads and writes from the hard disk as well as program
the MDX-SASI-1 and select the controller. For detailed
information about the different modes of data transfer on
SASI, consult Shugart's product specification on the SASI
bus.

Computer Memories Corp.
9233 Eaton Ave.
Chatsworth, CA 91311
213-709-6445
Data Technology Corp.
2775 Northwestern Parkway
Santa Clara, CA 95051
4OS-496-0434
Irwin International
2000 Green Road
Ann Arbor, MI 4S1 05
313-663-3600
Memorex Corp.
San Tomas at Central Expressway
Santa Clara, CA 95052
4OS-9S7-1OOO
Rotating Memory Systems
1701 McCarthy Blvd.
Milpitas, CA 95035
40S-946-6692

VIII-28

REFERENCES

Sea gate Technology
360 EI Pueblo Road
Scotts Valley, CA 95066
408-438-6550

MDX-SASI-l Ops Manual #4420263

M/OS-80 Ops Manual #4420064
Shugart Associates
475 Oakmead Parkway
Sunnyvale, CA 94086
408-733-01 00

MOSGEN Ops Manual #4420270
Shugart SASI Product
Specification #30134-0 Rev. A

Tandon Corp.
20320 Prairie
Chatsworth, CA 91311
714-675-2928
Texas Instruments
P.O. Box 202145
Dallas, TX 75220
1-800-231-4717
In TX - 1-800-392-2860

APPENDIX A
MODULE Hardware Interface Routines

.*
.*
.*
.*

Description: This module contains the hardware interface routines required to communicate with MDX-SASI-l. All
routines assume that the AUTO ACK logic (J4) is enabled .

.*

Ver 0.1

.*
.*
,.*

The following are Port definitions as they exist on the MDX-SASI-l board:

.*
.*
.*
.*
.*
.*

.*

A7
x
x
x
x

A6
x
x
x
x

10 Nov 81

A5
x
x
x
x

A4
x
x
x
x

A3
x
x
x
x

A2
x
x
x
x

Al
0
0
1
1

AO
0
1
0
1

PIO
PIO
PIO
PIO

Function
Port A Data (Bidirectional)
Port B Data (Bit Control Mode)
Port A Control
Port 8 Control

Where x = Port Strapping options on the MDX-SASI Board.
Status Control Port Definitions (Port B on PIO):

.*

.*
.*
.*
.*
.*
.*

.*
.*
.*

b7
RES

b6
SEL

b5
ACK

b4
BSY

b3
MSG

I

b2

bl
REO

T

I

bO
1/0

L-

Input/Output (input)
Request (input)
Control/Data (input)
Message (input)
Busy (input)

.*

Acknowledge (input)

.*
.*
.* Note that Port B is programmed for BIT CONTROL MODE.

Reset (output)

Bits bO-b5 are configured for inputs while b7 and b6 are outputs.

VIII-29

Select (output)

·* Port B Bit Control Constants
RES
EOU
80H
;Reset
SEL
EOU
40H
;Select
ACK
EOU
20H
;Acknowledge
BSY
EOU
10H
;Busy
08H
;Message
MSG EOU
CD
EOU
04H
;Control/Data
REO
EOU
02H
;Request
10
EOU
01 H
;Input/Output

.*
.*

r-------------------------------------------------------------------------------,
MDX-SASI-1 Hardware Interface Routine

.*
.* These routines handle reset, selection, status, command, and data to/from the MDX-SASI-1 board. These are the only
.* routines that directly "toggle bits" on MDX-SASI-1. All routines use polled operation (no interrupts or DMA) .

.*

.*

.*
.*
.*

PROCEDURE initialize PIO
Description: Initializes the Z80-P10 for polled operation
with the MDX-SASI-1 board .

.*
.*
.*

Vt;lrO.1

.*

Entry:

C - Base address of MDX-SASI-1 board .

.*

Exit:

AF is changed .

INITPIO

26 Sep 81

EOU $

Set Port A of the PIO for bidirectional (Mode 2) operation.
INC C
;Point to Port A control register
INC C
LD A, 8FH
;Program Port A for
OUT (C),A
mode 2 operation
Set Port B of the PIO for bit control (Mode 3) operation:
INC C
;Point to Port B control register
LD A,OCFH
;Program Port B for
OUT (C), A
mode 3 operation
For Mode 3, the next byte must set the I/O regsiter bits.
Bits 7 and 6 are outputs. Bits 5, 4, 3, 2, 1, and 0 are inputs.
LD A, 00111111 B
OUT (C), A

.*

Initialize MDX-SASI-1 board ...
DEC C
;Point to Data Port B
DEC C
XOR A
;Deassert all control lines
OUT (C),A
DEC C
IN
A, (C)

.*

. ;Point to Data Port A
;Dummy read to enable MDX-SASI-1

That's all for now...

RET
VIII-30

·*

END procedure initialize Pia
PROCEDURE Reset

.*
,.*
.*

Description: Resets the controller connected to the MDX-SASI-1 .

.*
.*
.*
.*
.*
,.*

VerO.1

26 Sep 81

Entry:

C - 8ase address of MDX-SASI-1 board.
If A is 0, Then no errors.
If A is non 0, Then A contains the error code .

Exit:

RESET

EQU $
INC C

;Point to Port B

LD ARES
OUT (C),A

;Assert Reset Signal

XORA
OUT (C), A

;Remove Reset signal

Check if all status lines are deasserted
IN
A (C)
;If status lines deasserted
CP 0
JR Z, OUT
THEN get out
LD A,40H
;ELSE get error code
OUT:

DEC C

;Restore original value of C

RET

;Enough for now...

END PROCEDURE Reset

.*

PROCEDURE select

.*

Description: Selects the controller connected to the MDX-SASI-1 .

.*
.*
.*
.*

VerO.1

26 Sep 81

Entry:

A - ID of controller (normally bit 0 set to 1)
C - Base address of MDX-SASI-1 board

Exit:

AF is changed .

.*

.*

SELECT

WAIT4:

EQU $
OUT (C), A

;Assert ID bit (normally bit 0)

INC C

;Point to Port B

LD A SEL
OUT (C),A

;Assert Select

IN
A(C)
AND BSY
JR Z,WAIT4

;While

XOR A
OUT (C),A

;Deassert Select

•

busy not asserted
wait

VIII-31

DEC C
RET

;Restore original value of C
and exit

.*

END PROCEDURE select

.*

PROCEDURE block read

.*

Description: Reads a block of up to 256 bytes from the MDX-SASI-1 board.

.*
.*
.*
.*

VerO.1

26 Sep 81

Entry:

B - Byte count (Note that a value of 0 is 256).
C - Base address of MDX-SASI-1 board.
HL - Points to first byte of buffer area .

.*
.*

...

A is changed .
B is zero .
HL points one past the last byte read .

Exit:

.*
,.*

...

BLKRD

EOU $

LOOPO:

INC C

WAITO:

IN
A,(C)
;WHILE
AND ACK
acknowledge asserted
JR NZ,WAITO;
wait

WAIT1:

IN
A, (C)
AND REO
JR Z,WAIT1

;WHILE
request not asserted
wait

DEC C

;Point to Port A

INI

;Read a byte

JR
RET

...

;Point to Port B

NZ,LOOPO;

and keep-on till done

;That's all for now

END PROCEDURE block read

VIII-32

PROCEDURE block write

.*

.*
.*

Description: Sends a block of up to 256 bytes to the MDX-SASI-1 board (Polled).

.*
.*

VerO.1

.*

Entry:

26 Sep 81
B - Byte count (Note that a 0 implies 256 bytes).
C - Base address of MDX-SASI-1 board.
HL - First byte of block .

.*
.*

A is changed.
B is zero .
HL points one past the last byte sent.

Exit:

.*
.*

..*

BLKWR

EQU $

LOOP1:

INC C

WAIT2:

IN
A. (C)
;WHILE
AND ACK
acknowledge asserted
JR NZ.WAIT2;
wait

WAIT3

IN
A. (C)
AND REO
JR Z.WAIT3

;WHILE
request not asserted
wait

DEC C

;Point to Port A data

OTI

;Send a byte

JR
RET

.*

;Point to Port B Data

NZ.LOOP1;

and keep-on till done

;Let's get out of here

END PROCEDURE block write

II
VIII-33

vm·34

l'J

UNITED

COMPUTER
PRODUCTS
DIVISION

TECHNOLOGIES
MOSTEK

MDX-FLP2 VS. MDX-FLP1 :HARDWARE AND SOFTWARE ISSUES
APPLICATION NOTE #8

INTRODUCTION

5. On the Type 1 commands the step rate select bits are
assigned differently. Table 3 shows the differences.

With the introduction ofthe MDX-FLP2, the MDX-FLP1 will
become increasingly less cost effective due to the
performance increases ofthe MDX-FLP2. With this in mind,
this application note will detail the differences between
these two products so that present users of MDX-FLP1 can
make the move to MDX-FLP2 with a minimum of effort .

1771 COMMAND SUMMARY
Table 1

HARDWARE

TYPE COMMAND

BITS

Restore
Seek
Step
Step In
Step Out
Read Command
Write Command
I Read Address
II Read Track
III Write Track
IV Force Interrupt

The major differences between the MDX-FLP1 and MDXFLP2 are in the areas of the floppy controller chip, jumper
options, 1/0 port definitions, and miscellaneous board
differences.

Floppy Chip
Probably the biggest single difference between these two
products is the presence of a Western Digital 1771 on
MDX-FLP1 and a Western Digital 1797 on MDX-FLP2. The
1771 is a single-sided, single-density floppy controller/
formatter while the 1797 supports both double-density and
double-sided operation. This is not to imply that the 1797
doesn't support single-density and single-sided operation
as well.

7

6

5

4

3

2

1

0

0
0
0
0
0

0
0
0

0
0

0

1
1

0

0
0

0

1
1
1
1

0

V r,
V r,
V r,
V r,
V r,
E 0
E a,
E 0
1 0
1 0
I,

ro
ro
ro
ro
ro

1
1
1
1
1
1

h
h
h
h
h
b
b

1
1
1
1
1

0

1
u
u
u
m
m

0
0
1
1

0
0
0
13

'2

0
ao

0
s

0
10

1797 COMMAND SUMMARY
Table 2
BITS

The command formats for both the 1771 and 1797 are
virtually identical. Tables 1 and 2 provide a summary of the
command formats for the 1771 and 1797, respectively. The
only differences are as follows:

iTYPE COMMAND

The 1797 allows the selection of a particular side with bit
1 of Type II and Type III commands. The 1771 doesn't
support side select.
2. On the Write Sector command the 1771 allows the
selection of 4 different data address marks where as the
1797 allows only 2.
3. The Read Track command of the 1771 may be
conditionally synchronized with each address mark
through the use of bit 0 of this command. The 1797
always synchronizes with the address marks.
4. Type III commands of the 1797 can have the head
settling delay conditionally enabled. The 1771 always
enables the delay except for the read address command
on which it is an option.
VIII-35

I
I
I
I
I
II
II
III
III
III
IV

Restore
Seek
Step
Step In
Step Out
Read Sector
Write Sector
Read Address
Read Track
Write Track
Force Interrupt

7

0
0
0
0
0
1
1
1
1
1
1

6
0
0
0

5
0
0

1
1

0

0
0

0

1
1
1
1

0

1
1
1
1
1

0

4
0
1
u
u
u
m
m

0
0
1
1

3

2

1

h
h
h
h
h
b
b

V
V
V
V
V
E
E
E
E
E

r, ro
r1 ro
r, ro
r, ro
r, ro
U 0
U ao

'2

'0

0
0
0
13

U
U
U
I,

0

0
0
0

•

stEP RAnis

information on this topic can begained from the>1981 $TO
BUS Specification and Pra~ice.yvhich isavailableJ~p~ the
STD Users G r o u p : " .
. ',.

.

Table 3

8"

STEP RATE
R1 Ro

00
01
10
11

1797
.'

51,4"

1771
,.

1797

·3 rns •..··S.m9· 'Sms
6ms
12 ms
6 ins
10ms
10 ms
20ms
20ms
15 ms
30ms

1771

J2, on the FLP2, is also used to provide for an external DMA
request. This feature allows the DMA chip on theFLP2to be
shared with another peripheral controller such as the MDXSASI1 hard disk interface. Figure 1 details the pin-out of
connector J2.

12ms
12 ms
20ms
40ms

Jumper Options
There is a great deal of similarity between the jumper
options of the MDX-FLP1 and the MDX-FLP2. Table 4
summarizes the correlation betWeen MDX-FLP1 and MDXFLP2. The Timing Resistor (R2) on FLP2 is socketed allowing
easy replacement when adjusting the timing of U2
(74LS221) for the optimum Head Load Timing delay
required by the drive being used.
If R2 equals
6.2 K nHLT = 43 ms
9.1 K nHLT = 64 nis
12 K n HLT= 84 ms

JUMPER CORRELATION
Table 4
FLP1
ADDRESS:
BIT 7 E9
6 E10
5 E11
4 E12
3 E13

51,4"

I/O Ports

FLP1, on the other hand, has bit b4 assigned as the side
select. Port 2, bits 0, 1, and 5 are identical for both FLP1 and
FLP2. FLP2 has Port 2, bit b6 assigned as a "zero" where as
FLP1 has this bit assigned'as a "one". This feature can be
used by software to determine whether aFLP1 or FLP2 is
present.
ADDITIONAL INFORMATION
One ofthe major additions to the MDX-FLP2 isthe ability to
support mUltiple DMA devices. This capability isaccomplished through the implementation of a DMA daisychain which adheres to the STD BUS Practice for multiple
DMA devices. Connections to the daisy chain are made on
connector J2. Since the MDX-FLP1 is unable to support this
feature, there is generally no need to concern oneself with
it. It is, however, a feature that one should be aware of
especially if one plans to have other mass storage interfaces
Such as an MDX-SASI2 hard disk interface. Additional

E1
E2

JS(2,1)
JS(4,3)

HEAD
LOAD
DELAY

S"

PortsO, 1.4,5; 6, and7 arethesameforFLP1 andFLP2. The
only difference being in a few of the status bits on some
commands. Ports 2' and 3 have several differences. The
drive select bits of Port 3 are the same for both FLP1 and
FLP2. FLP2 doesn't have the side select bit but it does have
both a density cpntrol bit and a 1797 reset bit in Port 3. The
density control bit is in location b7 and the reset is in
location b6.

J10(10,9)
J10(S,7)
J1 0 (6,5)
J10(4,3)
J1 0 (2,1)

FLOPPY
CONTRL.
CLOCK

51,4"
S"

The notable differences are lack of Automatic Precompensation on FLP1, no support of 10EXP* on FLP1, and no forced
single/double selection on FLP2.

FLP2

DRIVE
10'
5%"

S"
# SIDES
SINGLE
DOUBLE

DATA
SEP.
5%"

S"
AUTO
PRECOMP'
'5%"

S"
10EXP
If using
If not using
EXTREQ
. LEVEL
HIGH
LOW

V/U-36

ES (OUT)
ES(IN)

R2 is
, socketed

E3(1N)
E3 (OUT)

'J9(IN)
J9(OUT)

E4(1N)
E4(OUT)

N/A (bit 0 of Port 2,
"0" = single sided
"1" double·sided)

E5(OUT)
E5(1N)

J6(4,3)
J6(2,1)

N/A
N/A

J4(OUT)
J4(1N)

N/A
N/A

J11 (1,2 + 3.4)
J11 (2,3)

N/A

J12 (2,1)
J12(2,3)

N/A

=

data separator output to the controller. If one of these drives
is used, the etch run going to pin 48 should be cutto prevent
damage to either the FLP2 or the drive. Figure 2 shows the
pin-out of J3 (J2-FLP1) with differences noted between
FLP1 and FLP2.

DMA DAISY CHAIN CONNECTOR
Figure 1
x

x

x

x

: I:

The final hardware difference is in the area of the reset
circuitry. FLP1 gets its reset from the SYSRESET* line
directly. FLP2 gets its reset directly from SYSRESET* for
everthing exceptthe floppy controller chip. The chip gets its
reset from one of the I/O port bits which is initialized to a
"zero" by SYSRESET*. Therefore, the FLP2 comes up in the
reset state and must be taken out of reset by outputing a
"one" to bit b6 of Port 3. FLP1 comes up in the initialized
state.

J 2 -TopView

PIN NUMBER

FUNCTION

1,3,5,7

Ground

2

BAI (Bus ACK In)

4

BAO (Bus ACK Out)

6

No connection

8

External DMA Request Input

An additional feature of FLP2 is the ability to run at system
speeds of 4 MHz. This speed improvement does not speed
up the transfer rate from the drive but it does allow a mass
storage device to be interfaced to a 4 MHz system.
The pin-out of J3 (J2-FLP1 ) is unchanged except for pin 48,
side select; therefore, the cable used between the MDXFLP1 and the disk devices can also be used with the MDXFLP2. On FLP1, pins 14 and 16 are tied together and
assigned as the side select control line. FLP2, on the other
hand, has pins 14 and 48 tied together for this same
function. In general, this will not cause a problem unless 8·'
drives which provide an internal data separator are used.
(Shugart model #851.) These drives assign pin 48 as the

SOFTWARE
Software differences between FLP2 and FLP1 are relatively
minor. Most of the differences have been detailed in the
hardware section. In summary those differences are the
side select, step rate assignment, data address marks, reset
control, and head settling delay. The lack of 4 data address
marks on FLP2 shouldn't be a problem because most
software only uses the Data Mark(FB) and the Deleted Data
Mark (F8) both of which are supported by FLP2. The other
two supported by FLP1 are user defined and may vary from
routine to routine.
DUAL-DENSITY FORMAT
Table 5

NUMBER
OF BYTES

DRIVE INTERFACE
Figure 2
Signal

Description

Pin Number

Drive Select 1,2,3,4
Side Select
Step
Write Data
Write Gate
Direction
Head Load
Read Data
Index
Trackoo
Write Protect
Drive Ready
2 Sided

Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input

26,28,30,32
14,48 (see note), 1 6*
36
38
40
34
18
46
24 (5 in.) or 20 (8 in.)***
42
44
22
10**

80
12
3
1
50*
r -12
3
1
1
1
1
1
1
22
12
3
1
256
1
_54
598**

NOTE: Some 8" drives have an optional DATA
SEPARATOR output on pin 48. If this is true on your drive,
cut the etch on the FLP2 board going to pin 48 on J3.
* Pin 14 & 16 (FLP1)
Pin 14 & 48 (FLP2)
** only on FLP2
*** Pins 20 and 24 are common (tied together) on FLP1 and
FLP2

*
~*

VIII-37

HEX VALUE OF
BYTE WRITTEN
4E

00
F6
FC (Index Mark)
4E
00
F5
FE (10 Address Mark)
Track Number (0 thru 4C)
Side Number (0 or 1)
Sector Number (1 thru 1A)
01
F7 (2 CRCs written)
4E
00
F5
FB (Data Address Mark)
DATA
F7 (2 CRCs written)
4E
4E

Write bracketed field 26 times
Continue writing until FD179X interrupts out.
Approx. 598 Bytes.

•

Even though the software differences between FLP2 and
FLP1 are not very large, the implications of double-density
operation versus single-density operation should not be
underestimated. First of all, the data comes off the disk
twice as fast as it does for single-density operation. This
increased speed means that for programmed tranfers the
software must be more efficient if there is to be no lost data.
Secondly, the buffers must be twice the size they are for
single-density operation because the sectors are twice as
big.
Another area that the programmer must be aware of is that
of the different format information required for single- and
double-density operation. The single-density formats for
FLP1 and FLP2 are identical. Table 5 shows the format
information for IBM System 34 double-density operation. A
few notable points are the sector length field (field after
sector #), increased length of all gaps, and the different
values placed into the gaps. Table 6 shows the values
placed into the sector length field and what they mean. Note
that this table is only valid when bit b3 of Type II commands
isa "one". If this bit is a "zero", then the sector length field is
treated as non-IBM format and it is beyond the scope ofthis
application note to discuss all the possibilities of nonstandard formats.

SECTOR LENGTH FIELD DEFINITION
Table 6
SECTOR LENGTH TABLE

*
**

Sector Length
Field (Hex)

Number of Bytes
in Sector (Decimal)

00
01
02
03

128*
256**
512
1024

Single density value
Double density value

REFERENCES
FD1771-01 Data Sheet
Western Digital Corp.
FD179X-02 Data Sheet
Western Digital Corp.
MDX-FLP1 Ops Manual #4420032

SUMMARY
MDX-FLP2 Ops Manual #4420262
It is hoped that this application note has provided the user
with sufficient information to make the switch from MDXFLP1 to MDX-FLP2. The majority of the changes are in
hardware and should have minimum effect on the software
for those users who are just using FLP2 as a replacement
for FLP1. Again, to recap the areas of importance:
1. Remember that side selection takes place in the chip for
FLP2 and on the board for FLP1 .
2. 51,4" drives will always appear ready to FLP2.
3. Be aware of the slight differences between command
and status information.
4. There is a fixed head settling delay for FLP2 which may
require an additional software delay for 51,4" drives
unless the value of R2 is changed to increase the setting
delay.

Western Digital Corp.
2445 McCabe Way
Irvine, California 92714
(714) 557-3550
STD Users Group
Bill-Shields - Chairman
8697 Frobisher St.
San Diego, California 92126
(714) 297-1353
STD Manufacturers Group
Matt Biewer - Chairman
Pro-Log Corp.
2411 Garden Rd.
Monterey, California 93940

VIII-3B

!t

UNITED
TECHNOLOGIES
MOSTEK

COMPUTER
PRODUCTS
DIVISION
MDX-CPU3/4 I/O DRIVERS
APPLICATION NOTE #10

SCOPE:

INTERFACING THE SERIAL PORT (J3)

This application note will detail how to control the serial
port, parallel port, and the timer channels available on the
MDX-CPU3 and MDX-CPU4.

The serial communication signals to perform an RS-232-C
type interface have been buffered and pinned out to a
26-pin connector in such a manner that a flat ribbon mass
terminated type connector could be used. Hardware and
software considerations follow below.

INTRODUCTION:
The purpose of this application note is to help the first time
user of the MDX-CPU3/4 interface the serial and parallel
ports quickly. Sample drivers are provided and can be
modified to suit the user's particular needs.

HARDWARE:
Table 1 lists the connections required for the serial port.

SERIAL PORT (J3) PINOUT
Table 1
MDX-CPU3/4 (J3)
Pin #
Signal
1
2
3
4
5
6
7
8
20

GND
RX(BB)
TX(BA)
RTS(CA)
CTS (CB)
DSR (CC)
GND
RLSD (CF)
DTR (CD)

Z80-STI (MK3801)
Pin #
NC
38
11
37
9
10
13
NC
14
12

SI&
13
50
11
12
15

Input
Input
Output
Input
Output
Output

16
14

Output
Input

INTERFACING THE PARALLEL PORT (J2)

MATING CONNECTORS (P31 FOR J3

Flat Ribbon
Type:

SIGNAL DIRECTION
Relative to CPU3/4

The parallel output port has been designed to support a
parallel Centronics type printer interface directly. The port
has been pinned out to a 26-pin connector in such a manner
that a flat ribbon mass terminated type connector could be
used on both ends. Hardware and software considerations
follow below.

11 T & B Ansley # 609-26ooM
21 Winchester Electronics
#51-1126-00
313M #3399-6000

Discrete Wire 1) Winchester Electronics
Housing = #PGB-13-A
Type:
Contacts = #1OO-72020S (20-24AWG)
(Crimp) #1OO-72026S (26-30AWG)

HARDWARE:
Table 2 lists the connections required for the parallel port.

VIII-39

•

SERIAL PORT
Figure 1

INITIALIZE STI
FOR SERIAL PORT
OPERATION

r-----SET BAUD RATE

L ______ _

CONSOLE IN

VIII-40

CONSOLE OUT

PARALLEL PRINTER PORT (J2) PINOUT
Table 2

MDX-CPU3/4 (J2)
Pin #
Signal

1

ISTB

2
3

POO
P01
P02
P03
P04

4

5
6
7
8
9

10
11

2

21
22

23
24

DO
01
02
03
04

P06
P07

28

NC
BUSY
NC

14
15

GNO
GNO

07

8 10

PE

15

SIGNAL DIRECTION
Relative to CPU3/4

Output
Output
Output
Output
Output
Output
Output
Output
Output

TBO

25
26 05
27 06

P05

12
13
16-26

Z80-STI (MK3801)
Pin #

Input
Input

17

NC

MATING CONNECTORS (P2) FOR J2

MATING CONNECTOR FOR PRINTER (36-PIN
CENTRONICS TYPE)

Same as those for J3
Flat Ribbon Type:

1) 3M #3366-1001 (Bail Mount)

PARALLEL PRINTER PORT
Figure 2

NO

HAS
PREVIOUS
CHARACTER BEEN
ACKNOWLEDGED

VIII-41

III

INTERFACING THE TIMERS

TIMER C & D CONTROL REGISTER (TCDCR) PORT7.

There are four timers associated with the STI chip onboard
the MDX-CPU3/4. Timers A & B are full function timers
that can perform basic delay function, event counting, or
pulse measurement. Timers C & D on the other hand are
delay timers only. The timer outputs have been dedicated as
indicated below.

IRE~ET I

Z80-STI (MK3801)
Pin #
1
2
3
4

TAO
TBO
TCO
TDO

CONNECTOR
Pin #

CC21 CC1

I I I
CCO

RE:ET

TimerC
Control Bits

DC21 DC1

I I
DCO

TimerD
Control Bits

. CONTROL BIT DEFINITION

J3-Pin 18 (/TAO) Available for user
J2-Pin 1 (/TBO) Printer Strobe
J3-Pin 11 (/TCO) Available for user
No external conn. Baud Rate
Measurement

TIMER GENERAL COMMENTS
D All timer outputs are forced low by device (board) RESET.
D Only timer A & B outputs can be forced low by setting the

A or B register RESET bit respectively. If this method is
used, the other bits must be maintained in the correct
state as well.
D Timer Data Registers and the main counters will

maintain their contents during a RESET.

C3 C2 C1 CO

o 0 0 0
00 0
001

1
0

0

1
0

o
o
o
o
o

1

1
0

1 0 1
1 1 0
1 1 1
1 000
1 0 0 1
101 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

COMMENT
Timer Stopped
Delay Mode, -;- 4 Prescale
Delay Mode, -;- 10 Prescale
Delay Mode, -;- 16 Prescale
Delay Mode, -;- 50 Prescale
Delay Mode, -;- 64 Prescale
Delay Mode, -;- 100 Prescale
Delay Mode, -;- 200 Prescale
Event Count Mode
Pulse Width Mode, -;- 4 Prescale
Pulse Width Mode, -;- 10 Prescale
Pulse Width Mode, -;- 16 Prescale
Pulse Width Mode, -;- 50 Prescale
Pulse Width Mode, -;- 64 Prescale
Pulse Width Mode, -;- 100 Prescale
Pulse Width Mode, -;- 200 Prescale

D No counting can occur while timer is stopped.

SOFTWARE:

D Timer contents remain unaltered while stopped.
D Residual count in timer is lost when reloaded with a new

General Comments

value.
The following assumptions are made:
1. MDX-CPU3 clock frequency is 3.6864 MHz. (standard)
2. Timer D is used for Baud rate generation.
3. Timer B is used for Printer Strobe.

D In the Delay Mode, the prescaler is always active.
D In the Event Count Mode, the prescaler is disabled.
D Timer count will decrement to 01---then reload value

from data register and toggle output state, during what
normally would be count 00.

Direct Registers are addressed as:
IN
A (STI+register-name)
OUT
(STI+register-name)A

D Two time-out pulses are required for one complete

output

cycle.
Indirect Registers are addressed as:

D If the timer is stopped, the value loaded into the data

register will also be loaded into the counter.
D If the timer is running, data must

LD

A(lnterrupt-vector.AND.11100000B)+register
-name
OUT
(STI+PVR)A
A,(STI+IDR)
IN

be written while the

timer is not counting through 01 H.
D If timer is running, and the prescaler is changed, the first

or

output pulse will be incorrect (0 2':TO::S; 200 clock cycles).
TIMER A & B CONTROL REGISTER (TABCR) PORT 9.

AC31 AC21 AC1
Timer A
Control Bits

I I
ACO

BC31 BC2

I I I
BC1

BCO

TimerB
Control Bits

VIII-42

LD
OUT
LD
OUT

A,(Interrupt-vector.AND.11100000B)+register
-name
(STI+PVR)A
Aregister-value
(STI+IDR)A

STI CHIP REGISTER DEFINITIONS
STI

EQU

OBOH

STI BASE PORT ADDRESS

DIRECT REGISTERS
IDR
GPIP
IPRB
IPRA
ISRB
ISRA
IMRB
IMRA
PVR
TABCR
TBDR
TADR
UCR
RSR
TSR
UDR

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

0
1
2
3
4
5
6

7
8
9
10
11
12
13
14
15

Indirect Data Register
General purpose I/O Interrupt
Interrupt Pending Register B
Interrupt Pending Register A
Interrupt In-Service Register B
Interrupt In-Service Register A
Interrupt Mask Register B
Interrupt Mask Register A
Pointer/Vector Register
Timers A and B Control Register
Timer B Data Register
Timer A Data Register
USART Control Register
Receiver Status Register
Transmitter Status Register
USART Data Register

INDIRECT REGISTERS
SCR
TDDR
TCDR
AER
IERB
IERA
DDR
TCDCR

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

0
1
2
3
4
5
6

7

Sync Character Register
Timer D Data Register
Timer C Data Register
Active Edge Register
Interrupt Enable Register B
Interrupt Enable Register A
Data Direction Register
Timers C and D Control Register

BIT DEFINITIONS
PTRACK
PTRBSY

EQU
EQU

0

7

Input Printer Acknowledge
Input Printer Empty

RTS
CTS

EQU
EQU

1
2

Input Request To Send
Output Clear To Send

RX

EQU

3

DTR
DSR

EQU
EQU

4
5

Input Receive serial data
(for Baud rate measurement)
Input Data Terminal Ready
Output Data Set Ready

RSLD

EQU

6

Output Received Line Signal Detect

DDRVAL
GPIVAL

EQU
EQU

01100100B
OOOOOOOOB

Value for DDR Register
Idle values for General Purpose Port

PTR

EQU

ODOH

Output Printer Data Port Address

BITO
BITl
BIT2
BIT3
BIT4

EQU
EQU
EQU
EQU
EQU

1
2
4

8
16
VIII-43

•

BIT5
BIT6
BIT7

EQU
EQU
EQU

32
64
128

ASCII SPECIAL CHARACTERS
NUL

ETX
EOT
BEL
BS
HT
LF
FF
CR
NAK
CAN
ESC
DEL

DEFL
DEFL
DEFL
DEFL
DEFL
DEFL
DEFL
DEFL
DEFL
DEFL
DEFL
DEFL
DEFL

OOH

03H
04H

07H
08H

09H
OAH
OCH
ODH
15H

18H
1BH

7FH

INITIALIZE THE STI CHIP

STINIT:
01
LD
OUT
LD
OUT

A,DDR
(STI+PVR).A
A,DDRVAL
(STI+IDR).A

just in case

LD
OUT

A,GPIVAL
(STI+GPIP).A

set up the general purpose port

and set up idle values

FIXED BAUD RATE DRIVER

LD
OUT
LD
OUT

A,TCDCR
(STI+PVR).A
A,OOOOOOO1 B
(STI+IDR).A

LD
OUT
LD
OUT

A,TDDR
(STI+PVR).A
A,3
(STI+IDR),A

timer 0 divide by 4 prescale

then divide by 3
the output toggles for each output
giving an effective divide by 2
the USART will divide by 16
thus 3.6864/4/312/16

LD

A,1 0001 oooB

=9600

USART control: divide by 16
8-bitword
async 1 stop
no parity

VIII-44

OUT

(STI+UCR),A

LD
OUT
IN

A,OOOOOOO1 B
(STI+RSR),A
A(STI+RSR)

enable receiver

LD

A,OOOOO1 01 B
(STI+TSR),A
A(STI+TSR)

enable transmitter

OUT
IN
LD
OUT
OUT

A,OOOOOOOOB
(STI+IERA),A
(STI+IERB),A

disable all interrupts

LD

ACR

CALL
LD
CALL

TTYOUT
ALF
TTYOUT

and clear any flags

and clear any flags

AUTOMATIC BAUD RATE DETERMINATION

LOOP1:

LD
OUT
XOR
OUT

A,AER
(STI+PVR),A
A
(STI+IDR),A

Set active register for pulse
width measurement of serial in

OUT

(STI+TABCR),A

Stop timer (just in case)

OUT

(STI+TBDR),A

Initialize counter value

LD
OUT

AOOOO11 01 B
(STI+TABCR),A

set up pulse width mode

LD
OUT
XOR
OUT
OUT
LD
OUT

AIERA
(STI+PVR),A
A
(STI+IDR),A
(STI+IMRA),A
AOOOOOOO1 B
(STI+IDR),A

set up interrupts in STI

LD
OUT
XOR
OUT
OUT
LD
OUT

AIERB
(STI+PVR),A
A
(STI+IDR),A
(STI+IMRB),A
AOOOO1000B
(STI+IDR),A

IN
AND
JR

A(STI+IPRB)
BIT3
NZ,DONE1

clear previous interrupt

clear previous interrupt

look for end of pulse
if end of pulse, exit

VIII-45

•

I

PRINTER INITIALIZATION DRIVER

I

PTRINT:
LD
OUT
LD
OUT
LD
OUT
LD
OUT

A.OOOOOOOOB ; Stop the timer (just in case)
(STI+TABCR).A
AOOOO1000B ; Force the timer low
(STI+TCDCR).A
16 x 10 x 271 nanosec =43 msec
A.16
(STI+TBDR).A
A.OOOOOO10B
intent is that approx 43 msec
(STI+TABCR).A
the printer strobe (timer
will go high

IN
CP
JR

A(STI+TBDR)
15
NZ.WAIT1

Wait for first cycle to stop

IN
CP
JR

A(STI+TBDR)
16
NZ.WAIT2

Wait for second cycle

LD
OUT

AOOOOOOOOB
(STI+TABCR).A

LD
CALL
LD
CALL

ACR
PTROUT
A.LF
PTROUT

WAIT1:

WAIT2:

Then turn off the timer

RET

PRINTER OUTPUT DRIVER

PTROUT:
PUSH

AF

Save Character

IN
BIT
JR

A(STI+GPIP)
PTRBSY.A
Z.BUSY

see if printer is busy
make this paper empty

IN
BIT
JR

A.(STI+GPIP)
PTRACK.A
NZ.ACK

BUSY:
l'

ACK:
see of previous'ack is finished

VIII-46

POP
OUT

AF
(PTRI.A

now output the character

PUSH

AF

save it again

LD
OUT
LD
OUT
LD
OUT

AO
(STI+TABCRI.A
A16
(STI+TBDRI.A
AOOOOOO10B
(STI+TABCRI.A

stop the timer (just in case)

IN
CP
JR

A(STI+TBDRI
14
NZ.WAIT1

wait for first cycle to start

IN
CP
JR

A.(STI+TBDR)
15
NZ.WAITT2

wait for second cycle to start

LD
OUT

AO
(STI+TABCR).A

then turn off timer

POP
RET

AF

16 x 10 x 271 nanosec

=43 msec

intent is that in approx 43 msec
the printer strobe (timer b output)
will go low for approximately
and then go high again

WAITT1:

WAITT2:

SAMPLE PROGRAM
The example program below is a simple one. It inputs a
character from the CRT console. echos the character back
out to the CRT console and outputs the character to the
printer.

.zao
0000'

0080

ASeG
STI

UseZ80Code

;

eau

OBOH

STI BASe PORT ADDRESS

DIReCT REGISTeRS

0000
0001
0002
0003
0004
0005
0006
0007
0008

0009

oooA
oooB
OOOC

lOR
GPIP
IPRB
IPRA
ISRB
ISRA
IMRB
IMRA
PVR
TABCR
TBDR
TADR
UCR

eau
eau
eau
eau
eau
eau
eau
eau
eau
Eau
Eau
eau
eau

0
1
2
3
4
5
6
7

8
9
10
11
12

VIII-47

•

IN
AND
JP

A(STI+IPRA)
BITO
Z,LOOP1

B110:

LD
JR

B,105
DONE2

if overflow, then 110 Baud

DONE1:

IN
NEG
SRL

A(STI+TBDR)
A

get pulse count counted down
from 0
divide by 2 due to timer output

LD

B,11000000B

RLCA
JR
SRL
JR

C,DONE2
B
LOOP2

LD
OUT
LD
OUT

ATDDR
(STI+PVR),A
AB
(STI+IDR).A

output corrected value to
Baud rate generator

LD
OUT
LD
CP
LD
JR
LD

ATCDCR
(STI+PVR),A
AB
105
A,OOOOOO10B
Z,DONE3
A,OOOOOOO1 B

output prescaler

OUT

(STI+IDR).A

LD
CP

AB
105

LD

A10011000B

LOOP2:

DONE2:

DONE3:

;

prepare to correct value

110 Baud?
divide by 10
. else divide by 4

110 or higher?

;

DONE4:

USART control: divide by 16
8 bit word
async 2 stop bit
no parity

JR

Z,DONE4

skip around if 110 baud

LD

A1 0001 OOOB

USART control: divide by 16
8 bit word
async 2 stop bit
no parity

OUT

(STI+UCR).A

LD
OUT
IN

A,OOOOOOO1 B
(STI+RSR),A
A(STI+RSR)

enable receiver
and clear any flags

LD
OUT
IN

AOOOOO101 B
(STI+TSR).A
A(STI+TSR)

LD
OUT
XOR
OUT
OUT
LD
OUT
XOR
OUT
OUT

AIERA
(STI+PCR).A
A
(STI+IDR).A
(STI+IMRA).A
AIERB
(STI+PVR).A
A
(STI+IDR).A
(STI+IMRB).A

CALL

TIYIN

enable transmitter
and clear any flags

disable interrupts

disable interrupts

flush out that first input
character

RET

CONSOLE-IN DRIVER

TIYIN:
IN
BIT
JR

A(STI+RSR)
7.A
Z,TIYIN

Input from receive status
Bit 7 is "receive char available
Wait for character to be received

IN
RES

A(STI+UDR)
7.A

Input the character
Strip parity bit

RET

CONSOLE-OUT DRIVER

TIYOUT:
PUSH

AF

Save the character

IN
BIT
JR

A(STI+TSR)
7.A
ZWAIT

Input the transmitter status
Bit 7 is the "buffer empty bit"
Wait for buffer to be empty

POP
OUT
RET

AF
(STI+UDR).A

Restore character

IN
BIT
RET

A(STI+RSR)
7.A

Input the receive status register
Bit 7 is the buffer full bit
which is set if a character
is received

WAIT:

TIYCHK:

VIII-49

•

;

0060
0060
0061
0061
0063
0065
0067
0068
006A

TTYOUT:
F5

PUSH

AF

OB BE
CB 7F
28 FA

IN
BIT
JR

A,(STI+TSR)
7,A
Z,WAIT

F1
03
C9

POP
OUT
RET

AF
(STI+UOR).A

IN
BIT
RET

A,(STI+RSR)
7.A

WAIT:

BF
;
TTYCHK;

006B
006B
0060
006F

OB BO
CB 7F
C9

0070
0070
0072
0074

OB BO
CB 7F
28 FA

IN
BIT
JR

A,(STI+RSR)
7.A
Z,TTYIN

0076
0078
007A

OB
CB
C9

IN
RES
RET

A,(STI+UOR)
7.A

007B
007B
0070
007F
0081
0083
0085
0087
0089

TTYIN:

3E
03
3E
03
3E
03
3E
03

BF
BF

00
B9

08
B7
10
BA
02
B9

INITIALIZE THE PRINTER
;
PTRINT:
,LO
OUT
LO
OUT
LO
OUT
LO
OUT

A,OOOOOOOOB
(STI+TABCR),A
A,OOOOl000B
(STI+TCOCR).A
A,16
(STI+TBOR),A
A,OOOOOO10B
(STI+TABCR),A

;

008B
oo8B
0080
008F

WAIT1:
OB BA
FE OF
20 FA

IN
CP
JR

A,(STI+TBOR)
15
NZ,WAIT1

;

I

I

t

0091
0091
0093
0095

OB BA
FE 10
20 FA

IN
CP
JR.

A,(STI+TBOR)
16
NZ,WAIT2

0097
0099

3E 00
03 B9

LO
OUT

A,OOOOOOOB
(STI+TABCR),A

009B
0090
OOAO
OOA2

3E
CO
3E
CO

LO
CALL
LO
CALL

A,CR
PTROUT
A,LF
PTROUT

OOA5

C9

OOA6
OOA6

F5

WAIT2:

00
OOA6
OA
OOA6

RET

PTROUT:
PUSH

AF
VIII-50

BUSY:

OOA7
OOA7
OOA9
OOAB

DB Bl
CB 7F
28 FA

OOAD
OOAD
OOAF
OOBl

IN
BIT
JR

A,(STI+GPIP)
PTRBSY.A
Z,BUSY

DB Bl
CB 47
20 FA

IN
BIT
JR

A,(STI+GPIP)
PTRACK.A
NZ.ACK

OOB3
OOB4

Fl
D3

POP
OUT

AF
(PTR),A

OOB6

F5

PUSH

AF

OOB7
OOB9
OOBB
OOBD
OOBF
OOCl

3E 00
D3 B9
3E 10
D3 BA
3E 02
D3 B9

LD
OUT
LD
OUT
LD
OUT

A,O
(STIHABCR).A
A,16
(STI+TBDR).A
A,OOOOOOl DB
(STI+TABCR).A

IN
CP
JR

A,(STI+TBDR)
14
NZ,WAITTl

DB BA
FE OF
20 FA

IN
CP
JR

A,(STI+TBDR)
15
NZ,WAITT2

OOCF
OODl

3E 00
D3 B9

LD
OUT

A,O
(STI+TABCR).A

OOD3
OOD4
OOD5

Fl
C9

POP
RET
END

AF

OOC3
OOC3
OOC5
OOC7
OOC9
OOC9
OOCB
OOCD

ACK:

DO

WAITT1:
DB BA
FE DE
20 FA
WAITT2:

ENCODE:

Macros:
Symbols:
OOAD
0008
OOOD
0064

0004
0004
OOOC
0009

0004
0003

0004
OOFF
0000
0007
0008
0001
OOBO

ACK
BS
CR
DDRVAL
DTR
EOT
FF
HT
IERB
IPRA
ISRB
MAPAD
NUL
PTRBSY
PVR
RST
STI

0003
OOA7
0002
007F
OOD5
00lB
0001
0000
0007
0002
OOOA
0005
OODO
007B
0006
0003
0023

AER
BUSY
CTS
DEL
ENCODE
ESC
GPIP
IDR
IMRA
IPRB
LF
MAPN
PTR
PTRINT
RSLD
RX
STINIT
VIII-51

0007
0018
0006
0005
OOOB
0003
0000
0005
0006
0005
0018
0015

0000
OOA6
OOOD

0000
0009

BEL
CAN
DDR
DSR
ENTRY
ETX
GPIVAL
IERA
IMRB
ISRA
LOOP
NAK
PTRACK
PTROUT
RSR
SCR
TABCR

oooD
oooE
oooF

RSR
TSR
UDR

EOU
EOU
EOU

13
14
15

INDIRECT REGISTERS
0000

0001
0002
0003
0004

0005
0006
0007

SCR
TDDR
TCDR
AER
IERB
IERA
DDR
TCDCR

a

EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU

1
2
3
4
5
6
7

MEMORY MAP CONTROL
0005

MAPN

EOU

5

OOFF

MAPAD

EOU

OFFH

BIT DEFINITIONS
0000
0007

PTRACK
PTRBSY

EOU
EOU

a

0001
0002

RTS
CTS

EOU
EOU

1
2

0003

RX

EOU

3

0004
0005

DTR
DSR

EOU
EOU

4
5

0006

RSLD

EOU

6

0064
0000

DDRVAL
GPIVAL

EOU
EOU

01100100B
OOOOOOOOB

0000

PTR

EOU

ODOH

7

ASCII SPECIAL CHARACTERISTICS
0000

0003
0004
0007
0008
0009
oooA
OOOC
oooD
0015
0018
001B
007F

NUL
ETX
EDT
BEL
BS
HT
LF
FF
CR
NAK
CAN
ESC
DEL

DEFL
DEFL
DEFL
DEFL
DEFL
DEFL
DEFL
DEFL
DEFL
DEFL
DEFL
DEFL
DEFL

OOH
03H
O4H
07H
08H
09H
OAH
OCH
ODH
15H
18H
1BH
7FH
VIII-52

Memory Map #5
Configuration
Memory Map Control
Port Address

0000
0003

21
11

0006
0009
oooB
oooD
OOOF
0012
0015
0018
001B
001E
0021

01 OOCA
ED BO
3E 05
D3 FF
CD 0023
CD 007B
CD 006B
CD 0070
CD 0060
CD OOA6
18 F5

oooB
oooB

ENRTY:

LOOP:

ORG
LD
LD

00
HL,ENTRY
DE,ENTRY

LD
LDIR
LD
OUT
CALL
CALL
CALL
CALL
CALL
CALL
JR

BC,ENCODE-ENTRY
AAMPN
(MAPAD),A
STINIT
PTRINT
TTYCHK
TTYIN
TTYOUT
PTROUT
LOOP

Block Source Address
Block Destination
Address
Block Length
Load Map Number
Set Memory Map

STINIT
STINIT:

0023
0023
0024
0026
0028
002A

F3
3E 06
D3 B8
3E 64
D3 BO

DI
LD
OUT
LD
OUT

ADDR
(STI+PVR),A
ADDRVAL
(STI+IDR),A

002C
002E

3E
D3

00
B1

LD
OUT

AGPIVAL
(STI+GPIP),A

0030
0032
0034
0036

3E
D3
3E
D3

07
B8
01
BO

LD
OUT
LD
OUT

ATCDCR
(STI+PVR),A
AOOOO0001 B
(STI+IDR),A

0038
003A
003C
003E

3E
D3
3E
D3

01
B8
03
BO

LD
OUT
LD
OUT

A,TDDR
(STI+PVR),A
A3
(STI+IDR),A

0040

3E

88

LD

A1 0001 oooB

0042

D3

BC

OUT

(STI+UCR),A

0044
0046
0048

3E 01
D3 BD
DB BD

LD
OUT
IN

AOOOOOOO1 B
(STI+RSR),A
A(STI+RSR)

004A
OO4C
004E

3E 05
D3 BE
DB BE

LD
OUT
IN

AOOOO01 01 B
(STI+TSR),A
A(STI+ TSR)

0050
0052
0054

3E
D3
D3

00
B5
B4

LD
OUT
OUT

A,OOOOOOOOB
(STI+IERA),A
(STI+IERB),A

0056

3E

OD

LD

ACR

0058
005B
oo5D

CD 0060
3E OA
CD 0060

CALL
LD
CALL

TTYOUT
ALF
TTYOUT
VIII-53

•

oooB
0002
006B
OOOC
008B
OOC9

TADR
TCDR
TTYCHK
UCR
WAIT1
WAITT2

OOOA
0001
0070
oooF
0091

TBDR
TDDR
TTYIN
UDR
WAIT2

No fatal error(5)

VIII-54

0007
oooE
0060
0061
OOC3

TCDCR
TSR
TTYOUT
WAIT
WAITT1

IJ

UNITED
TECHNOLOGIES
MOSTEK

COMPUTER
PRODUCTS
DIVISION

PRO-LOG M900 UNIVERSAL PROM PROGRAMMER
WITH THE STD-Z80
APPLICATION NOTE #11
INTRODUCTION
This application note describes the hardware and software
required for programming MOS EPROMs using Mostek
STD-Z80 Bus computer boards with a PROLOG M900
Universal PROM Programmer. A thrirty-two bit I/O module,
the MDX-PIO, is the interface between the PROLOG M900
and the STD-Z80 Bus computer. With the system as
described most MOS EPROMs can be programmed, read,
contents verified against the RAM buffer and contents
modified and then programmed into another PROM using
the memory modify command. Files can be loaded from disk
in binary or in HEX format and then the files can be
programmed into the device that is selected. All operations
are assisted with prompts from a menu driven screen driver.
The driver isn't limited to STD-Z80 computer products as it
is port I/O mapped and can be used on most other computer
systems.
FUNCTIONAL DESCRIPTION
The driver writes data from the computer to the PROLOG
M900 unit, controls the address and data outputs, and then
initiates the program cycle or read cycle. Basically, the driver
manipulates the data and the address/control inputs from
the computer so the PROLOG M900 receives the proper
data to transfer to the target PROM from its internal buffer.
The PROLOG M900 has an internal buffer to load data into.
The buffer size is optional and should be the size of the
largest PROM that is going to be used.
The driver supports 2708, 2516, 2716, 2532, 2732, 2564,
and 2764 EPROMs. It will prompt the user on what
configuration and personality modules for the M900 are
needed with the selected PROM type. Some of the things
the driver and the M900 will do:
(L)oad a file from disk to buffer area.
(M)odify the buffer contents.
(P)rogram PROM.
(R)ead the contents of a PROM into buffer area.
(V)erify the contents of a PROM to the buffer area.
(Q)uit driver and return to operating system.

command directs the data to be loaded in the PROM buffer
within the M900; also, the program command controls the
addressing and control signals needed to setup the M900to
program the PROM. As a support task, the driver can read
PROMs and transfer the contents to the data buffer where
the data can be modified or programmed into another
PROM. The verify command compares the data in the data
buffer and the PROM. If any locations do not match, an error
message will be printed on the console device. After all
tasks are complete or a new pattern is needed from the disk
file, a QUIT command returns the control of the system to
the operating system.
MDX-Z80 Bus Computer
Whereas this software driver can be configured to almost
any computer system via the I/O port map, the Mostek
MDX-Z80 Bus computer products are used as the host
computer system. The system is a 64K disk based system
with Mostek's M/OS-80* operating system. The I/O
interface to the PROLOG M900 is provided by the MDX-PIO
board. The MDX-PIO is a 32-bit parallel I/O board with TIL
compatible outputs/inputs. The MDX-PIO communicates
with the M900 through the parallel port provided as a
factory installed option by PROLOG. The system needs to be
at least a 32K operating system. The boards used with the
driver are detailed below.
MDX-CPU1A (MK77855)
The MDX-CPU 1A is a Z80 computer with 4K bytes of PROM
sockets. The disk control firmware and the boot monitor are
located on the board in the two 24-pin PROM sockets. The
actual strapping is described in the appendix section.
MDX-DRAM32A (MK77761)
The MDX-DRAM32A is a memory board with 32K x 8 bytes
of dynamic RAM that can be located on any 4K boundary.
The system consists of two DRAM32As strapped at 0000
and 8000H. In addition, the upper RAM board has the 4K
notch option enabled to stop any memory contentions
between the CPU and the RAM boards. Strapping details
are described in the appendix.
MDX-FLP2 (MK77677)

The driver allows files that are stored on disk to be retrieved,
the data is then loaded into memory and transferred to the
PROM via the M900. The Memory command allows data to
be altered or tabulated in the data buffer, then transferred to
the PROM with the program command. The program

The MDX-FLP2 is a controller for interfacing the STD-Z80
Bus to floppy disk. The MDX-FLP2 allows double- or singlesided and single- or double-density 8-inch or 5\4-inch
floppy driyes.

VIII-55

III

PROLOG M900 Universal PROM Programmer

MDX-SI02 (MK71670)
The MDX-SI02 is a serial communications board that
provides the console interface and the printer port. The
MDX-SI02 has two independent asynchronous or
synchronous serial 1/0 channels. Strapping information is
described in the appendix.
MDX-PIO (MK77650)
The MDX-PIO is a 32 bit paraliellnputlOutput board that
provides the total interface between the host computer and
the PROLOG M900 Universal PROM Programmer. The
MDX-PIO has four eight-bit 1/0 ports with handshake lines.
The detailed strapping information is described in the
appendix.
M/OS-SO Operating System (MK71010CS1)

The PROLOG Universal PROM Programmer can program
many different types of bipolar PROMs and MOS EPROMs.
This application note and driver will deal with MOS
. EPROMs. The EPROM type selected has a personality
module and configuration module. The driver will prompt
the user on which module it expects. If the wrong module is
in place, an error will be printed and the BELL will sound.
The M900 interfaces to the host computer through a
parallel port that is a factory installed option. The port
provides a handshake routine for transferring data either to
or from the COPY socket of the M900 PROM programmer.
Connection is made via a 25-pin D-type connector. The
interface has eight parallel bits for input data, eight bits for
output data, and six bits for handshake and control lines.

M/OS-80 is a C/PM* compatible operating system.
*C/PM is a trademark of Digital Research Corp.

PARALLEL INTERFACE DEFINITION
Figure 1
I NTERLOC K'
MODE'
T RANSFER

I

.

N
T

COMPUTER

WRITE DATA 8 - b i t s _

1/0 PORT

REA o DATA 8 - b i t s -

PROLOG

R

M900

R ESPONS E*

F

ERROR'

A

.

ADDRESS
GND ...

E

C
E - ~GND

SI GNALGN 0

• LOW ACTIVE SIGNALS

PARALLEL INTERFACE PINOUT
Table 1

PIN

INPUTS

8
6
13
10
9
7
12
11
2
3
5

WRITE DATA 8*
WRITE DATA 7*
WRITE DATA 6*
WRITE DATA 5*
WRITE DATA 4*
WRllE DATA 3*
WRITE DATA 2*
WRITE DATA l '
TRANSFER*
MODE*
INTERLOCK*

OUTPUTS

PIN

SIGNAL

22 . READ DATA 8*
21 READ DATA 7*
24 READ DATA 6*
23 READ DATA 5*
18 READ DATA 4*
17 READ DATA 3*
20 READ DATA 2*
19 READ DATA 1*
15 ADDRESS*
14 ERROR*
16 RESPONSE*

1

+5 VOLTS"

PIN

•• The signals are not used in this application.

VIII-56

25
4

LOGIC GND**
-12 VOTS"

PRLOG Driver Considerations

DESCRIPTION OF OPERATION

The driver is a M/OS-80 compatible program. It is invoked
by typing the programs file name "PRLOG" and then a
carriage return (CR). The driver is approximately 5K and
reserves RAM from 2000H to 3FFFH forthe data buffer area
to store data read from a PROM or loaded from a disk drive, a
2764 EPROM requires 8K for its data area. The operating
system expects the area from OFFOOH to OFFFFH to be
reserved for the system scratch-pad area. The minimum
system requires a 32K system with the previous areas
reserved for the driver. In addition, the driver uses the 1/0
port addresses OA8H to OAFH as the MDX-PIO ports.

After the driver is loaded, the driver will prompt for the type
of device, 2708, 2516, 2716, 2532, 2732, 2564, or 2764.
After the device is selected, the driver will prompt the user
with the personality and configuration modules as a
reminder. Also at this time, the driver is establishing
handshaking with the M900. If the handshake routine does
not take place, and error message wil be displayed at the
console and the console bell will sound until the RESET on
the PROLOG M900 is pressed. The error condition should
be removed with the reset; if not, check the setup and
configuration modules to make sure the correct ones for the
device are in place.

PRLOG DRIVERS MEMORY MAP

L-Load a specfied file
P-Program a PROM

Figure 2

256

"

,

OFFOOH

" SCRATCH P A D " " ' "

BYTES
OFOOOH

~

<

SK

~~~~~~~~~~~~~~~~~~~~~~~~~~

3FFFH

"""""""""""""
""""""""""""'"

2000H

""""""''''''''''''''''''
"""""",",""''''''''''
""'"''''''''''''''''''''''
~~~~~~~~

5K

Enter type of action required (L,R,P,V,M,Q)?

)

"""""""""""""
""""""""',""""
~~~~~~~~ DATA BUFFER ~~~~~~~~
""""""',"",,"""
""""""',""""""

PRLOG. COM

M-Modify or tabulate
memory

After the operation needed is selected, the driver will
prompt the user for additional information it may require to
complete the task selected. The information needed is
detailed below.
LOAD Command
12FFH

The load command is used to bring a file from the disk. The
file has to be specified when the PRLOG driver is invoked.

~~~~~~~~~

"""""""""'"','','''
"""""""""'"''''''''
'"''''''''''''''''''''''''''
"''''''''''''''''''''''''''''

R-Read data from a PROM
V-Verifiya PROM against
memory
Q-Exit from program

A. PRLOG filename.ext (CR)
100H

PRLOG . . . . . . . . . . . . . . . .. Drivers name,
filename.ext ............. file to be loaded form disk
and the extension of .COM
or .HEX.
(CR) .......... , ......... carriage return

PRLOG PORT MAP
Figure 3

FF
DO

"""'"''''''''''''

CONSOLE 8< PRINTER
PORT

AS

' " ' ' ' ' ' ' ' ' ' ' ' ' ' ' ",",,,,

COMMUNICATIONS
PORT WITH M900

The file name is stored until additional information is
provided to load the data into the data buffer. The user must
specify whether the file is in a binary or hexadecimal format.
The driver has a hex loader for the hex files.
If the prompt for the type of action is an "L" and the file is
specified, a prompt for the PROM loading address will be
issued to the console. If a file is not loaded, then the
following error message will be displayed at the console:
"**File name was not entered before load**"
The driver will have to be reinvoked and the file name
loaded with it.

00

VIII-57

•

The buffer area is limited to the size of the EPROM being,
programmed. For example, a 2716 has a max buffer size of
2K, so the relative load address is anywhere from 0000 to
7FFH. Typically, the response is zero (0) in almost all cases.

address and the contents along with the ASCII characte~s
displayed beside the data line. A period will terminate the
printing to the console device.
QUIT Command

The next prompt asks for the File load address and is asking
for the starting location of the file to be loaded. The file will
load only the amount of the data buffer. Again, using the
2716 as an example, only 2K of the file will be loaded into
the data buffer. So ifthe file to be loaded is over2K in length,
it will require repeated loads to get all the file into the
EPROMs. After the prompts are answered, the driver will
access the disk and load the data according to the
parameters entered from the prompts. The driver will reissue the command prompt. A P-Program command or a
V-Verify command typically follows the load.

PROGRAM Command
The PROGRAM command will transfer any data in the data
buffer to the EPROM in the COPY socket of the M900 unit.
The user will be prompted for PROM start'location, where
the data goes in the EPROM itself, again relative to zero (0).
There is an optional PROM stop location. With multiple
loads and the PROM startl end information many programs
can be loaded into one PROM. This is very important when
trying to use the larger format EPROMs.

READ Command

The QUIT command returns the system to the operating
system.

OPERATIONAL HINTS
Saving the Data Read from a PROM
This is a suggested routine to save the data onto a disk unit.
After reading the data from a ,PROM with the READ
command, the data is stored in the data buffer from 2000H
to the end of the buffer which is determined by the PROM
type selected. A 2732 would end its buffer at 2FFFH, so the
complete PROM data would be from 2000H to 2FFFH. After
the READ command has finished, use the QUIT command
to return the system to the operating system. With the EXEC
command of M/OS-80 execute the DDT monitor by typing:
A. EXEC E11 0 (CR)
The"." (period) prompt will be displayed. This is the prompt
for the DDT monitor. The data is still in memory and needs to
be transferred to memory location 1OOH to save disk space.
Using the copy command of DDT type:
. C 2000,XXXX, 100 (CR)

The READ command reads the data out off a PROM in the
COPY socket ofthe M900 PROM programmer and transfers
the data to the data buffer. The data can then be transferred
to a PROM with the PROGRAM command or looked at and
modified with the Memory command, using the "Save"
command of M/OS-80 or C/PM* to save the data on the
disk media.

C-COPY.... memory contents from start-stop location.
2000.... The starting location of the data buffer.
XXXX.... The ending location of the data in the data buffer.
100.... The target load address.

VERIFY Command
The VERIFY command reads the data in a PROM in the
COPY socket of the M900 and compares the contents
against the data buffer. If any differences are noted, the
address of the bad data with the read and expected data are
displayed to the console device. A period will stop the
display from advancing if many locations are noted. The
period is used as a terminator for most of the other
commands as well.

After the prompt returns type: .E 0 (CR)
This will return the system to the operating system. After
the operating system prompt appears, use the SAVE
command to save the data on to the disk. The format of the
command under M/OS-80 is as follows:
A. SAVE nn [8:]filename.com (CR)

MEMORY Command

nn .... Is the number of 256 byte blocks to be saved.

The MEMORY command is a valuable aid in correcting or
tabulating PROMs. After getting the data from a PROM or
disk file into the data buffer with a READ command or a
LOAD command, the data can be tabulated to the console
device by entering and "M" (CR) and answering the
memory startlstop prompt. To modify a memory location,
the single location to be modified is entered with no stop
address and then the carriage return after the "M"
command is entered. The MEMORY command shows the

[8:1.... The unit of the drive the data is to be saved on.

VIII-58

PROGRAMMING MANY PROGRAMS ON A PROM

M - Display or update
memory

The best way to program several programs into one PROM
is to use the XFER command of M/OS-80 to append the
files to be programmed into one file. The format is:

Enter type of action required (L,R,P,V,M,Q):M

Q - Exit from the program

Enter starting address Lending address]:O.l F
0000 19228A 12 CD EO OA DA 76 OA CD 7F OA CD A2 OA

A.XFER [options] [B:]newfile.ext=[B:]file1.exUile2.ext, ....
filen.ext (CR)

." ...... v .......

Then with the "newfile", follow the LOAD instructions and
PROGRAM the PROM as needed.

'Looked at first 16 bytes of the 2nd 2K loaded'
L - LOAD a specified file
P - Program data to PROM

EXAMPLES

M - Display or update
memory

PRLOG TEST. COM
Enter PROM type nnnn [2708, 2516, 2716, 2532, 2732,
2564, or 2764]:2716

Enter type of action required (L,R,P,V,M,Q):R
Read complete

SETUP THE PROLOG PROGRAMMER WITH THE

R - Read data from a PROM
V - Verify a PROM against
memory
Q - Exit from the program

'The contents of a PROM in the copy
socket read'

PM9064 and PA24-1 PERSONALITY MODULES.
L - LOAD a specified file
P - Program data to PROM

AND THE 2048 CONFIGURATION PLUG.
L - LOAD a specified file
P - Program data to PROM
M • Display or update
memory

R - Read data from a PROM
V - Verify a PROM against
memory
Q - Exit from the program

M - Display or update
memory

R - Read data from a PROM
V - Verify a PROM against
memory
Q - Exit from the program

Enter type of action required (L,R,P,V,M,Q):P

Enter type of action required (L,R,P,V,M,Q):L

Enter PROM starting, [ending address]:0,7FF 'Program new
data in PROM'

Enter file type - "B" for Binary or "H" for Hex:B

Program complete

'PROM data transferred to new
PROM'

Enter PROM load address (PROM offset):O
L - LOAD a specified file
P - Program data to PROM

Enter starting file address, [.file ending address]:O
File load completed

'1 st 2K offile was loaded from disk'

L - LOAD a specified file
P - Program data to PROM
M - Display or update
memory

R - Read data from a PROM
V - Verify a PROM against
memory
Q - Exit from the program

M - Display or update
memory

Enter type of action required (L,R,P,V,M,Q):V
Verify complete

'contents of PROM compared with data
buffer'

L - LOAD a specified file
P - Program data to PROM

Enter type of action required (L,R,P,V,M,Q):L

R - Read data from a PROM
V - Verify a PROM against
memory
Q - Exit from the program

Enter file type - "B" for Binary or "H" for Hex:B

R - Read data from a PROM
V - Verify a PROM against
memory
Q - Exit from the program

Enter PROM load address (PROM offset):O

M - Display or update
memory

Enter starting file address, [.file ending address]:800

Enter type of action required (L,R,P,V,M,Q):Q

File load completed

'2nd 2K of file was loaded from disk'

L - LOAD a specified file
P - Program data to PROM

R - Read data from a PROM
V - Verify a PROM against
memory
VIII-59

A.

'Return to the operating system'

II

APPENDIX A
STRAPPING OF PIO
J2

J3

1- 2
17-18
23-24

3-4 (OA8H)
7-8

Change U6 from 74LS243 (as shipped from the factory) to a 74LS242.
STRAPPING OF FLP2
J2

J4

J6

J7

J8

J9

N/C

1-2

1-2

1-2

3-4

N/C

J10

J11

J12

1-2
3-4

2-3

2-3

The above strapping is for a single-sided eight-inch disk drive.
STRAPPING OF THE CPU1 A

J2/U5

J3

3-5
6-7
8-9

N/C

J4/U10

11-14
10-12

EPROMs MK6235 and MK6340 should be in the PROM sockets U6 and U7.
STRAPPING OF THE CPU2A
J3

J4

J5

J6

J7-J8

J9-J12

3-4

N/C

3-4

N/C

1-8
2-3
4-5
7-9

1-8
3-9
4-5
6-7

PROMs MK6235 and MK6340 should be in the PROM sockets U7 and U8 and 1K static RAMs in the other four sockets.
DRAM32/32A
1 st DRAM (OOOOH)

2nd DRAM (8000H)
U28

U28

A-a
O-E
H-J

A-a
closed
closed
closed
closed

1
2
3
4

D-E
H-J

VIII-60

open
closed
closed
closed

1
2
3
4

SI02 STRAPPING
RS232 (DCE)
Channel A:

Channel B:

J3

J7

1- 2
11-18
12-17
13-20
14-21
15-22
16-19

1-2
3-4

J4

J7

1- 2
11-18
12-21
13-20
15-22
16-19

5-6
17-8

J8

J9
5-6 (ODCH)

7-8 (9600 Baud)
open (19200 Baud)

J8
15-16 (9600 Baud) or
9-10 (1200 Baud)

APPENDIX B
CABLE INFORMATION

25 D-type
Plug

PIN

PROLOG M900
SIGNAL

PIN

MDX-PIO
SIGNAL

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

+5VDC
TRANSFER*
MODE*
-12 VDC
INTERLOCK*
WR DATA 7*
WR DATA 3*
WR DATA 8*
WRDATA4*
WRDATA5*
WR DATA 1*
WR DATA 2*
WR DATA 6*
ERROR*
ADDRESS*
RESPONSE*

J2-23
J2-16
J2-18
J2-3
J2-5
J2-17
J2-19
J2-6
J2-4
J2-8
J2-20
J2-7

B7
A6
A2
A7
A3
A4
AO
A1
A5
B2
B1
BO

17
18
19
20
21
22
23
24
25

RD DATA 3*
RD DATA 4*
RD DATA 1*
RD DATA 2*
RD DATA 7*
RD DATA 8*
RD DATA 5*
RD DATA 6*
GROUND

J1-18
J1-5
J1-19
J1-6
J1-16
J1-3
J1-17
J1-4
J1-14

A2
A3
AO
A1
A6
A7
A4
A5
GND

26-Pin discrete
header

N/C

J2-22
J2-10

B5
B6

N/C

*Low Active Signal

VIII-61

II

PORT MAP OF DRIVER

J2

PlO#1
PORTA
PORTA
PORTB
PORTB

DATA
CONTROL
DATA
CONTROL

PORTA
PORTA
PORTB
PORTB

DATA
CONTROL
DATA
CONTROL

AS
A9

AA
AB

J1

PIO#2

AC
AD
AE
AF

VIII-62

1983 COMPUTER PRODUCTS DATA BOOK

•••••

~

•••• u " •• "

•• M

••••

, ••••• , .

,,~

••

~

~

IJ

UNITED

SOFTWARE
PRODUCTS

TECHNOLOGIES
MOSTEK

FLEXIBLE DISK OPERATING SYSTEM - M/OS-SO

USER FEATURES

M/OS-SO provides a direct migration path to CP/M
compatibility without any changes tothe system hardware.

o Virtual CP/MTM compatibility gives the user many
available programs to choose from.

o

Additional utilities and systems commands provide
incre.ased capability and functionality to the user.

o

Provided on standard media for use with Mostek
standard systems and MD Series boards for short system
integration time.

SYSTEM FEATURES
M/OS-SO is a more sophisticated and powerful floppy disk
operating system than any other micro-operating system
available. It provides the user with a unique, but invisible,
library structure. By assigning one system disk as a Master
library disk, the system can free the user to place all
application-related files on another disk while still having
the utility of the various system programs on-line.

INTRODUCTION

Unlike other operating systems, M/OS-SO provides the
user with comprehensive error messages. In most cases,
methods of recovery are displayed and the operator is given
several options from which to choose.

M/OS-SO is a CPIMTM compatible, floppy disk operating
system for the MD or SO series of microcomputer board
systems. It offers a comprehensive solution to a wide variety
of systern design problems. The software is provided on an
S-inch single-sided, single-density floppy diskette which
can be booted on Mostek disk-development systems or
user-configured systems (see "Hardware Required"
paragraph). M/OS-SO can be altered for different
inputloutput hardware configurations by using the
MOSGEN Utility (sold separately).

HARDWARE REQUIRED
M/OS-SO is currently supplied in three versions. V3 is
deSigned to run on Mostek's MATRIX systems and on
systems built with MD Series boards. An MD Series system
must contain the following boards:

Several powerful utilities are provided with M/OS-SO.
These programs give the user a broad base of support and
will improve design efficiency. These include:

Item
Processor
Console Interface
Printer Interface
Floppy Interface
Memory

Editior (Edit)
Designer's Development Tool (Debugger)
Transfer Utility (XFER)
FilelDisk Dumps (DSKDUMP)
Print Utility (PRINT)
. Print Spooler (SPOOL)
. Several System Utilities

The V5 system is for use with a Mostek Phantom PROM
system configuration. The following boards are required:

Because of M/OS-SO's CP/M compatibility, a large
number of pre-written programs are avai.lable. M/OS-SO is
designed to run programs written for other CP/Mcompatible operating systems, such as CDOSTM, I/OSlM,
and SDOSTM, provided these programs conform to, the
standards described by Digital Research in .versions 1.4
through 2.2. Virtually all compilers and interpreters.now
sold for use on CP1M (versions 1 .4 -2.2) will work. For those
Mostek customers who are currently running FLP-SODOS,
CP1M is a Trademark of Digital Research. ·Inc.
COOS is a Trademark of Cromemco, Inc.

Hardware Required
MDX-CPU1 or MDX-CPU2
MDX-EPROM/UART or MDX-SIO
MDX-PIO or MDX-SIO
MDX-FLPl or MDX FLP2
(2) MDX-DRAM with 64K of RAM

Item
Processor
Floppy Interface
Memory·

,Hardware Required
MDX-CPU3 or MDX-CPU4
MDX-FLP2
(2) MDX-DRAM with 64K of RAM
(required only for MDX-CPU4)

The V6 system is for use with a Mostek Phantom hard-disk
system. The following boards are required:
SDOS is a Trademark of SO Systems, Inc.
I/OS is a Trademark of Infosot! Systems. Inc.

IX-1

Item
Processor' ...
Floppy Interface
Memory
,
H.ardDisk,. .
Interface

Hardware Required
MDX-CPU3 or MDX-CPU4
MDX-FLP2
(2) MDX-DRAM with 64K of RAM
(required only for MDX-CPU4)

Delete a line(s) or characterts), .
Put a block of tellt into another. file' .'
Get a b'ICek Oftext'from ai\plher file
View text on the console IlCirt!eif
Print text on the line printer
Create a set of commands which can be executed
asarnacro

: MDX-SASI1& MDX-SASI2

With either the V3, V5 or V6, M/OS"80 requires 64K bytes
of RAM for operation, Four bootstrap PROMs are supplied
with V3, and one bootstrap PROM is supplied with V5 orV6,
The system initially mList have at least one 8-inch, singlesided, single-density floppy disk drive in order to boot-up
M/OS-80. Up-to-four disk drives are supported. The V6
configuration can also boot-up from hard disk.

XFER - Trensfer Utility
The XFER program is a general-file transfer utility. It all~
for the moving of files from disks or devices to other (or the
same) disks or devices. The XFER features include:
TranSfer an ASCII file
Compare two files without moving
Filtero\Jt iiiegal ASCII characters
Conditionally transfer a file (user prompted)
Transfer a Read-Only file
Expand tabs
Verify files after"moving
Print HEX address of comparison failure
Transfer only old files
Transfer only new files

Table 1 details the peripheral and CPU configurations
required for the M/OS-80 versions.

M/OS~~O CONFIGURATION SU!IIIMARY
Table 1

PERIPHERALS

CPU,' CPU2 CPU3 CPU4*

UART Console
SIO Console
STI Console
SIO Line Printer
PIO Line Printer
STI Une Printer'
FLP1
FLP2
SASI

V3
V3
V3
V3
N/A.
N/A
V3**
V3**
V3
V3
N/A
N/A
V3
V3
V3*** V3***
*
*

N/A

N/A,
N/A'

N/A,
N/A

V5/6 " V5/6
V5** 16 V5** 16
N/A

N/A

V5/6

V5/6

N/A

N/A
viv6
va

V5/6
V6

The DSKDUMP prOgram allows reading or modifying of a
file, the disk data area;'.or the disk directory. Each block
requested is read into a.128-bytebuffer, then displayed. The
blocks are numbered' sequentially. Any block can be
selected; displayed, modified, and written back to the disk.
PRINT - Print Utility.

Not Applicable.,.
Future Design.
SID line printer configuration issupplied as alternate
on systems disk.,
Single-density only.'

NOTE:
1. MOSGEN Utility may be purchasedto configure systems for different peripherals
and smaller sizes of RAM. See the MOSGEN Data Sheet for more inform&!ion.

EDIT - Text Editor
The ASCII EDITor file provided with M/OS-80 provides a
text editor for users who do rlot have access to a screeneditor. The editor allolllis creation and modification of the
text files by several easy-to~usecommands. EDIT features
inClude:
Find a text String
Change a text string
Find a line
Insert new text

DSKDUMP - Disk Dump

The PRINT utility formats ASCII files to the CRT or printer
with automatic headings, tabbing and pagination. Userspecified options include page width and length, page
headings, date printed of the top of each page, and page
formatting.
SPOOL - Print Spooler
The SPOOL file system f~ature is used to output a file from
the printer to a system list device while the system
continues with other functions. Any ASCII file may be spoolprinted, and direct printer activity is prevented while a spoolprint is active.
other System Utilities
M/OS-SO provides several other system utilities to permit a
user the highest degree of flexibility in the manipulation of
the files and programs created and used with the system.
Some of these utilities include: programs to format disks,
change disk labels, examine directories, and to diagnose
disk probiems: A PROM programming utility is also included
that interfaces with Mostek's PPG 8/16.

: IX-2

ORDERING INFORMATION
DESIGNATOR

DESCRIPTION

PART NO.

M/OS-SOV3

One diskette containing all M/OS-SO programs in binary, four
bootstrap PROMs, and one Operations Manual. (See Table 1 for
hardware configuration requirements.) Requires the signed
Software License Agreeement (enclosed) with purchase order.

MK71010C-S1

M/OS-SOV5

One diskette containing all M/OS-SO programs in binary, one
bootstrap PROM, and one Operations Manual. (See Table 1 for
hardware configuration requirements.) Requires the signed
Software License Agreement (enclosed) with purchase order.

MK71 011 C-81

M/OS-SOV6

One diskette containing all M/OS-SO programs in binary, one
PROM for booting from floppy or hard disk. and an Operations
Manual. (See Table 1 for hardware configuration requirements.)
Requires the signed Software License Agreement (enclosed)
with purchase order.

MK71012C-81

M/OS-SO
Operations
Manual

Detailed description of the operation and use of the
M/OS-SO software package.

4420064

MOSGEN

System generation utilities and device drivers, data sheet

442026S

MSO/LBO
BASIC-SO
BASCOM
FORTRAN-SO

Microsoft language packages, data sheet

4420309

AIM-ZSO

In-circuit-emulation for ZSO, data sheet

4420245

III
IX-3

IX-4

I!t

UNITED

SOFTWARE
PRODUCTS

TECHNOLOGIES
MOSTEK

MOSGEN UTILITY
MK71001
USER FEATURES
o Adapts M/OS-SO to customized MDX and SD systems.

MOSGEN is supplied on two single-sided, single-density
S-inch diskettes. They are the System Generation diskette
and the Device DriverslLibrary diskette.

o Allows tailoring M/OS-SO for different I/O devices and
RAM sizes.

MOSGEN OPERATION
The MOSGEN package creates a batch submit (.CMD) file
which, when executed, walks the system through the
complex re-assembly, trial linkage, and final linkage process
automatically and without operator intervention. The last
steps of the MOSGEN-created batch file test the newlycreated system for errors in linkage, size, and conformity to
system restrictions. The user-supplied drivers are linked
into the main core of the system during this linkage process.
A special linkage editor is provided for the sole purpose of
this system generation link. MOSGEN proves itself useful, if
not essential, when system restrictions limit the amount of
available RAM in the target system, or require the use of
non-standard peripherals or special-intelligent 1/0 drivers.

o Works on systems configured around the DDTIDCF
PROMs or Phantom PROM.
o Menu driven format to speed the configuration process.

DESCRIPTION
Mostek's MOSGEN Utility is a system generation package
used to generate unique configurations of the M/OS-SO
Operating System, MOSGEN allows the user to modify the
M/OS-SO by rewriting existing 1/0 drivers or creating new
drivers for specialized 1/0 operation, and configuring
different system RAM sizes.

MOSGEN may be used to configure M/OS-SO for different
sizes of RAM in the user system down to a minimum of24K
bytes.

MOSGEN allows creation of a command file which will link
a newly customized system. The MOSGEN package also
includes a set of object and source files to provide the user
with a valid set of device drivers. These drivers are provided
to help the user create new drivers based on knownworking examples. Users are permitted to modify or select
drivers for the following logical-unit devices:

•
•
•
•
•
•
•

MOSGEN SYSTEM REQUIREMENTS
MOSGEN and all related software require the userto have a
running 64K M/OS-SO system in place. Depending on the
requirements of the users development languages, the
system memory requirements may be in excess of the 32K
bytes of RAM required for a minimum M/OS-SO system.

System Console (output)
Keyboard (input)
List
Punch
Reader
Disk
Clock

1~-5

. ORD~RII~G INfORMATION

DESCRIPTION

PART NO ..'

MOSGEN'Utility.

Two diskettes containing MOSGEN system generation utilities
and device drivers. both source and object files. and one
Operations Manual. A signed Software License Agreement is
required with purchase order.

MK71 001 c-ao

MOSGEN
Operations Manual

Detailed description of the operation and use of the MOSGEN
Utility.

4420270

. DESIGNATOR'

IX-6

IJ

UNITED
TECHNOLOGIES
MOSTEK

SOFTWARE
PRODUCTS

ASM-68000 STRUCTURED
MACRO CROSS ASSEMBLER
LlNK-68000 RELOCATING LINKAGE EDITOR
FEATURES
o Absolute or relocatable code generation

o

Uses Motorola mnemonics and addressing

o

Enhanced macro and conditional assembly capability

o

Structural statements:
IF-THEN-ELSE
FOR-DO
LOOP-ENOL

REPEAT -UNTIL
WHILE-DO
EXIT

o

Complex expression evaluation

o

Source code, symbol table and cross-reference listing

o

Includes Relocating Linkage Editor

GENERAL DESCRIPTION
Mostek's ASM-68000 Structured Macro Assembler is a
powerful software package which enables the user to
develop application programs for MK68ooo-based microcomputer systems. ASM-68000 translates assembly
language source statements into relocatable object code for
the LlNK-68000 Relocating Linkage Editor, which in turn
combines them into an absolute load module suitable for
loading into the AIM-68ooo.

ASM-68000
The basic goals of ASM-68ooo are: (1) to provide the
programmer with the means to translate assembly
language source statements into relocatable object code
(for the Linkage Editor); and (2) to provide a printed listing
containing the source language input, assembler object
code, and additional information (such as error codes, if any)
useful to the programmer. 68000 assembly language is a
collection of mnemonics and symbols representing 68000
machine instructions, assembler directives, macros,
symbolic names (labels), operators, and special symbols.

™OEC, PDP, RSX, VAX, and VMS are trademarks of Digital Equipment
Corporation.
IX-7

ASM-68OOO uses Motorola-compatible mnemonics, addressing modes, and expression syntax. Numerous
enhancements have been made in the ASM-68000 macro
and conditional assembly capability, as compared to the
Motorola assembler.
ASM-68ooo produces a relocatable object module which
contains information enabling LlNK-68ooo to combine
modules and assign new sets of memory locations.

LlNK-68000
LlNK-68ooo accepts object modules generated by ASM68000 and combines them into an absolute load module.
The user may specify up to four "segments" of memory. For
example, ROM code could be contained in a segment
separate from RAM data. Up to 16 relocatable sections, plus
absolute and named common sections (limited only by
available memory space), may be allocated among the
segments. Comprehensive listing output options are
provided, including a load map, externally defined symbols,
undefined symbols, multiply defined symbols, segment
lengths, and error counts. Extensive control of LlNK-68000
is provided interactively at link time, including module order,
address assignment, resolution of undefined references,
and generation of listings.

OPERATING ENVIRONMENT
ASM-68000 and LlNK-68000 are supplied on DOS-11
formatted magnetic tape (800 bpi) in compiled object form,
ready to link and run on DEC PDP-11 under RSX-11 M, or
VAX under VMS in compatibility mode. A minimum user
partition of 64K is required. Command files for automated
installation are provided.

ORDERING INFORMATION
DES.IGN~TOR.

DESCRIPTION

PART NUMBER

ASM-68000

68000 Structured Macro Cross Assembler, with manuals,
includes LlNK-68000, for RSX-11 M (or VAXNMS
in compatibility mode

MK71020C-33

ASM-68000

Documentation package for above

MK71020D

RADIUS

Remote Development Station data sheet

4420194

AIM-68000

Application Interface Module data sheet

4420316

IX-8

I!I

UNITED
TECHNOLOGIES
MOSTEK

SOFTWARE
PRODUCTS

MICROSOFT MBO/LBO MICROSOFT BASIC-BO MICROSOFT BASCOM MICROSOFT FORTRAN-BO -

MK71002
MK71003
MK71004
MK71005

FEATURES

BASIC-80

o M/OS-80 development aids for Z80 microcomputer

BASIC-80 is the most extensive implementation of BASIC
available for the Z80 microprocessor. In three years of use, it
has become the world standard for microcomputer BASICs,
meeting the requirements for the ANSI subset standard for
BASIC, and supporting many unique features rarely found
in other BASICs.

o

CP/MTM compatible

o

Macro assembler

o

Relocating linking loader

o

BASIC interpreter and compiler

o

FORTRAN compiler

o

Common relocatable object format-link modules in
different languages

BASCOM
Microsoft's BASIC compiler (BASCOM) is a powerful new
tool for programming BASIC applications or microcomputer
system software. The single-pass compiler produces
extremely efficient, optimized machine code that is in
standard Microsoft relocatable binary format. Execution
speed is typically 3-1 Otimes faster than interpreter BASICs.
The Mao/LSD assembler/linker package is included with
BASCOM.

INTRODUCTION
A series of Microsoft program development tools are now
available from Mostek. They offer a comprehensive solution
to a wide variety of system and application design problems.
The software is provided on 8-inch single-sided singledensity floppy diskettes and operates under M/OS-80.

FORTRAN-SO
Microsoft's FORTRAN-80 package provides new capabilities for users of Z80 microcomputer systems.
FORTRAN-80 is comparable to FORTRAN compilers on
large mainframes and minicomputers. All of ANSI standard
FORTRAN X3.9-1966 is included except the COMPLEX
data type. Therefore, users may take advantage ofthe many
application programs already written in FORTRAN. The
M80/LBO assembler/linker package is included with
FORTRAN-80.

M80/LBO
M80 is a relocatable macro assembler for Z80 microcomputer systems, incorporating almost all "big computer"
assembler features without sacrificing speed or memory
space. The M80/LSO package is comprised of the M80
assembler, L80 linking loader, and a cross reference utility.

Portions of this data sheet are copyrighted by Microsoft, Inc.
CP/M is a trademark of Digital Research, Inc.

IX-9

ORDERING INFORMATION
D.ESIGNATOR

DESCRIPTION

PART NUMBER .

MSO/LaO

Relocating macro assembler/linker on diskette.
with operations manual

MK71002C-SO

BASIC-SO

BASIC interpreter pn diskette. with operations manual

MK71003C-SO

BASCOM

BASIC compiler on dis~ettewith operations manual
(includes MSO/L80)

MK71004C-SO

FORTRAN-SO

FORTRAN compiler on diskette. with operations manual
(includes MSO/LaO)

MK71005C-SO

M/OS-SO

CP/MTM compatible disk operating system data sheet

4420271

IX-10

I!I

UNITED

SOFTWARE
PRODUCTS

TECHNOLOGIES

MOSTEK

CRASM-70
3870 CROSS-ASSEMBLER

FEATURES
o Assembles standard 3B70 and FB source

system. The Mostek MATRIX-BO/SOS disk development
system can be used for stand-alone assembly arid debug
capability, with the AIM-7X plugged directly into the
system. The assembler object module may also be
downloaded from a M/OS-80-based system to a Mostek
RADIUS development system containing an AlM-7X.

o Produces absolute load module in FBHEX format
o Runs under M/OS-SO on any Mostek disk system
o Produces complete assembly listing to disk or printer

CRASM-70 produces an assembly listing which can be
directed to a disk file or directly to the M/OS-80 LST: list
device (printer). The listing shows program address,
machine code, and line number for each statement, along
with each source program statement. Any errors which are
found in the source program are indicated in the listing. A
symbol reference table is printed at the end ofthe listing. Up
to 500 symbols may be used in the source program.

o Produces symbol reference table
DESCRIPTION
The Mostek 3B70 Cross Assembler (CRASM-70) runs
under the M/OS-80 operating system, and assembles
standard 3B70/F8 assembly language. The output is an
absolute object file (load module) in F8HEX format. A
conversion utility is provided to convert F8HEX files to
Mostek Hex for use with the AIM-7X in-circuit-emulator

CRASM·70 is supplied on a standard 8-inch single-sided
single-density CP/M-compatible diskette, precompiled,
ready to run under M/OS-BO.

M/OS-BO, RADIUS, and MATRIX are trademarks of Mostek Corporation
CP/M is a trademark of Digital Reserach Corporation

IX-"

ORDERING INFORMATION
.','

DESIGNAtOR

DESCRIPTION

PART NUMQEFi

c'RASM~70

~870/F8 Cross,Assembler, runs under M/OS-80, on
8" SSSD diskette, with manual

MK71007C-80

CRASM-70

Documentation package for above

MK71007D

RADIUS

Remote Development Station data sheet

4420194

AIM-7XE

Application Interface Module data sheet

4420246

IX-12

Il

UNITED

TECHNOLOGIES
MOSTEK

SOFTWARE
PRODUCTS
SOFTWARE MODULAR LIBRARY

FEATURES

DESCRIPTION

o

Software subroutines/modules supplied in source form

o

Software modules supplied for STD-Zao MDX-Modular
Board Series
• MDX-CPU1/2/3/4
• MDX-PIO
• MDX-UART
• MDX-SI01/2/422
• MDX-FLP1/2
• MDX-SASI1/2

The Mostek Software Modular Library is a set of software
subroutines/modules which provide example programs for
users of STD MDX boards. Each module is supplied in
source form in Z80 assembly language. Complete
documentation is included as comments in the source
program which describes the interface, operation, and use
of the module. Adaptation of the example program to the
user's specific hardware configuration is the user's
responsibility. All general/standard MDX I/O interfaces are
included in the software modules.

o Software modules supplied for zao chip set
•
•
•
•
•

o

MK3881
MK3882
MK3883
MK3884/SI7
MK3801

The Modular Library is supplied on M/OS-80 single-sided,
single-density 8-inch diskette. A file named "READ. ME" is
supplied with the product which gives a general description
of each module. This file can be listed to the console or
printer. A complete printed listing is also supplied with the
product. M/OS-80 and a zao assembler such as
Microsoft's M80/L80™ package is required.

PIO
CTC
DMA
SIO
STI

General Software Modules
• PROM Programmer software for PROLOG M900
Programmer

The printed listing may be ordered separately for those
users who do not have access to an operational disk system.

o Assembly language source supplied on M/OS-80™
diskette

o

M/OS-80 and CP/MTM Z80 compatible

o

Designed for ease of modification by user

o

Clear documentation provided in source

•

CP/M is a trademark of Digital Research Corporation.
M/OS-SO is a trademark of Mostek Corporation.
MaO/LSO is a trademark of Microsoft Corporation.

IX-13

ORDERING INFORMATION
:.'

..
r

D~S~NATO/:l
.MODLIB

,

MODUB Listing

.

DESCRIPTION

One M/OS-SO di.skEltte cQntE!ining the Software Modular Library

:

....: . source. Printed source listing: Is Included.

{-

: PAA,TNO.··

MK71009C-80
MK71009D

Printed source listing only.

';:"

IX-·14

1983 COMPUTER PRODUCTS DATA BOOK

Integrated Digital Systems

:

"!;.'

!t

UNITED

COMPUTER
PRODUCTS
DIVISION

TECHNOLOGIES
MOSTEK

MK8200
GENERAL PURPOSE MEMORY
FEATURES

MK8200
Figure 1

o 64 MB capacity with ECC
72 MB capacity without ECC
o 64 bit word width
o 100 ns/word sequential data rate
400 ns random access cycle time
o Four dynamically switchable refresh modes
o Unidirectional or bidirectional data bus
o Single bit correct, double bit detect capability
o Front panel access to internal error log
DRead and,write capability to internal check bits
o Automatic check bit validation
o Rugged steel chassis
Two piece connector system for enhanced reliability
Integral fan pack and power supply

The MK8200 memory system family, designed with the
user in mind, is highlighted by a microprocessor-controlled
front panel which allows centralized system interrogation
via hardware or software control. Four dynamically
selectable refresh modes include asynchronous (cycle hold
off), external (external timing/internal address), synchronous (external timing/external address) and hidden (with
refresh overhead hidden in an eight-way sequential
addressing requirement).

o High capacity power distribution to support burst refresh
requirements

INTRODUCTION
Mostek's MK8200 memory system family is based on an
architecture that permits maximum flexibility, with a
capacity of 4 to 72 megabytes and word widths from 16 to
72 bits. Common piece parts can be easily reconfigured to
fulfill a wide variety of applications, including such fieldproven applications as fixed-head disk replacement, main
memory, video buffers, digital telephone switching, and
data acquisition and processing. The result is custom
system performance without the problems normally
encountered with "one-of-a-kind" approaches.

Additional user-friendly features include card slot(s) inside
the chassis for user control logic, mUltiple voltage power
distribution available to support multiple logic families, and
check bit validation which automatically writes memory to
establish good ECC check bits. Convenient signal probe
points and probe grounds are available throughout the
system.

Designed around Mostek's MK4564 64K dynamic RAM,
the MK8200 family gives you up to 72 megabytes of
memory in a single, 15.75-inch rack-mountable chassis.
Plus, all the logic necessary to support 256K RAMs is
already in place, allowing for future "x4" densities without
costly redesign. Performance features include 400 ns
random cycle and access times, plus the abilityto mix reads
and writes at a 100 ns sequential data rate.

The Mostek MK8200 family, housed in a rugged steel
chassis, is specifically designed for reliability and ease of
maintenance. All cards feature a two-piece connector
system which provides enhanced mechanical and electrical
integrity over card-edge types. A high-capacity power
distribution supports the peak power demands of full-speed
operation and burst refresh modes. Ball bearing fans
X-1

· feature fan rotation sensors with warning circuitry, and the
system has a two-level ambient overtemperature warning
and shutdown feature.
Maintainability is .assured by power supply "in-tolerance"
monitoring, built-in ECC, a built-in error log with isolation to
the physical RAM location, and an optional diagnostic card
to perform a full system check.

mUlti-layer design that provides user access to auxiliary
power distribution as well as standard system voltages. The
card's top edge.can handle up to 10 ribbon cable connectors
for interfacing the card to the user or toother cards in the
MK8200 system. In addition, the socket array area holds up
to 250 16-pin packages; to allow user-inserted sockets, the
MK8171 card is available unpinned, or fully pinned with
hollow pin socket contacts.

HARDWARE

SPECIFICATIONS

Array Card

Storage Capacity (with ECC)

Mostek's MK8200 general-purpose memory system is
based on the MK8100 array card, which features a full
capacity of 3 MS, using industry-standard Mostek MK4564
64K dynamic RAMs. Compatibility of the MK81 00 array
card with 256K dynamic RAMs will allow for future "x4"
offerings.

Standard Capacity: t
Up to 32 MB (four-way interleave)
Up to 48 MB (two-way or no interleave)
Extended Capacity: t
Up to 64 MS (four-way interleave)
Word Width

The MK8100 array card has no user qptions; each card's
address is determined by the motherboard slot into which it
plugs. In addition, the card's flexible architecture allows full
system population at 24-, 48- and 72-bit internal word
widths.
Timing and AddressControl Card
The MK811 0 timing and address control card provides all
system timing, including four dynamically switchable
refresh modes, a high-speed pipeline architecture and
mUltiple-user interface protocols. The MK8110 card also
features automatic check bit validation, a port for the
optional diagnostic card, and an error log with locations for
every RAM device in the system.

Up to 64 bits plus ECC (always 8 ECC bits)
Modes of Operation
Read
Write
Read/ merge/write
Refresh (four modes)
Sequential Data Rate
100 ns per word (read or write)*
Random Read or Write Cycle Time

Data and Error Correction Control Card

400 ns maximum*

The MK8111 data and ECC card completes the control card
set. With error correction enabled, this card provides singlebit correction and double-bit detection of all memory device
errors. Other important features include a fully independent
read-and-write path architecture that supports unidirectional
or bidirectional operation, high-speed pipeline data paths,
serial-byte write and partial word-merge capabilities, realtime error status with the error syndrome and flags provided
at read access time, and a port for the optional diagnostic
card.

Read Access Time
400 ns maximum* at chassis interface
Refresh Cycle Time
400 ns maximum* (refresh may be hidden)
Input Receivers
High-impedance TTL

System Extender Card
Output Drivers
The MK8170 extender card features closely controlled
circuit impedance plus a provision to move the motherboard
termination to the end of the extender, allowing the card to
be used at full system throughput speeds. Additional
features include integral card guides to support extended
cards, plus convenient probe signal and grounding points.

Two sets of up to 72 Single-ended lines

Universal Wrapped-Wire I/O Card

Data Output

The MK8171, a universal wrapped-wire card, features a

Two sets of up to 72 single-ended lines

X-2

Tri-state and open collector
Data Input

Address Inputs

Thermal Shock

27 lines and three controller addresses

30°C/hour maximum

Physical Size

Humidity

Height: 15.75 inches
Depth: 23.60 inches
Width: 17.62 inches (flanges meet dimensional requirements for standard 19-inch RETMA rack)

10% to 90% without condensation
AC Power Requirements
11 5 ± 10% 47Hz - 63 Hz. 30 A Max.
or
220 ± 10% 47Hz - 63 Hz. 15 A Max.
(power consumption depends on configuration and
application)

Temperature
Storage: -4Q°C to +80°C
Operating: O°C to 50°C inlet ambient (unrestricted)

tExtended capacities are achieved by reducing the number of card slots
available for userwoption control boards and increasing the number of memory
array card slots. Chassis size is unaffected.

DISPLAY PANEL
Figure 2

Fan and Cooling
Waming

Diagnostic

Controller
Selection

~
" ...

....""~''''.'
"lIa,
.... ,;

,/;'"

"

\

:

Recessed Circurt Breaker

Diagnostic Keypad Entry

BUser-Accessible
Switches and LEOs

On-LineiOff-Line
Switch

Front Panel
Reset

Box Address
Selection

ORDERING INFORMATION
The Mostek MK8200 is a family of high density. high performance memory subsystems. Many system configurations are
available; these are detailed in the individual product descriptions. This section provides an overall numbering scheme for
the MK8200 family. The available configurations are described by a three-part number, as defined below:

-==r-'- TTl

ProductFamily _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

MK82aa b - c - d e

J

External Bus Configurations
Control Panel Configuration and Voltage
Data Word Width
Word D e p t h - - - - - - - - - - - - - - - - - - - - - - - - - - - - - J

X-3

MK8200 PRODUCT FAMILY DESCRIPTION
Field aa is a two - digit field which comprehends the following variables:
1.
2.
3.
4.

Chassis Size
Internal Bus Structure (Maximum Word Width and Capacity)
Performance Thresholds which· affect RAM type and/or Array Card Quantities
Custom Configurations

These numbers will be assigned sequentially as systems are configured, using the following as a starting point:
-10 Series
-30 Series
-50 Series

72 Bit Internal
48 Bit Internal
24 Bit.lnternal

Existing Product Families are defined in the chart below:

MK8200 PRODUCT FAMILY CHART
InterLeaving

RAM Type

18 Arrays =6 M Word
(Standard Capacity)

4-Way

150 ns

72 Bits

24 Arrays =8 M Word
(Extended Capacity)

4-Way

150 ns

15.75"

12 Bits

18 Arrays = 6 M Word
(Standard Capacity)

None*

200ns

MK8221

15.75"

72 Bits

24 Arrays =8 M Word
(Extended Capacity)

None*

200 ns

MK8230

15.75"

48 Bits

16 Arrays =.8 M Word
(Split System)

4-Way

150 ns

MK8231

15.75"

48 Bits

24 Arrays = 12 M Word
(Extended Capacity)

4-Way

150 ns

MK8232

15.75"

48 Bits

24 Arrays = 12 M Word
(Extended Capacity)

None *

150ns

Product
Family

Chassis
Size

Internal Bus
Width
Depth

MK8210

15.75"

72 Bits

MK8211

15.75"

MK8220

* All MK8200 Systems will support4-Way interleaving if a sufficient population of memory exists. Systems denoted by a "*"
may not support interleaved operation at minimum populations.

. ;~:

X-4

m

UNITED
TECHNOLOGIES
MOSTEK

Mostek Corporation, 1215 West Crosby Rd.
Carrollton, Texas 75006 USA; (214) 466 -6000
In Europe, Contact: Mostek Brussels
270-272 Avenue de Tervuren (BTE21)
B-1150 Brussels, Belgium; Telephon e: 762.18.80

PRINTE D IN USA March 1983

Copyright 1983 by Mostek Corpo ration
A ll rights Reserved



Source Exif Data:
File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19
Create Date                     : 2017:07:02 11:58:41-08:00
Modify Date                     : 2017:07:02 12:47:04-07:00
Metadata Date                   : 2017:07:02 12:47:04-07:00
Producer                        : Adobe Acrobat 9.0 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:5f4dde5f-d466-0041-a6f2-81dfc67b2115
Instance ID                     : uuid:95242ac5-4fdc-4047-8223-261d9ddea78e
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 534
EXIF Metadata provided by EXIF.tools

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